Datasheet UCC1919, UCC2919, UCC3919 Datasheet (UNITRODE)

Download

Page 1

查询UCC1919供应商

3V to 8V Hot Swap Power Manager

FEATURES

Precision Fault Threshold

•

Charge Pump for Low RDS

•

Drive Differential Sense Inputs

•

Programmable Average Power Limiting

•

Programmable Linear Current Control

•

Programmable Fault Time

•

Fault Output Indicator

•

Manual and Automatic Reset Modes

•

Shutdown Control w/Programmable

•

Softstart Undervoltage Lockout

•

High Side

DESCRIPTION

The UCC3919 family of Hot Swap Power Managers provide complete power management, hot swap, and fault handling capability. The UCC3919 features a duty ratio current limiting technique, which pro vides peak load capability while limiting the average power dissipa tion of the external pass transistor during fault conditions. The UCC3919 has two reset modes, selected with the TTL/CMOS com patible L/R pin. In one mode, when a fault occurs the IC repeatedly tries to reset itself at a user defined rate, with user defined maximum output current and pass transistor power dissipation. In the other mode the output latches off and stays off until either the L/R pin is re set or the shutdown pin is toggled. The on board charge pump circuit provides the necessary gate voltage for an external N-channel power FET.

application

INFO

available

UCC1919 UCC2919 UCC3919

• Electronic Circuit Breaker Function

BLOCK DIAGRAM

VDD

CSP

CSN

IMAX

IBIAS

UVBIAS

GND

Note: Pins shown for 14-pin package.

07/99

FLT

VDD

50mV

1.5v

VDD

OVERCURRENT

COMPARATOR

– +

36µA

+ –

1.5V

0.5V

+ –

1.2µA

LINEAR

CURRENT

AMPLIFIER

+ –

200mV

SRQ

OVERLOAD

COMPARATOR

DOMINANT

5 6

LR SD

– +

SET

SRQ

RESET

CHARGE

PUMP

UVBIAS

DRIVER

FLT

VDD

UVLO

CAP

GATE

FLT

UDG-98123

Page 2

ABSOLUTE MAXIMUM RATINGS

VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V

Pin Voltage

(All pins except CAP and GATE). . . . . . –0.3V to VDD + 0.3V

Pin Voltage

(CAP and GATE) . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V

PL Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mA to –10mA

IBIAS Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 3mA

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C

Currents are positive into, negative out of the specified termi nal. Consult Packaging Section ofDatabook for thermal limita tions and considerations of package.

CONNECTION DIAGRAMS

DIL-14, (Top View) N, J Packages

IMAX

IBIAS

N/C

CAP

L/R

FLT

SOIC-16, TSSOP-16 (Top View) D or PW Package

UCC1919 UCC2919 UCC3919

CSP

VDD

CSN

GND

GATE

A =TJ.

CSP

VDD

CSN

GND

GATE

N/C

ELECTRICAL CHARACTERISTICS:

IMAX

IBIAS

Unless otherwise specified, VDD = 5V, TA = 0°C to 70°C for the UCC3919, –40°C

N/C

CAP

L/R

N/C

FLT

to 85°C for the UCC2919 and –55°C to 125°C for the UCC1919. All voltages are with respect to GND. T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Supply

Supply Current VDD = 3V 0.5 1 mA

VDD = 8V 1 1.5 mA

Shutdown Current SD

= 0.2V 1 7 µA

Undervoltage Lockout

Minimum Voltage to Start 2.35 2.75 3 V Minimum Voltage after Start 1.9 2.25 2.5 V Hysteresis 0.25 0.5 0.75 V

IBIAS

Output Voltage, (0

A < I

< 15 A) 25°C, referred to CSP 1.47 1.5 1.53 V

OUT

Over Temperature Range, referred to CSP 1.44 1.5 1.56 V

Maximum Output Current 12 mA

Page 3

UCC1919 UCC2919 UCC3919

ELECTRICAL CHARACTERISTICS:

to 85°C for the UCC2919 and –55°C to 125°C for the UCC1919. All voltages are with respect to GND. T

Unless otherwise specified, VDD = 5V, TA = 0°C to 70°C for the UCC3919, –40°C

A =TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Current Sense

Over Current Comparator Offset Referred to CSP, 3V ≤VDD ≤8V –55 –50 –45 mV Linear Current Amplifier Offset V

= 100mV, Referred to CSP,

IMAX

–120 –100 –80 mV

3V ≤VDD ≤8V

= 400mV, Referred to CSP,

IMAX

–440 –400 –360 mV

3V ≤VDD ≤8V

Overload Comparator Offset V

= 100mV, Referred to CSP,

IMAX

–360 –300 –240 mV

3V ≤VDD ≤8V CSN Input Common Mode Voltage Range Referred to VDD, 3V ≤VDD ≤ 8V, (Note 1) –1.5 0.2 V CSP Input Common Mode Voltage Range Referred to VDD, 3V ≤VDD ≤8V, (Note 1) 0 0.2 V Input Bias Current CSN 15µA Input Bias Current CSP 100 200 µA

Current Fault Timer

CT Charge Current V CT Discharge Current V On Time Duty Cycle in Fault I

= 1V –56 –35 –16 µA

= 1V 0.5 1.2 1.9 µA

= 0 1.5 3 6 %

CT Fault Threshold 1.0 1.5 1.7 V CT Reset Threshold 0.25 0.5 0.75 V

IMAX

Input Bias Current V

= 100mV, Referred to CSP –1 0 1 µA

IMAX

Power Limiting Section

Voltage on PL I

On Time Duty Cycle in Fault I

and L/R Inputs

= –250µA, Referred to VDD –1.0 –1.4 –1.9 V

= –1.5mA, Referred to VDD –0.5 –1.8 –2.2 V

= –250µA 0.25 0.5 1 %

= –1.5mA 0.05 0.1 0.2 %

Input Voltage Low 0.8 V Input Voltage High 2V L/R Input Current 136µA

Internal Pulldown Impedance 100 270 500 k

FLT Output

Output Leakage Current VDD = 5V 10 µA Output Low Voltage I

= 10mA 1 V

OUT

FET GATE Driver and Charge Pump

Peak Output Current V Peak Sink Current V

= +15V, V

CAP

= 5V 20 mA

GATE

= 10V –3 –1 –0.25 mA

GATE

Fault Delay 100 300 nS Maximum Output Voltage VDD = 3V, Average I

VDD = 8V, Average I Charge Pump UVLO Minimum Voltage to

Start

VDD = 3V 6.5 7.5 V

VDD = 8V 6.5 8 V Charge Pump Source Impedance VDD = 5V, Average I

= 1µA 8 10 12 V

OUT

= 1µA 121416 V

OUT

= 1µA 50 100 150 kΩ

OUT

Note 1: Guaranteed by design.Not 100% tested in production.

Page 4

PIN DESCRIPTIONS

CAP: A capacitor is placed from this pin to ground to fil

ter the output of the on board charge pump. A .01µFto

0.1µF capacitor is recommended .

CSN: The negative current sense input signal. CSP: The positive current sense input signal. CT: Input to the duty cycle timer. A capacitor is con

nected from this pin to ground, setting the off time and the maximum on time of the overcurrent protection cir cuits.

FLT

: Fault indicator. This open drain output will pull low

under any fault condition where the output driver is dis abled. This output is disabled when the IC is in low cur rent standby mode.

GATE: The output of the linear current amplifier. This pin drives the gate of an external N-channel MOSFET pass transistor. The linear current amplifier control loop is in ternally compensated, and guaranteed stable for output load (gate) capacitance between 100pF and .01µF. In applications where the GATE voltage (or charge pump voltage) exceeds the maximum Gate-to-Source voltage ratings (V Zener clamp may be added to the gate of the MOSFET. No additional series resistance is required since the internal charge pump has a finite output impedance of 100k

GND: The ground reference for the device. IBIAS: Output of the on board bias generator internally

regulated to 1.5V below CSP. A resistor divider between this pin and CSP can be used to generate the IMAX volt age. The bias circuit is internally compensated, and re quires no bypass capacitance. If an external bypass is required due to a noisy environment, the circuit will be

) for the external N-channel MOSFET, a

typical.

UCC1919 UCC2919 UCC3919

stable with up to .001µF of capacitance. The bypass must be to CSP, since the bias voltage is generated with respect to CSP. Resistor R2 (Figure 4) should be greater than 50k ance of the IBIAS pin on the IMAX threshold.

IMAX: Used to program the maximum allowable sourcing

current. The voltage on this pin is with respect to CSP. If the voltage across the shunt resistor exceeds this voltage

the linear current amplifier lowers the voltage at GATE to limit the output current to this level. If the voltage across the shunt resistor goes more than 200mV beyond this voltage, the gate drive pin GATE is immediately driven

low and kept low for one full off time interval.

L/R: Latch/Reset. This pin sets the reset mode. If L/R is

low and a fault occurs the device will begin duty ratio cur rent limiting. If L/R is high and a fault occurs, GATE will go low and stay low until L/R is set low. This pin is inter

nally pulled low by a 3µA nominal pulldown.

PL: Power Limit. This pin is used to control average power dissipation in the external MOSFET.If a resistor is connected from this pin to the source of the external MOSFET, the current in the resistor will be roughly proportional to the voltage across the FET. As the voltage across the FET increases, this current is added to the fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the average power dissipation in the FET.

: Shutdown pin. If this pin is taken low, GATE will go

low, and the IC will go into a low current standby mode and CT will be discharged. This TTL compatible input

must be driven high to turn on.

VDD: The power connection for the device.

to minimize the effect of the finite input imped

APPLICATION INFORMATION

The UCC3919 monitors the voltage drop across a high side sense resistor and compares it against three differ ent voltage thresholds. These are discussed below. Fig ure 1 shows the UCC3919 waveforms under fault conditions.

Fault Threshold

The first threshold is fixed at 50mV. If the current is high enough such that the voltage on CSN is 50mV below CSP, the timing capacitor C 35µA if the PL pin is open. (Power limiting will be dis cussed later). If this threshold is exceeded long enough

to charge to 1.5V, a fault is declared and the exter

for C

T begins to charge at about

nal MOSFET will be turned off. It will either be latched off

(until the power to the circuit is cycled, the L/R pin is

taken low, or the SD fixed off time (when C

pin is toggled), or will retry after a

T has discharged to 0.5V), depend

ing on whether the L/R pin is set high or low by the user. The equation for this current threshold is simply:

FAULT

The first time a fault occurs, C

charge 1.5V. Therefore:

FAULT ON

005.

SENSE

()

(sec)

T is at ground, and must

•

.µ 15

(1)

(2)

Page 5

APPLICATION INFORMATION

In the retry mode, the timing capacitor will already be charged to 0.5V at the end of the off time, so all subse quent cycles will have a shorter ton time, given by:

()

≅=(sec)

FAULT ON

Note that these equations for ton are without the power limiting feature (R

PL pin open). The effects of power limit

ing on ton will be discussed later. The off time in the retry mode is set by C

T and an inter

nal 1.2µA sink current. It is the time it takes C charge from 1.5V to 0.5V. The equation for the off time is therefore:

OFF

(sec).=

Shutdown Characteristics

When the SD pin is set to TTL high (above 2V) the UCC3919 is guaranteed to be enabled. When SD to a low TTL (below 0.8V) the UCC3919 is guaranteed to be disabled, but may not be in ultra low current sleep mode. When SD

is set to 0.2V or less, the UCC3919 is guaranteed to be disabled and in ultra low current sleep mode.See Fig.1.

1.e-02

1.e-03

1.e-04

1.e-05

1.e-06

1.e-07

(3)

T to dis

(4)

is set

UCC1919 UCC2919 UCC3919

reduces the voltage on GATE to control the external MOSFET in a constant current mode.

During this time C

this condition lasts long enough for C a fault will be declared and the MOSFET will be turned off.The I

Note that if the voltage on the IMAX pin is programmed

to be less than 50mV below CSP, then the UC3919 will

MAX

CSP IMAX

control the MOSFET in a constant current mode all the time. No fault will be declared and the MOSFET will re main on because I

Overload Threshold

There is a third threshold which, if exceeded, will declare a fault and shutdown the external MOSFET immediately, without waiting for CT to charge. This “Overload” threshold is 200mV greater than the IMAX threshold (again, this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is on, with a load current below I across the output. This allows hot-swapping in cases where the UCC3919 is already powered up (on the backplane) and capacitors are added across the output bus. In this case, the load current could rise too quickly for the linear amplifier to reduce the voltage on GATE and limit the current to I the MOSFET will be turned off quickly and a fault de clared. A latch is set so that C teeing that the MOSFET will remain off for the same period as defined above before retrying. The overload current is:

OVERLOAD

T is charging, as described above. If

T to charge to 1.5V,

current is calculated as follows:

–

SENSE

is less than I

MAX

MAX, and a short is quickly applied

MAX. If the overload threshold is reached,

T can be charged, guaran

–.

CSP IMAX

SENSE

FAULT

MAX

SENSE

(5)

(6)

1.e-08 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Figure 1. Typical Shutdown Current

IMAX Threshold

The second threshold is programmed by the voltage on IMAX (measured with respect to the CSP pin). This con trols the maximum current, I

MAX, that the UCC3919 will

allow to flow into the load during the MOSFET on time. A resistive divider connected between IBIAS and CSP gen erates the programming voltage. When the drop across the sense resistor reaches this voltage, a linear amplifier

Note that I

OVERLOAD

depending on the value of R

may be much greater than IMAX,

SENSE

Power Limiting

A power limiting feature is included which allows the power dissipated in the external MOSFET to be held relatively constant during a short, for different values of input voltage. This is accomplished by connecting a re

sistor from the output (source of the external MOSFET) to PL. When the output voltage drops due to a short or overload, an internal bias current is generated which is

equal to:

VV V

––

()

IN OUT PL

≅

(7)

Page 6

APPLICATION INFORMATION (cont.)

This current is used to help charge the timing capacitor in the event that the load current exceeds I plified schematic of the circuit internal to the UCC3919 is shown in Figure 2.) The result is that the on time of the MOSFET during current limit is reduced as the input volt age is increased. This reduces the effective duty cycle, holding the average power dissipated constant.

VDD

UCC3919

POWER LIMIT

1X 1X

VDD

FAULT

. (A sim

UCC1919 UCC2919 UCC3919

PIV

=••0 033.

DISS MAX IN

Calculating C

(min) for a Given Load Capacitance

without Power Limiting

To guarantee recovery from an overload when operating in the retry mode, there is a maximum total output ca pacitance which can be charged for a given t time) before causing a fault. For a worst case situation of a constant current load below the fault threshold, C for a given output load capacitance (without power limit ing) can be calculated from:

−

(min)=

•••

IN OUT

MAX LOAD

35 10

−

(11)

(fault

T(min)

(12)

GATE

LOAD

RPL

FLT

UGD-98124

Figure 2. Power limiting circuit.

It can be seen that power limiting will only occur when I

is > 0 (it cannot be negative). For power limiting to begin to occur, the voltage drop across the MOSFET must be greater than VDD-V

VV V

−≥14.

IN OUT

The on time using R

35 10

+•

The graph in Figure 4 illustrates the effect of R

or 1.4V(typ).

PL is defined as:

∆

•

where V = 1V

−

(8)

(9)

on the average MOSFET power dissipation into a short. The equation for the average power dissipation during a short is:

−

MAX IN

DISS

IVt

MAX IN ON

ON OFF

•••

12 10

−

+•

35 10

•• +

, or

(10)

If PL is left unconnected, the power limiting feature will not be exercised. In the retry mode, the duty cycle during a fault will be nominally 3%, independent of input voltage. The average power dissipation in the external MOSFET with a shorted output will be proportional to input voltage, as shown by the equation:

A larger load capacitance or a smaller C

T will cause a

fault when recovering from an overload, causing the cir cuit to get stuck in a continuous hiccup mode. To handle larger capacitive loads, increase the value of C

The

equation can be easily re-written, if desired, to solve for C

OUT(max)

For a resistive load of value RL and an output cap C C

Tmin

for a given value of CT.

OUT

can be smaller than in the constant current case,

and can be estimated from:

(min)=



28 10

•



 

CRn

−••−

OUT L

MAX L





•



(13)

Note that in the latch mode (or when first turning on in the retry mode), since the timing capacitor is not recover ing from a previous fault, it is charging from 0V rather than 0.5V. This allows up to 50% more load capacitance without causing a fault.

Estimating C

If power limiting is used, the calculation of C given C

OUT

cially with a resistive load. This is because the C current becomes a function of V

(min) When Using Power Limiting

min for a

becomes considerably more complex, espe

charge

, which is changing

OUT

with time. The amount of capacitance that can be charged (without causing a fault) when using power limit ing will be significantly reduced for the same value C due to the shorter ton time.

The charge current contribution from the power limiting circuit is defined as:

VV V

−−

()

≅

IN OUT PL

(14)

Page 7

APPLICATION INFORMATION (cont.)

UCC1919 UCC2919 UCC3919

t0: Normal condition - Output current is nominal, output

voltage is at positive rail, V

1: Fault control reached - Output current rises above

the programmed fault value, C 35µA + I

2: Maximum current reached - Output current reaches

begins to charge with

the programmed maximum level and becomes a con stant current with value I

3: Fault occurs - C

MAX

has charged to 1.5V, fault output

Figure 3. Typical Timing Diagram

goes low, the FET turns off allowing no output current to flow, V

4: Retry - CT has discharged to 0.5V, but fault current

is still exceeded, C

OUT increases.

3 to t5: Illustrates <3% duty cycle depending upon

PL selected.

6 = t4

T begins charging again, FET is on,

discharges to GND.

OUT

t7: Fault released, normal condition - return to normal operation of the circuit breaker

UDG-97073

Page 8

APPLICATION INFORMATION (cont.)

Constant Current Load

For a constant current load, the output capacitor will charge linearly. During that time:

Iavg

()≅

()

IN PL

••

−

PL IN

Modifying equation (12) yields:



()

 



MAX LOAD

(min)≅

••

IN OUT

−

IN PL

••

PL IN

−

+•

35 10

(15)



(16)



−26

 

0.25

0.15

0.05

POWER DISSIPATION (Watts)

0.3

0.2

0.1

For I

MAX

123456

VDD (Volts)

UCC1919 UCC2919 UCC3919

=7A

RPL=

24.9K 20K

15K 10K

Resistive Load

Determining C

(min) for a resistive load is more complex.

First, the expression for the output voltage as a function of time is:



VtI R e

()=• −

OUT MAX LOAD

Solving for T

START

when V

 

 

OUT

START

−

•

LOAD OUT

= VINyields:

4.99k

100k

 



 

1CSP

(17)

IMAX

IBIAS CSN

Figure 4. MOSFET average short circuit power dissipation vs. V

−••−

START

RC n

LOAD OUT

for values of RPL.







MAX LOAD



•







Assuming that the device is operating in the retry mode, where C t, C

VDD

is charging from 0.5V to just below 1.5V in time

is defined as:

Idt

•

=+•

()

CT PL

Idt

=•

35 10

−

0.01Ω

Where

(18)

(19)

Figure 5. Application circuit.

0.01µF

N/C

CAP

L/R

FLT

GND

GATE

RPL10k

0.01µF

OUT

LOAD

OUT

UDG-98137

Page 9

APPLICATION INFORMATION (cont.)

Substituting equation (15) into (19) yields:

 

−

()

(min)=

IN PL

 

••

PL IN



35 10

+•

This yields the following expression for C sistive load with power limiting. By substituting the value calculated for T

in equation (18) for dt, CT(min) is

START

determined.



•

()

IN PL

(min)=

 

••

PL IN



35 10

+•

Example

The example in Figure 5 shows the UCC3919 in a typical application. A low value sense resistor and N-channel MOSFET minimize losses. With the values shown for R1, R2, and R ear current limiting (I

S, the overcurrent fault will be 5A nominal. Lin

will occur at 7.14A and the

MAX)

overload comparator will trip at 27A. The calculations are shown below.

005 005

FAULT

===

001

 

−26

•

  

 

−26

•

 

(min) for a re

START

(20)

(21)

(22)

UCC1919 UCC2919 UCC3919

For a worst case 5A constant current load: C 27µF.

With L/R grounded, the part will operate in the retry or “hiccup” mode. The values shown for C yield a nominal duty cycle of 0.32% and an off time of

8.3ms. With a shorted output, the average steady state power dissipation in Q1 will be less than 100mW over the full input voltage range.

If power limiting is disabled by opening R

µµ1

P shorted

For a worst case 1Ωresistive load: C

==•=sec

FAULT ON

()

DISS

714 5 287 10

•• •

87 10 833 10

−−

•+•

IVt

••

MAX IN ON

OFF ON

−

287

12 5

WwithV V

()

OUT

For a worst case 5A constant current load: C 120µF.

THERMAL CONSIDERATIONS Steady State Conditions

OUT

and RPLwill

, then:

(max) ≅ 220µF.

OUT

(max) ≅

(29)

(30)

(max) ≅

−

MAX

IIRAA

OVERLOAD MAX

OFF

With the value shown for R

I output shorted

PL typ





 

t shorted

P shorted

CSP IMAX

=+=+=

(sec)

()

−

IN PL

()

35 10

+•

()

DISS

()















−

••714 5 2727µ

+•

833 10

()

RR R

001



−516



=340µ



001 10

•

375

IVt

••

MAX IN ON

ON OFF

012

−

•

15 1

+•

714

.===

833

−

001

714..

2714

(23)

(24)

(25)

(26)

(27)

(28)

In normal operation, with a steady state load current below I

, the power dissipation in the external MOSFET

FAULT

will be:

P RDS I

=•

DISS ON LOAD

(31)

The junction temperature of the MOSFET can be calcu lated from:

TT P

=+ •θ

JA DISSJA

Where T

()

is the ambient temperature and θJA is the

(32)

MOSFET’s thermal resistance from junction to ambient. If the device is on a heatsink, then the following equation:

+++

θθθθ

JA JC CS SA

Where

is the MOSFET’s thermal resistance from

junction to case, θ to sink, and θ

is the thermal resistance of the heatsink

CS is the thermal resistance from case

(33)

to ambient. The calculated T

must be lower than the MOSFET’s

maximum junction temperature rating, therefore:

DISS

−(max)

(34)

For a worst case 1Ωresistive load: C

(max) ≅ 47µF.

OUT

Page 10

APPLICATION INFORMATION

Transient Thermal Impedance

During a fault condition in the retry mode, the average MOSFET power dissipation will generally be quite low due to the low duty cycle, as defined by:

IVt

Pavg

()=

DISS

••

MAX IN ON

ON OFF

(w/output shorted)

(35)

UCC1919 UCC2919 UCC3919

This effective transient thermal impedance, when multi plied by the pulse power, will give the transient tempera ture rise of the die. To keep the junction temperature below the maximum rating, the following must be true:

()

trans

()

max=−

P pulse

()

DISS

(38)

(In the latch mode, t

will be the time between a fault

OFF

and the time the device is reset.) However, the pulse power in the MOSFET during t

with the output shorted, is:

P pulse I V

()=•

DISS MAX IN

In choosing t

for a given VIN,I

(w/output shorted) (36)

, and duty cycle it is

MAX

important to consult the manufacturer’s transient thermal impedance curves for the MOSFET to make sure the de vice is within its safe operating area. These curves pro vide the user with the effective thermal impedance of the device for a given time duration pulse and duty cycle. Note that some of the impedance curves are normalized to one, in which case the transient impedance values must be multiplied by the DC (steady state) thermal resistance, θ

For duty cycles not shown in the manufacturer’s curves, the transient thermal impedance for any duty cycle and ton time (given a square pulse) can be estimated from [1]:

θθθ

trans D D

()=• +−•1

JC JC SP

()

where D is the duty cycle:

()

ON OFF

(37)

If necessary, the junction temperature rise can be re duced by reducing ton (using a smaller value for C by reducing the duty cycle using the power limiting fea

ture already discussed. Note that in either case, the amount of load capacitance, C

, that can be charged

OUT

before causing a fault, will also be reduced.

Safety Recommendations

Although the UCC3919 is designed to provide system

protection for all fault conditions, all integrated circuits

can ultimately fail short. for this reason, if the UCC3919 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3919 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device.

References

[1] International Rectifier, HEXFET Power MOSFET Design-

er’s Manual, Application Note 949B,

Operating Area, and High Frequency Switching Perform ance of Power HEXFETs,

pp.1553-1565, September 1993.

Current Ratings, Safe

), or

and θ

is the single pulse thermal impedance given in

the transient thermal impedance curves for the time du ration of interest (t

). Note that these are absolute num

bers, not normalized. If the given single pulse impedance is normalized, it must first be multiplied by θ

JC before us

ing in the equation above.

UNITRODE CORPORATION 7 CONTINENTAL BLVD.• MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460

Page 11

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.