Datasheet UCC1890, UCC2890, UCC3890 Datasheet (UNITRODE)

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Off-Line Battery Charger Circuit

UCC1890 UCC2890 UCC3890

FEATURES

• Transformerless Off-Line Operation

• Low Voltage Operation to 0.8V

• Ideal for Battery Trickle Charger

Applications

• Current Mode Operation With 100mV Shunt

• Voltage Mode Operation With Fixed 1.25V Output or Resistor Adjustable Output

• Efficient BiCMOS Design

• Inherent Short Circuit Protection

BLOCK DIAGRAM

DESCRIPTION

The UCC3890 controller is optimized for use as an off-line, low power, low voltage, regulated current supply, ideally suited for battery trickle charger applications. The unique circuit topology used in this device can be visualized as two cascaded flyba ck converters; each operating in the discontinuous mode, and both driven from a s ingle external power switch. The significant benefit of this approach is the ability to charge low voltage batteries in off-line applications with no transformer, and low internal losses.

The control algorithm used by the UCC3890 forces a switch on time inversely pr oportional to t he input line v oltage, whil e the switch off time is inversely proportional to the output voltage. This action is automatically controlled by an internal fe ed ba c k l oo p a nd reference. The cascaded c onfiguration al lows a large voltage c onversion ratio with r easonable switch duty cycle.

While the UCC3890 is ideally suited for control of constant current battery chargers, provision is also made to operate as a fixed 1.25V regulated supply, or to use a resistor vo l tage di vi der to obtain output vol tages hi gher than 1.25V.

Note: This device incorporates patented technology used under license from

Lambda Electronics, Inc.

3/97

UDG-96052

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UCC1890 UCC2890 UCC3890

ABSOLUTE MAXIMUM RATINGS

IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mA

Current into TON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mA

Voltage on V

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20V

CONNECTION DIAGRAMS

DIL-8, SOIC-8 (Top View) J, N, or D Packages

Current into TOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250µA

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

ELECTRICAL CHARACTERISTICS:

UCC1890, –40°C to 85°C for the UCC2890, and 0°C to 70°C for the UCC3890. No load at DRIVE pin (C

Unless otherwise stated, these specifications apply for TA = –55°C to 125°C for

= 0), TA = TJ.

LOAD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

General

VDD Zener Voltage I Minimum Operat in g C urre nt I

TON

= 4.75mA,I

= 0mA 8.3 9.0 9.4 V

TON

IDD = –1mA, F = 150kHz 1.65 2.0 mA

Undervoltage Lockout

Minimum Voltage to Start FB = 0 7.8 8.6 9.2 V Minimum Voltage after Start FB = 0 5.75 6.3 6.65 V Hysteresis FB = 0 1.8 2.3 2.6 V VDD – V

START

FB = 0 0.2 0.4 0.7 V

Oscillator

Amplitude I

TON

= 3mA; I

= 50µA; VFB = 0V CT = 100pF 3.1 3.4 3.7 V

TOFF

CT to DRIVE High Delay Overdrive = 200mV 80 200 ns CT to DRIVE Low Delay Overdrive = 200mV 50 100 ns Charge Coefficient I

CT/ITON

Discharge Coefficent I

CT/ITOFF

= 3mA; V

TON

= 50µA; VCT = 3.0V 0.95 1.00 1.05µA/µA

TOFF

= 3.0V 0.135 0.15 0.165µA/µA

Driver

Rise Time C Fall Time C

I = 100mA (Note 1) 0.7 1.8 V I = –100mA referred to VDD (Note 1) –2.9 –1.5 V

= 1nF 35 70 ns

= 1nF 30 60 ns

Line Voltage Detection

Minimum I

Detector Hysteresis 110

TON

for Fault 1.0 1.5 2.0 mA

TON

On Time During Fault 0.5

OUT

Error Amplifier

Reference Level I

Voltage at TOFF I Regulation gm I

= 50µA, ICT = 25µA, TJ = 25°C 1.20 1.25 1.30 V

TOFF

= 50µA, ICT = 25µA, Over Temperature 1.15 1.25 1.35 V

TOFF

= 50µA 0.3 0.4 0.5 V

TOFF

= 50µA (Note 2) 2.0 4.0 7.7 mA/V

TOFF

Current Sense Amplifier

Gain VCS = 90 – 110mV 11.8 12. 5 13.0 V/V Input Offset Voltage V Input Voltage for CS Amplifier Enabled I Input Voltage for CS Amplifier Disabled I

= 90 – 110mV –5 0 5 mV

= 3mA, Referred to VDD –1.5 –0.8 V

TON

= 3mA, Referred to VDD –0.8 –0.3 V

TON

Note 1: VDD forced to 100mV below VDD Zener Voltage

∆

Note 2: gm is defined as

are for I

at 65% amd 35% of its maximum value.

for the values of VFB where the error amp is in regulation. The two points used to calculate gm

∆

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PIN DESCRIPTIONS

CS:

The high side of the current sense shunt is connected to this pi n. Short CS to VDD for voltage feedback operation.

UCC1890 UCC2890 UCC3890

TOFF:

Resistor R this pin to provide a maximum capacitor discharge current proportional to output voltage.

OFF

connects from voltage output to

CT:

Oscillator timing capacitor is connected to this pin.

DRIVE: FB:

Gate drive to external power switch.

Output of current sense amplifier. This pin can be used for direct output voltage feedback if the current sense amp input pin CS is shorted to the VDD pin.

GND:

Ground pin.

APPLICATION INFORMATION

TON:

Resistor R

connects f rom lin e in put to this pin to provide capacitor charge current proportional to line voltage. The current in R

also provides power for the 9V

shunt regulator at VDD.

VDD:

Output of 9V shunt regulator.

Figure 1. Typical Voltage Mode Application

OPERATION (VOLTAGE OUTPUT)

Figure 1 shows a typical voltage mode application. When input voltage is first applied, all of the current through R

and 80% of the current through R

ON,

charge the ext ernal ca paci tor C3 conn ected to VDD. As the volta ge builds on VDD, u ndervoltage lockout holds the circuit off and the output DRIVE low until VDD reaches 8.4 V. At this time, DRI VE go es h igh, turning on the external power switch Q1, and 15% of the current into TON is directed to the timing capacitor C

. The voltage at TON is fixed at approximately 11V, so C charges to a fixed threshold with current

I = 0.2 •

– 11V

Since the input line is much greater than 11V, the charge current is approximately proportional to the input

line voltage. DRIVE is only high while C

is charging, so

the power swi tc h on time i s inver sely pr oportional to l ine voltage. Thi s provides a constant line voltage-switch on time product.

At the end of the switc h on time, Q1 i s turned off, and

the 15% of the R

current which was charging CT is diverted to ground . The power switch off time is controlled by discharge of C

, which is determined by the outut

voltage as described here:

UDG-96053

UDG-96054

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APPLICATION INFORMATION (cont.)

1. When V provides inherent short circuit protection. However, to ensure output voltage startup when the output is not a short, a high value resistor, R parallel with C frequency.

OUT

= 0, the off time is infinite. This feature

is placed in

to establish a minimum switching

Frequency =

TON =

TOFF

CT • 3.4V

(

)

MAX

= 1.5 • RS • CT (regions 1 and 4

TON

TOFF

•

0.15 • R

– 11V

UCC1890 UCC2890 UCC3890

)

2. As V set by R

As V

OUT

rises above approximately 0.4V, I

OFF

, and is defined by

OUT

– 0.4V

DCHG

OUT

OFF

increases, I

DCHG

increases resulting in the

DCHG

reduction o f off time. The frequency of operation increases and V

OUT

rises quickly to its regulated

value.

3. In this regi on, a transconductance amplifier reduces

DCHG

in order to maintain V

OUT

in regulation. The input to the transconduct an ce am plif ier is the pin FB . (In this mod e the pi n CS s hould be shorted to VDD.) FB can either be connected directly to V late at nominal V

OUT

through a resistor divider R

OUT

= 1.25V or to be connected to

OUT

VS1/RVS2

to regu-

late at nominal

)

VS2

DCHG

4. If V

•

VS1

1.25V

OUT

should ri se above its regulation range, I

VS2

falls to zero and the circuit returns to the minimum frequency established by R

and CT.

The range of sw itch ing fre quencies is establis hed by

OFF

, R

, RS, and CT as follows:

TOFF

•

3.4V

OUT

•

− 0.4V

OFF

(region 2

)

The above equ ations assume VD D = 9, the voltage at TON = 11V, the voltage at TOFF = 0.4V.

OPERATION (CURRENT OUTPUT)

Figure 2 shows a typical current mode application. In current mode, operation is the same as in voltage mode, except that in region 3 the transconductance amplifier is cont rolled by the current sense a mplifier which

senses the voltage across a shunt resistor R

. The circuit then re gulates the curre nt in the shunt to the nominal value

100mV

The circuit shown in this schematic would be suitable for an application which trickle charges a battery at a low current, (e.g. C/10), and has a battery load which draws a high current, (e.g. C), when turned on. In that

SH1

case, R

100mV

value is chosen so that

SH1

Figure 2. Typical Current Mode Applicatio n

UDG-96055

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APPLICATION INFORMATION (cont.)

SH2

If R

then the regulator output will assist the battery, minimizing or eliminating battery output current.

DESIGN EXAMPLE

A typical design has the following requirements: V

V V

I F

Component v alu es a re in dica ted i n Figure 3. The explanation for the choices in component values follows.

First calc ulate the maximum duty cycle, d(max). To calculate thi s assume that at m aximum loa d/minimum line conditions, the converter wil l be at the continuous conduction bou nd ary and there wil l be no i dle time after the inductors are discharged. Fo r all other load/line conditions, the UCC3890 will stretch the off time, to create an idle time afte r the inductors are discharged, in order to

is chosen so that

100mV

IN OUT OUT

LOAD

SWITCHING

(eff.) = 50% (excluding efficiency losses in

SH2

′

= 80 to 132 VAC or 100 to 180 VDC = 1.25V = 2.0V (assumes 1.25

750mV forward drop in D3) = 500mADC max = 100kHz

D3 which will be very large due to the

low output voltage. Losses in D3 are

accounted for by using V

calculations).

VOUT

with

OUT

′

in the

UCC1890 UCC2890 UCC3890

maintain a con stant out put volt age. For a single flyback stage at continuous conduction boundary

1 +

OUT

1 +

100kHz



√

OUT

100V



√

d(max

SWITCHING

0.125

1 − 0.125

100kHz

′

= 0.125

)

1.25

= 8.75µs

d =

For the cascaded flyback stages of the UCC3890 topology, the corresponding equation is

d(max) =

in this case

d(max) =

Next using the operating frequency and the maximum duty cycle to calculate the maximum on time

TON(max) =

in this case

TON(max) =

correspondingly

TOFF(min) =

Figure 3. Example Application

UDG-96056

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APPLICATION INFORMATION (cont.)

The average input current at minimum line and maximum load will be

UCC1890 UCC2890 UCC3890

entire range of operat ion mus t be cons idered to choose values for the rest of the components.

′

OUT

•

in this case

500mA

0.5

•

100V

20mA

Knowing that input current is drawn from the line only during TON, calculate the peak current in L1 to be

(pk) =

•

IIN •

TON + TOFF

TON

in this case

(pk) =

•

20mA •

1.25

+ 8.75µs

1.25

= 320mA

Now calculate the value for L1

VIN

• (pk)

TON

in this case

= 100V •

1.25µs 320mA

= 390µH

The output voltage of the first flyback stage is

= VIN •

TON

TOFF

in this case

= 100V •

1.25µs

8.75µs

= 14.3V

Knowing that out put cur rent is pro vi ded to t he l oad only during TOFF, calc ulate the peak current in L2 to be

(pk) =

OUT

•

TON

•

TOFF

in this case

(pk) =

•

0.5A •

Now calculate the value of L

′ •

OUT

L2 =

1.25µs + 8.75µs

TOFF

(pk)

8.75

= 1.14A

in this case

= 2V •

8.75µs

1.14A

= 15µH

For all of the calculations so far only the maximum load/minimum line condition have been considered. The

Under all no rmal operating c onditions the current I

TON,

(which is the current in RON), should be greater than 2mA and less than 7 .5mA. In this case set R

TON

= 2.8mA at low line. The voltage at TON will be

to give

about 11V so

−

100V

With RON = 33k, I

180V − 11V

TON

At high line, the power dissipation in R

)

P(R

will need to be at least a 1W resistor. Alternately it

2.8mA

= (

180V

33k

11V

TON

at high line will be

33k

Ω

= 5.1mA

−

11V) • 5.1mA = 860mW

will be

could be four 1/4W 8.2kΩ resistors in series. Once R

for C

is set, CT can be chos en. The char ge current

is nominally 15% of I

TON

, and the nominal oscilla-

tor amplitude is 3.4V, so

TON =

CT • 3.4V

•

0.15

TON

solving for CT

TON • 0.15 • I

CT =

TON

at low line is 2.8m A , an d th e ta rge t TON at low line

3.4V

TON

is 1.25µs, so in this case

•

1.25µs

CT = The final com pone nt to be chosen is R

0.15 • 2.8mA

3.4V

= 150pF

OFF

, which determines the minimum value of TOFF. When the output voltage is bel ow the regu lation point, the discharge current for CT is equal to I

TOFF

(the current in R

OFF

). Un-

der that condition

TOFF =

CT • 3.4V

TOFF

since the voltage at the TOFF pin = 0.4V

−

OUT

OFF

• (

0.4V

OUT

•

−

3.4V

0.4V

OFF

)

TOFF

substituting and solving for R

OFF

The largest discharge current, and hence the minimum off time, will occur when the output is about 10mV be-

Page 7

APPLICATION INFORMATION (cont.)

low the regulation point of 1.25V. The minimum value for TOFF is 8.75µs. So in this case

−

)

8.75µs • (1.24V

OFF

150pF • 3.4V

OTHER APPLICATION CONSIDERATIONS Output Capacitor:

For best regulation of the output voltage or c urrent, the output capacitor should be a low ESR type. This i s e spec ial ly t rue when operating i n current sense mode with a non-linear load such as a battery. If a low ESR cap acitor cannot be used, excellent regulation can also be achi eved by placing a low pass R/C filter between the current shunt and the CS input.

No Load Operation:

tected for short circui ts, but not for open circuits. If the load is removed, the output voltage will quickly rise up to the regulation point. Once the output is above the regulation voltage, the oscillator will drop to the minimum frequency set by R put, even at this low frequency the output voltage can quickly rise to a dangerous le vel. To protect agains t t h is , it is recom mended that a zene r or other voltage clamp always be connected across the output. The clamp should be chosen to be above the normal range of output voltage, but low enough to protect the output capacitor. In current sense operation, removal of the load will also break the regulation loop, in which case a sim-

0.4V = 15k

The UCC3890 is inherently pro-

S/CT

. With no loa d on the out-

UCC1890 UCC2890 UCC3890

ple clamp on the output may not be adequate. In current sense mode it is recomme nded tha t a second z ener be connected from the out pu t to the FB pi n, the br eakdown voltage of this clamp c hosen to b e high enough so that it will not conduct during normal operation, but will conduct at least 2V lower than the breakdown voltage of the other clamp.

Gate Drive for the External FET:

guaranteed to be able to deliver at least 1mA of steady state curre nt to the gate of the external FET at I 2mA. If I

TON

is higher th an 2mA, 80% of the additional current is available to drive the FET gate. If, as in the design example above, a moderate sized FET such as the IRF820 i s used, the operating frequency is 100kHz, and the minimum I

TON

at low line is 2.8mA, then the available gate drive current may be adequate. The IRF820 needs about 13nC to ch arge the gate on ea ch cycle. At 100kHz, this is equivalent to 1.3mA steady state; below the minimum 1.64mA available. In some combinations of a larger FET, and/or higher frequency operation, t he current available for dri ving the gate may not be adequa te. In t hat ca se ex tra current may be provided by connecting a resistor R the VDD pin. This resistor should be sized so that under all conditions the current input to VDD is below the

7.5mA absolute maximum limit. R be a power resistor.

The UCC3890 is

from the line input to

will likely need to

TON

UNITRODE CORPORATI ON 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424- 24 10 • FAX (603) 424-3460

Page 8

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