Datasheet UCC1857, UCC2857, UCC3857 Datasheet (UNITRODE)

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Page 1

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Isolated Boost PFC Preregulator Controller

UCC1857 UCC2857 UCC3857

PRELIMINARY

FEATURES

• PFC With Isolation, V

• Single Power Stage

• Zero Current Switched IGBT

• Programmable ZCS Time

• Corrects PF to >0.99

• Fixed Frequency, Average Current

Control

• Improved RMS Feedforward

• Soft Start

• 9V to 18V Supply V Range

• 20-Pin DW, N, J, and L Packages

< V

TYPICAL APPLICATION CIRCUIT

DESCRIPTION

The UCC3857 provides all of the control functions necessary for an Isolated Boost PFC Converter. These converters have the advantage of transformer isolation between primary and secondary, as well as an output bus voltage that is lower than the input voltage. By providing both power factor correction and down conversion in a single power processing stage, the UCC3857 is ideal for applications which require high efficiency, integration, and performance.

The UCC3857 brings together the control functions and drivers necessary to generate overlapping drive signals for external IGBT switches, and provides a separate output to drive an external power MOSFET which provides zero current switching (ZCS) for both the IGBTs. Full programmability is provided for the MOSFET driver delay time with an external RC network. ZCS for the IGBT switches alleviates the undesirable turn off losses typically associated with these devices. This allows for higher switching frequencies, smaller magnetic components and higher efficiency. The power factor correction (PFC) portion of the UCC3857 employs the familiar average current control scheme used in previous Unitrode controllers. Internal circuitry changes, however, have simplified the design of the PFC section and improved performance.

(continued)

RECTIFIED AC INPUT

REF

CKT

OUT

–

BIAS

SUPPLY

REF

13 73

1IAC

CRMS

10 VA–

11 VAO

5VREF

UCC3857

RT 19

8 154

VINCAOCA–MOUTPKLMT

PGND

AGND

14MOSDRV

16IGDRV1

18IGDRV2

12DELAY

Q2Q1

FEEDBACK

OPTO

REF

02/99

UDG-98065

Page 2

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN, VD). . . . . . . . . . . . . . . . . . . . . . 18V

General Analog/Logic Inputs

(CRMS, MOUT, CA–, VA–, CT, RT, PKLMT)

(Maximum Forced Voltage). . . . . . . . . . . . . . . . –0.3V to 5V

IAC (Maximum Forced Current) . . . . . . . . . . . . . . . . . . . 300µA

Reference Output Current . . . . . . . . . . . . . . . Internally Limited

Output Current (MOSDRV, IGDRV1, IGDRV2)

Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C

Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C

Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 s. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

UCC1857 UCC2857 UCC3857

DESCRIPTION (continued)

Controller improvements include an internal 6 bit A-D converter for RMS input line voltage detection, a zero load power circuit, and significantly lower quiescent operating current. The A-D converter eliminates an external 2 pole low pass filter for RMS detection.

This simplifies the converter design, eliminates 2nd harmonic ripple from the feedforward component, and provides an approximate 6 times improvement in input line transient response. The zero load power comparator prevents energy transfer during open load conditions without compromising power factor at light loads. Low startup and operating currents which are achieved through the use of Unitrode's BCDMOS process simplify the auxiliary bootstrap supply design.

Additional features include: under voltage lockout for reliable off-line startup, a programmable over current shutdown, an auxiliary shutdown port, a precision 7.5V reference, a high amplitude oscillator ramp for improved noise immunity, softstart, and a low offset analog square, multiple and divide circuit. Like previous Unitrode PFC controllers, worldwide operation without range switches is easily implemented.

CONNECTION DIAGRAMS

DIL-20, SOIC- 20 (Top View) J, N and DW Packages

IAC

CRMS

MOUT

VIN

VREF

AGND

CA–

CAO

SS DELAY

10VA–

IGDRV2

PGND

IGDRV1

MOSDRV

PKLMT

VAO

PLCC-20 (Top View) L Package

IAC CRMS MOUT

VIN

VREF

AGND

CA–

CAO

VA–

4 5 6 7 8

91110 12 13

122019

18 17 16 15 14

CT RT

IGDRV2 PGND IGDRV1 VD MOSDRV

PKLMT DELAY VAO

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UCC1857 UCC2857 UCC3857

ELECTRICAL CHARACTERISTICS:

UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, V

Unless otherwise stated, these specifications apply for TA= 0°C to 70°C for the

, VVD= 12V, RT= 19.2K, CT= 680pF.

VIN

TA= TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Supply

Supply Current, Active No Load on Outputs, V Supply Current, Startup No Load on Outputs, V

VD VD

= V = V

VIN VIN

3.5 5 mA 60 TBD µA

VIN UVLO Threshold 13.75 15.5 V UVLO Threshold Hysteresis 3 3.75 TBD V

Reference

Output Voltage (V

VREF

= 25°C, I

= 1mA 7.387 7.5 7.613 V

REF

Over Temperature, UCC3857 7.368 7.5 7.631 V

Over Temperature, UCC1857, UCC2857 7.313 7.5 7.687 V Load Regulation I Line Regulation V Short Circuit Current V

= 1mA to 10mA 2 10 mV

REF

= VVD= 12V to 16V 2 15 mV

VIN

= 0V –55 –30 mA

VREF

Current Amplifier

Input Offset Voltage (Note 1) –3 0 3 mV Input Bias Current (Note 1) –50 nA Input Offset Current (Note 1) 25 nA CMRR V AVOL VCM= 0V, V

= 0V to 1.5V, V

= 2V to 5V 65 85 dB

CAO

VOH Load on CAO = 50µA, V VOL Load on CAO = 50µA, V Maximum Output Current Source : V

Sink : V

CA–

= 0V, V

CA–

= 1V, V

= 3V 80 dB

CAO

MOUT

= 1V, V

MOUT

= 0V, VCA– = 1V 0.2 V

MOUT

= 1V, V

= 0V, V

CAO

= 0V 6 7 V

CA–

= 3V –150 µA

CAO

= 3V 5 30 50 mA

Gain Bandwidth Product fIN= 100kHz, 10mV p – p 3 5 MHz

Voltage Amplifier

Input Voltage Measured on V Input Bias Current Measured on V AVOL V VOH Load on V VOL Load on V Maximum Output Current Source: V

= 1V to 5V 75 dB

VAO

VA–

Sink: V

VA–

= 3.2V, V

VA– VA–

= –50µA, V

= 50µA, V

= 2.8V, V

= 3V 2.9 3 3.1 V

VAO

= 3V –50 nA

VAO

= 2.8V 5.3 5.55 5.7 V

VA–

= 3.2V 0.1 0.45 V

VA–

= 3V –20 –12 –5 mA

VAO

= 3V 5 20 30 mA

VAO

Oscillator

Initial Accuracy T

= 25°C 42.5 50 57.5 kHz

40 50 60 kHz

Voltage Stability V

= 12V to 18V 1 %

VIN

CT Ramp Peak-Valley Amplitude 4 4.5 5 V CT Ramp Valley Voltage 1.5 V

Output Drivers

VOH IL = –100mA 9 10 V VOL IL = 100mA 0.1 0.5 V Rise Time C Fall Time C

= 1nF 25 TBD ns

LOAD

= 1nF 10 TBD ns

LOAD

Trailing Edge Delay

Delay Time R

= 12k, CD= 200pF, V

= 4V 1.6 2 2.4 µs

VAO

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UCC1857 UCC2857 UCC3857

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for T

UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, V TA= TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Soft Start

Charge Current 10 µA Shutdown Comparator Threshold Measured on SS 0 0.4 V

Multiplier

Output Current, IAC Limited I Output Current, Power Limited IAC= 100µA, V Output Current, Zero IAC= 0 –2 0 2 µA Gain Constant 2.5 1/V

Zero Power, Peak Current

Zero Power Comparator Threshold Measured on VAO 0.5 V Peak Current Limit Comparator

Threshold

Note 1: Common mode voltages = 0V, V

= 100µA, V

Measured on PKLMT 0 V

= 3V

CAO

VAO VAO

= 5.5V, V = 5.5V, V

= 0V –200 µA

CRMS

= 1V –200 µA

CRMS

, VVD= 12V, RT= 19.2K, CT= 680pF.

VIN

= 0°C to 70°C for the

PIN DESCRIPTIONS

AGND: Reference point of the internal reference and all

thresholds, as well as the return for the remainder of the device except for the output drivers.

CA–: Inverting input of the inner current loop error amplifier.

CAO: Output of the inner current loop error amplifier. This output can swing between approximately 0.2V and 6V. It is one of the inputs to the PWM comparator.

IAC: A resistor is connected to the rectified AC input line voltage from IAC. This provides the internal multiplier and the RMS detector with instantaneous line voltage information.

IGDRV1: Driver output for one of the two external IGBT power switches.

IGDRV2: Driver output for one of the two external IGBT power switches.

VAO: This is the output of the voltage loop error amplifier. It is internally clamped to approximately 5.6V by the UCC3857 and can swing as low as approximately 0.1V. Voltages below 0.5V on VAO will disable the MOSDRV output and force the IGDRV1 and IGDRV2 outputs to a zero overlap condition.

CRMS: A capacitor is connected between CRMS and ground to average the AC line voltage over a half cycle. CRMS is internally connected to the RMS detection circuitry.

CT: A capacitor (low ESR, ESL) is tied between CT and ground to set the ramp generator switching frequency in conjunction with RT. The ramp generator frequency is approximately given by:

0.67

≈

•

DELAY: Aresistor to VREF and a capacitor to AGND are connected to DELAY to set the overlap delay time for the MOSDRV output stage. The overlap delay function can be disabled by removing the capacitor to AGND.

MOSDRV: Driver output for the external power MOSFET switch.

MOUT: Output of the analog multiply and divide circuit. The output current from MOUT is fed into a resistor to the return leg of the input bridge. The resultant waveform forms the sine reference for the current error amplifier.

PKLMT: Inverting input of the peak current limit comparator. The threshold for this comparator is nominally set to 0V. The peak limit comparator terminates the MOSDRV, IGDRV1 and IGDRV2 outputs when tripped.

PGND: Return for all high level currents, internally tied to the output driver stages of the UCC3857.

RT: A resistor, R

is tied between RT and ground to set

the charging current for the internal ramp generator. The UCC3857 provides a temperature compensated 3.0V at RT. The oscillator charging current is therefore: 3.0V/R Current out of RT should be limited to 250µA for best performance.

VA–: This is the feedback input for the outer voltage control loop. An external opto isolator circuit provides the

Page 5

PIN DESCRIPTIONS (continued)

output voltage regulation information to VA– across the isolation barrier.

UCC1857 UCC2857 UCC3857

VIN can be isolated from each other with an RC lowpass filter for better supply noise rejection.

SS: A capacitor is connected between SS and GND to provide the UCC3857 soft start feature. The voltage on VAO, is clamped to approximately the same voltage as SS. An internal 10µA (nominal) current source is provided by the UCC3857 to charge the soft start capacitor.

VD: Positive supply rail for the three output driver stages. The voltage applied to VD must be limited to less than 18VDC. VD should be bypassed to PGND with a 0.1µF to 1.0µF low ESR, ESL capacitor for best results. VD and

VIN: Input voltage supply to the UCC3857. This voltage must be limited to less than 18VDC. The UCC3857 is enabled when the voltage on VIN exceeds 13.75V (nominal).

VREF: Output of the precision 7.5V reference. A 0.01µF to 0.1µF low ESR, ESL bypass capacitor is recommended between VREF and AGND for best performance.

VCT(PIN 20) & V

(PIN 8)

CAO

CLOCK (INTERNAL)

TOGGLE F/F Q (INTERNAL)

IGDRV1 (PIN 16)

TD1

Figure 1. Typical control circuit timing diagram.

APPLICATION INFORMATION

UCC3857 is designed to provide a solution for single stage power factor correction and step-down or step-up function, using an isolated boost converter. The Typical Application Circuit shows the implementation of a typical isolated boost converter using IGBTs as main switches in push-pull configuration and using a MOSFET as an auxiliary switch to accomplish soft-switching of IGBTs. Many variations of this implementation are possible including bridge-type circuits. The presense of low frequency ripple on the output makes this approach practical for distributed bus applications. It will not provide the highly regulated low ripple outputs typically required by logic level supplies.

IGDRV2 (PIN 18)

MOSDRV (PIN 14)

UDG-98217

The circuit shown in the Typical Application Circuit provides several advantages over a more conventional approach of deriving a DC bus voltage from AC line with power factor correction. The conventional approach uses two power conversion stages and has higher cost and complexity. With the use of UCC3857, the dual functionality of power factor correction and voltage step-down is combined into a single stage.

The power stage comprises a current-fed push-pull converter where the ON times of the push-pull switches (Q1 and Q2) are overlapped to provide effective duty cycle of a conventional PWM boost converter. When only one switch is on, the power is transferred to the output

Page 6

APPLICATION INFORMATION (continued) BLOCK DIAGRAM

UCC1857 UCC2857 UCC3857

VIN

IAC

CRMS

13.75V / 10V

10VA–

3.0V

9SS

11VAO

7CA–

UVLO

RMS DETECT

AND

CONDITIONING

VOLTAGE AMP

10µA

ENBL

7.5V REF

÷XMULT

ZERO POWER

0.5V

1.0V ALWAYS ON

VREF

MOUT CAO

REF GOOD

CURRENT AMP

PEAK LIMIT COMP

OSCILLATOR

PKLMT

19 RT

DELAY

TRAILING

EDGE

DELAY

ENBL

PWM COMP

R R

PWM

LATCH

TOGGLE

F/F

DRIVER

14 MOSDRV

16 IGDRV1

IGDRV2

17 PGND

6 AGND

UDG-98218

through the transformer and the output rectifier. It can be seen that the¸÷ operation on the primary side of the circuit is that of a boost converter and UCC3857 provides input current programming using average current mode control to achieve unity power factor. The transformer turns ratio can be used to get the required level of output voltage (higher or lower than the peak line voltage). The transformer also provides galvanic isolation for the output voltage.

Power stage optimization involves design and selection of components to meet the performance and cost objectives. These include the power switches, transformer and inductor design.

The choice of IGBTs is based on their advantage over MOSFETs at higher voltages. For universal line operation, the voltage stress on the push-pull switches can approach 1000V. However, the slow turn-off of IGBTs can contribute high switching losses and the use of MOSFET (QA) helps turn the IGBTs off with zero voltage across them (ZCS turn-off). This is accomplished by keeping QA on (beyond the turn-off of Q1 or Q2 – see Fig. 1 for waveforms) to allow the inductor current to divert from IGBT to MOSFET while the IGBT is turning off and still maintain zero volts. The MOSFET delay time

(TD1) effectively adds to the boost inductor charge period. The voltage stress of the MOSFET is half the stress of the IGBTs under normal operating conditions. However, QA can see much higher voltage stress under start-up and short circuit conditions as the converter operates in a flyback mode then. For different operating requirements or constraints (e.g. single North American line operation), the choice of switching components may be different (e.g. MOSFETs for Q1 and Q2 and no QA) as the voltage stress is different. In that case, UCC3857 can still be used without using the MOSDRV output.

Transformer design is very critical in this topology. The push-pull transformer must have minimal leakage inductance between the primary and secondary windings. Similarly, the leakage between the two primary windings must be minimized. In practice, it is hard to achieve both targets without using sophisticated construction techniques such as interleaving, use of foils etc. In many cases, it may be beneficial to use a planar transformer to achieve these objectives. The effects of higher leakage inductance include higher voltage stresses, ringing, power losses and loss of available duty cycle. The high voltage levels make it difficult to design effective snubber circuits for this leakage induced ringing.

Page 7

APPLICATION INFORMATION (cont.)

The design of the boost inductor is very similar to the conventional boost converter. However, as shown in the Typical Application Circuit, an additional winding connected to the output through a diode is required on the boost inductor. This winding must have the same turns ratio as the transformer and meet the isolation requirements. This winding is required to provide a discharge path for the inductor energy when the push-pull switches are both off. During start-up, when the output voltage is zero, the converter can see very high inrush currents. The overcurrent protection circuit of UCC3857 will shut down all the outputs when the set threshold is crossed. At that instance, the boost inductor auxiliary winding directs the energy to the output. This is a preferred manner of bringing the output voltage up to prevent the main switches from handling the high levels of inrush current. However, when the auxiliary winding is transferring the power to the output, the voltage stress across QA becomes input voltage plus the reflected output voltage–higher than its steady state value of reflected output voltage.

Chip Bias Supply and Start-up

UCC3857 is implemented using Unitrode’s BCDMOS process which allows minimization of the start-up (60 A typical) and operating (3.5mA typical) supply currents. It results in significantly lower power consumption in the trickle charge resistor used to start-up the IC.

Oscillator Set-up

The oscillator of UCC3857 is designed to have a wide ramp amplitude (4.5V p–p) for higher noise immunity. The CT pin has the sawtooth waveshape and during the discharge time of C the discharge period, the effective internal impedance to GND is 600 . Based on this, the discharge time is given by 831•C

. As shown in the waveforms of Fig. 1, the in-

ternal clock pulse width is equal to the discharge time and that sets the minimum dead time between IGDRV1 and IGDRV2. The clock frequency is given by

•+ •

1 5 831

The IGDRV1 and IGDRV2 outputs are switched at half the clock frequency while MOSDRV is switched at the clock frequency.

Reference Signal (I

Like the UC3854 series, the UCC3857 has an analog computation unit (ACU) which generates a reference current signal for the current error amplifier. The inputs to the ACU are signals proportional to instantaneous line voltage, input voltage RMS information and the voltage

, a clock pulse is generated. During

RCRC

TTTT

MULT

≈

) generation

••

15(. ) (. )

(1)

UCC1857 UCC2857 UCC3857

error amplifier output. Unlike prior techniques of RMS voltage sensing, UCC3857 employs a patent pending technique to simplify the RMS voltage generation and eliminate performance degradation caused by the previous techniques. With the novel technique (shown in Fig. 3), need for external 2-pole filter for V is eliminated. Instead, the IAC current is mirrored and used to charge an external capacitor (C half cycle. The voltage on CRMS takes the integrated sinusoidal shape and is given by equation 2. At the end of the half-cycle, CRMS voltage is held and converted into a 6-bit digital word for further processing in the ACU. C

is discharged and readied for integration during

CRMS

next half cycle. The advantage of this method is that the second har-

monic ripple on the V

signal is virtually eliminated.

RMS

Such second harmonic ripple is unavoidable with the limited roll-off of a conventional 2-pole filter and results in 3rd harmonic distortion in the input current signal. The dynamic response to the input line variations is also improved as a new V

Ipk

CRMS

Vpk

CRMS

••

21ω

()

For proper operation, I

signal is generated every cycle.

RMS

()

Ipk

•ω

()

CRMS

−

cos

()

CRMS

(pk) should be selected to be

100 A at peak line voltage. For universal input voltage with peak value of 265 VAC, this means R noise sensitivity of the IC requires a small bypass capacitor for high frequency noise filtering. The value of this capacitor should be limited to 220nF maximum. The V value should be approximately 1V at the peak of low line (80 VAC) to minimize any digitization errors. The peak value of V sired C

CRMS

at high line then becomes 3.5V. The de-

CRMS

can be calculated from equation 2 to be

75nF for 60Hz line. The multiplier output current is given by equation (3) with

K = 0.33.

MULT

VIK

VAO AC

CRMS

••(–.)05

The multiplier peak current is limited to 200 A and the selected values for IACand V

should ensure that

CRMS

the current is within this range. Another limitation of the multiplier is that I

can not exceed two times the IAC

MULT

current, limiting the minimum voltage on V The discrete nature of the RMS voltage feedforward

means that there are regions of operation where the in-

generation

RMS

) during a

CRMS

= 3.6M. The

CRMS

(2)

(2a)

CRMS

(3)

Page 8

APPLICATION INFORMATION (cont.)

IAC

CRMS

6BIT

WORD

VAO

MULTI

DAC

(X2)

UCC1857 UCC2857 UCC3857

A•B

Figure 3. Novel RMS voltage generation scheme.

put voltage changes, but the V

value fed into the

RMS

multiplier does not change. The voltage error amplifier compensates for this by changing its output to maintain the required multiplier output current. When the output of the ADC changes, there is a jump in the output of the error amplifier. This has minimal impact on the overall converter operation.

Another key consideration with the RMS voltage scheme is that it relies on the zero-crossing of the Iac signal to be effective. At very light loads and high line conditions, the rectified AC does not quite reach zero if a large capacitor is being used for filtering on the rectified side of the

AC LINE

BRIDGE

RECTIFIER

bridge. In such instances, the feedforward effect does not take place and the controller functionality is compromised. For UCC3857, the I

current should go below

10 A for the zero crossing detection to take place. It is recommended that the capacitor value be kept low enough for light load operation or that the alternative scheme shown in Fig. 4 be used for I

sense.

Gate Drive Considerations

The gate drive circuits in UCC3857 are designed for high speed driving of the power switches. Each drive circuit consists of low impedance pull-up and pull-down DMOS output stages. The UCC3857 provides separate supply and ground pins (VD and PGND) for the driver stages. These pins allow better local bypassing of the driver circuits. VD can also be used to ensure that the SOA limits of the output stages are not violated when driving high peak current levels. For this, VD can be kept as low as possible (e.g. 10V) while VIN can go higher to handle the UVLO requirements.

1IAC

UCC3857

Figure 4. Alternative implementation for sensing IAC.

Current Amplifier Set-up

Once the multiplier is set-up by choosing the V range, the current amplifier components can be designed. The maximum multiplier output is at low line, full load conditions. The inductor peak current also occurs at the same point. The multiplier terminating resistor can be determined using equation 4.

RMS

Page 9

MULT

•

−

L PK SENSE

MULT PK

−

(4)

The current amplifier can be compensated using a previously presented techniques (U-134) summarized here. A simplified high frequency model for inductor current to duty cycle transfer function is given by

()=

∧

(5)

The gain of the current feedback path at the frequency of interest (crossover) is given by

∧

=••

SENSE

∧

ISE

(6)

Where VSE is the ramp amplitude (p-p) which is 4.5V for UCC3857. Combining equations. 5 and 6 yields the loop gain of the current loop and equating it to 1 at the desired crossover frequency can result in a design value for

. The current loop crossover frequency should be lim-

ited to about 1/3 of the switching frequency of the converter to ensure stability. See Unitrode Application Note U-140 for further information.

UCC1857 UCC2857 UCC3857

with line feedforward is indicative of load power. The delay time is programmed with external components, R and CD. The sequence of events starts when the internal CLK signal resets latch U2, causing PWMDEL to go high and the Q output to go low. C M1 and is held low until the internal PWM signal goes low (indicating turn-off of either of the IGBT drives). At this point M1 turns off and C reference through R

. A comparator U1 compares this

voltage to the voltage error amplifier output (V the voltage on C

is greater than V

set causing PWMDEL to go low. PWMDEL is logically

7.5V REF

DELAY

VAO

CLK

was discharged via

charges towards the 7.5V

). When

VAO

, the latch U2 is

VAO

CLK

MOSDRV

PWM

PWMDEL

Trailing Edge Delay

As shown in the waveforms of Fig. 1, the modified isolated boost converter requires drive signals for the two main (IGBT) switches and the auxiliary (MOSFET) switch with certain timing relationships. The delay between turn-off of an IGBT and turn-off of the MOSFET can be programmed for the UCC1857. In a PFC application, the input line varies from zero to the AC peak level, resulting in a wide range of required duty ratios. A fixed delay time will induce line current distortion at the peaks of the AC line under high line and/or light load conditions. This is caused by the minimum controllable duty ratio imposed on the modulator by the fixed delay. If the minimum controllable duty ratio is fixed, the inner current loop can exhibit a limit cycle oscillation at the line peaks, inducing line current distortion.

The UCC1857 has an adaptive MOSFET delay generator, which is directly modulated by load power demand. Referring to Fig. 5, this circuit directly varies the delay time based on the output level of the voltage error amplifier, which in an average current mode PFC converter

Figure 5. Circuit for adaptive MOSFET delay generation.

ANDed with CLK

to produce the signal which commands the MOSFET driver output (MOSDRV). The delay time, TD1, is given by

TD R C n

=••

–





 

.–

VAO

 

 

(7)

This technique reduces the overlap delay at light loads or high lines, but maintains a longer delay when the line voltage is low or the load is heavy. This by definition reduces the minimum controllable duty ratio to an acceptable level, and is programmable by the user. Reducing the delay time under light current conditions is acceptable since the IGBT current is directly proportional to load current. By providing programming flexibility with R and CD, the delay times can be optimized for current and future classes of IGBT switches. The delay can also be set to zero by removing C

from the circuit.

UNITRODE CORPORATION 7 CONTINENTALBLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410  FAX (603) 424-3460

Page 10

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