Datasheet UC3844BDG Specification

Page 1

UC3844B, UC3845B, UC2844B, UC2845B

High Performance Current Mode Controllers

The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They are specifically designed for Off−Line and dc−dc converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET.

Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, a latch for single pulse metering, and a flip−flop which blanks the output off every other oscillator cycle, allowing output deadtimes to be programmed from 50% to 70%.

These devices are available in an 8−pin dual−in−line and surface mount (SOIC−8) plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage.

The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideally suited for off−line converters. The UCX845B is tailored for lower voltage applications having UVLO thresholds of 8.5V (on) and 7.6V (off).

Features

• Trimmed Oscillator for Precise Frequency Control

• Oscillator Frequency Guaranteed at 250 kHz

• Current Mode Operation to 500 kHz Output Switching Frequency

• Output Deadtime Adjustable from 50% to 70%

• Automatic Feed Forward Compensation

• Latching PWM for Cycle−By−Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• High Current Totem Pole Output

• Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

• These Devices are Pb−Free and are RoHS Compliant

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

ref

RT/C

Voltage

Feedback

Input

Output/

Compensation

8(14)

4(7)

2(3)

1(1)

Undervoltage

Lockout

Oscillator

Error

Amplifier

Pin numbers in parenthesis are for the D suffix SOIC-14 package.

GND

Figure 1. Simplified Block Diagram

5.0V

Reference

ref

Latching

PWM

5(9)

7(12)

Undervoltage

Lockout

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)

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PDIP−8

N SUFFIX

CASE 626

SOIC−14

D SUFFIX

CASE 751A

SOIC−8

D1 SUFFIX

CASE 751

PIN CONNECTIONS

(Top View)

ref

Output

GN D

ref

Output

GND

Power Ground

Compensation

Voltage Feedback

Current Sense

RT/C

Compensation

Voltage Feedback

Current Sense

RT/C

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking section on page 16 of this data sheet.

December, 2012 − Rev. 11

1 Publication Order Number:

UC3844B/D

Page 2

UC3844B, UC3845B, UC2844B, UC2845B

MAXIMUM RATINGS

Rating Symbol Value Unit

Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, V

Total Power Supply and Zener Current (ICC + IZ) 30 mA

Output Current, Source or Sink (Note 2) I

Output Energy (Capacitive Load per Cycle) W 5.0

Current Sense and Voltage Feedback Inputs V

Error Amp Output Sink Current I

Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A

Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air

D1 Suffix, Plastic Package, SOIC−8 Case 751

Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air

N Suffix, Plastic Package, Case 626

Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air

Operating Junction Temperature T

Operating Ambient Temperature UC3844B, UC3845B

UC2844B, UC2845B

UC3844BV, UC3845BV

Storage Temperature Range T

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as

the total power supply and zener current is not exceeded.

2. Maximum package power dissipation limits must be observed.

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard

JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A

4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78

ELECTRICAL CHARACTERISTICS (V

= 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

TA is the operating ambient temperature range that applies [Note 6], unless otherwise noted.)

UC284xB UC384xB, xBV, NCV384xBV

Characteristic Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) V

Line Regulation (VCC = 12 V to 25 V) Reg

Load Regulation (IO = 1.0 mA to 20 mA) Reg

Temperature Stability T

Total Output Variation over Line, Load, & Temperature V

Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) V

ref

4.95 5.0 5.05 4.9 5.0 5.1 V

line

load

− 2.0 20 − 2.0 20 mV

− 3.0 25 − 3.0 25 mV

− 0.2 − − 0.2 − mV/°C

4.9 − 5.1 4.82 − 5.18 V

− 50 − − 50 −

Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV

Output Short Circuit Current I

− 30 − 85 −180 − 30 − 85 −180 mA

OSCILLATOR SECTION

Frequency TJ = 25°C

TA = T

low

to T

high

TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)

Frequency Change with Voltage (VCC = 12 V to 25 V)

Frequency Change w/ Temperature (TA = T

low

to T

high

Oscillator Voltage Swing (Peak−to−Peak) V

OSC

)

OSC

/DV

/DT

49 48

225

−

250

55 56

275

49 48

225

− 0.2 1.0 − 0.2 1.0 %

− 1.0 − − 0.5 − %

− 1.6 − − 1.6 − V

5. Adjust VCC above the Startup threshold before setting to 15 V.

6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

=0°C for UC3844B, UC3845B T

low

= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B

=+70°C for UC3844B, UC3845B

high

= − 40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV

= +125°C for NCV384xBV

36 V

1.0 A

− 0.3 to + 5.5 V

10 mA

862 145

°C/W

702 178

°C/W

1.25 100

°C/W

+150 °C

0 to +70

−25 to +85

−40 to +105

− 65 to +150 °C

−

250

55 56

275

°C

kHz

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UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (V

is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)

= 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

UC284xB UC384xB, xBV,

NCV384xBV

Characteristic Symbol Min Typ Max Min Typ Max Unit

OSCILLATOR SECTION

Discharge Current (V

= 2.0 V) TJ = 25°C

OSC

TA = T

low

to T

(UC284XB, UC384XB)

high

(UC384XBV)

dischg

7.8

7.5

8.3

8.8

7.8

−

8.3

8.8

−

7.6

−

7.2

8.8

−

8.8

−

8.8

ERROR AMPLIFIER SECTION

Voltage Feedback Input (VO = 2.5 V) V

Input Bias Current (VFB = 5.0 V) I

Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A

VOL

2.45 2.5 2.55 2.42 2.5 2.58 V

− − 0.1 −1.0 − − 0.1 − 2.0

65 90 − 65 90 − dB

Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz

Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB

Output Current − Sink (VO = 1.1 V, VFB = 2.7 V)

Output Current − Source (VO = 5.0 V, VFB = 2.3 V)

Sink

Source

2.0

− 0.512−1.0

−

2.0

− 0.512−1.0

−−mA

Output Voltage Swing

High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to V

, VFB = 2.7 V)

ref

(UC284XB, UC384XB) (UC384XBV)

5.0

6.2

−

0.8

−

1.1

−

5.0

6.2

−

0.8

−

0.8

−

1.1

1.2

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 9 & 10)

(UC284XB, UC384XB) (UC384XBV)

Maximum Current Sense Input Threshold (Note 9)

(UC284XB, UC384XB) (UC384XBV)

2.85−3.0−3.15−2.85

2.85

0.9−1.0−1.1−0.9

0.85

3.0

1.0

3.15

3.25

1.1

Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 9) PSRR − 70 − − 70 − dB

Input Bias Current I

Propagation Delay (Current Sense Input to Output) t

PLH(In/Out)

− − 2.0 −10 − − 2.0 −10

− 150 300 − 150 300 ns

OUTPUT SECTION

Output Voltage

Low State (I

High State (I

Output Voltage with UVLO Activated (VCC = 6.0 V, I

Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) t

Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) t

= 20 mA)

Sink

= 200 mA, UC284XB, UC384XB)

Sink

= 200 mA, UC384XBV)

Sink

= 20 mA, UC284XB, UC384XB)

Source

= 20 mA, UC384XBV)

Source

= 200 mA)

Source

= 1.0 mA) V

Sink

OL(UVLO)

−

0.1

−

1.6

−

2.2

−

13.5

0.4

−

13.4

−

0.1

−

1.6

−

1.6

13.5

13.4

−

12.9

−

0.4

2.2

2.3

−

− 0.1 1.1 − 0.1 1.1 V

− 50 150 − 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold UCX844B, BV

UCX845B, BV

Minimum Operating Voltage After Turn−On UCX844B, BV

UCX845B, BV

CC(min)

7.8168.4179.0

9.0

7.0107.6118.2

14.5

7.8168.4

8.5

7.0107.6

17.5

9.0

11.5

8.2

7. Adjust VCC above the Startup threshold before setting to 15 V.

8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. T

=0°C for UC3844B, UC3845B T

low

= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B

=+70°C for UC3844B, UC3845B

high

= − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV

= +125°C for NCV384xBV

9. This parameter is measured at the latch trip point with VFB = 0 V.

DV Output/Compensation

10.Comparator gain is defined as: A

DV Current Sense Input

V/V

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UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (V

values T

is the operating ambient temperature range that applies [Note 12], unless otherwise noted.)

= 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max

UC284xB UC384xB, xBV, NCV384xBV

Characteristic Symbol Min Ty p Max Min Ty p Max Unit

PWM SECTION

Duty Cycle

Maximum (UC284XB, UC384XB)

Maximum (UC384XBV)

Minimum

(max)

(min)

−

47 46

48 48

−

TOTAL DEVICE

Power Supply Current

Startup (V

= 6.5 V for UCX845B,

= 14 V for UCX844B, BV)

Operating (Note 11)

Power Supply Zener Voltage (ICC = 25 mA) V

−

0.3120.5

−

0.3

30 36 − 30 36 − V

11.Adjust VCC above the Startup threshold before setting to 15 V.

12.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. T

=0°C for UC3844B, UC3845B T

low

= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B

=+70°C for UC3844B, UC3845B

high

= − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV

=+125°C for NCV384xBV

8.0

5.0

, TIMING RESISTOR (k )

2.0 NOTE: Output switches at 1/2 the oscillator frequency

0.8

, OSCILLATOR FREQUENCY (kHz)

OSC

For RTu 5KfX

1.72

TCT

Figure 2. Timing Resistor

versus Oscillator Frequency

VCC = 15 V TA = 25°C

1.0 M500 k200 k100 k50 k20 k10 k

1.CT = 10 nF

2.CT = 5.0 nF

3.CT = 2.0 nF

4.CT = 1.0 nF

5.CT = 500 pF

6.CT = 200 pF

7.CT = 100 pF

% DT, PERCENT OUTPUT DEADTIME

20 k 50 k 200 k 500 k

, OSCILLATOR FREQUENCY (kHz)

OSC

Figure 3. Output Deadtime

versus Oscillator Frequency

0.5

1.0 M100 k10 k

2.55 V

2.5 V

2.45 V

VCC = 15 V AV = -1.0 TA = 25°C

0.5 ms/DIV

Figure 4. Error Amp Small Signal

Transient Response

3.0 V

2.5 V

20 mV/DIV

2.0 V

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VCC = 15 V AV = -1.0 TA = 25°C

200 mV/DIV

1.0 ms/DIV

Figure 5. Error Amp Large Signal

Transient Response

Page 5

100

)

, OPEN LOOP VOLTAGE GAIN (dB)

VOL

-20

Figure 6. Error Amp Open Loop Gain and

UC3844B, UC3845B, UC2844B, UC2845B

VCC = 15 V VO = 2.0 V to 4.0 V

Gain

100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Phase versus Frequency

RL = 100 k TA = 25°C

Phase

1.2 VCC = 15 V

120

150

180

10 M10

1.0

0.8

TA = 25°C

0.6

0.4

, EXCESS PHASE (DEGREES)

0.2

, CURRENT SENSE INPUT THRESHOLD (V

TA = 125°C

2.0 4.0 6.0 8.0

VO, ERROR AMP OUTPUT VOLTAGE (VO)

TA = -55°C

Figure 7. Current Sense Input Threshold

versus Error Amp Output Voltage

-4.0

-8.0

-12

-16

-20

, REFERENCE VOLTAGE CHANGE (mV)

ref

-24 0

Figure 8. Reference Voltage Change

VCC = 15 V

TA = -55°C

TA = 125°C

TA = 25°C

20 40 60 80 100 120

, REFERENCE SOURCE CURRENT (mA)

ref

versus Source Current

VCC = 15 V IO = 1.0 mA to 20 mA TA = 25°C

110

, REFERENCE SHORT CIRCUIT CURRENT (mA)

-55

-25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C)

Figure 9. Reference Short Circuit Current

versus Temperature

VCC = 12 V to 25 V TA = 25°C

VCC = 15 V RL ≤ 0.1 W

V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation

2.0 ms/DIV

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V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

2.0 ms/DIV

Page 6

(

)

LTA

N V

ATURATI

UTPUT ,

sat

-1.0

-2.0

3.0

2.0

1.0

UC3844B, UC3845B, UC2844B, UC2845B

TA = 25°C

TA = -55°C

200 400 600

Source Saturation

(Load to Ground)

VCC = 15 V 80 ms Pulsed Load 120 Hz Rate

TA = -55°C

Sink Saturation

(Load to VCC)

GND

IO, OUTPUT LOAD CURRENT (mA)

TA = 25°C

VCC = 15 V

CL = 1.0 nF

= 25°C

8000

50 ns/DIV

Figure 12. Output Saturation Voltage

Figure 13. Output Waveform

versus Load Current

, SUPPLY CURRENT (mA)

RT = 10 k CT = 3.3 nF

UCX845B

UCX844B

10 20 30 40

VFB = 0 V I

= 0 V

Sense

TA = 25°C

VCC, SUPPLY VOLTAGE (V)

, OUTPUT VOLTAGEV

, SUPPLY CURRENT

VCC = 30 V CL = 15 pF TA = 25°C

100 mA/DIV 20 V/DIV

100 ns/DIV

Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

8−Pin 14−Pin

1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.

2 3 Voltage

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this

4 7 RT/C

5 GND This pin is the combined control circuitry and power ground.

6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced

7 12 V

8 14 V

8 Power

11 V

9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.

2,4,6,13 NC No connection. These pins are not internally connected.

Function Description

This is the inverting input of the Error Amplifier. It is normally connected to the switching power

Feedback

supply output through a resistor divider.

information to terminate the output switch conduction.

The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to V

and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.

ref

and sunk by this pin. The output switches at one−half the oscillator frequency.

ref

This pin is the positive supply of the control IC.

This is the reference output. It provides charging current for capacitor CT through resistor RT.

This pin is a separate power ground return that is connected back to the power source. It is used

Ground

to reduce the effects of switching transient noise on the control circuitry.

The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.

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UC3844B, UC3845B, UC2844B, UC2845B

OPERATING DESCRIPTION

The UC3844B, UC3845B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. A representative block diagram is shown in Figure 16.

Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor C is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip−flop has been incorporated in the UCX844/5B which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the CT discharge period yields output deadtimes programmable from 50% to 70%. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz.

In many noise−sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. A method for multi−unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%.

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of

1.0 MHz with 57 degrees of phase margin (Figure 6). The non−inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 29). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the inverting input of the Current Sense

Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level:

Current Sense Comparator and PWM Latch

f(min)

3.0 (1.0 V) + 1.4 V

≈

0.5 mA

= 8800 W

The UC3844B, UC3845B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground−referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 1 where:

− 1.4 V

Ipk =

(Pin 1)

3 R

Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:

pk(max)

1.0 V

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I

clamp voltage.

pk(max)

A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 24).

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Page 8

UC3844B, UC3845B, UC2844B, UC2845B

ref

8(14)

2.5V

Internal

Bias

3.6V

Oscillator

4(7)

Voltage

1.0mA

Feedback

Input

Output/

Compensation

2(3)

1(1)

Error

Amplifier

GND

5(9)

Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SOIC-14 package.

Reference

Regulator

1.0V

Current Sense

Comparator

ref

UVLO

PWM Latch

7(12)

36V

(See

Text)

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)

= Sink Only Positive True Logic

Capacitor C

Latch “Set" Input

Output/ Compensation

Current Sense Input

Latch “Reset" Input

Output

Figure 16. Representative Block Diagram

Large RT/Small C

Figure 17. Timing Diagram

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Small RT/Large C

Page 9

UC3844B, UC3845B, UC2844B, UC2845B

Undervoltage Lockout

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (V

ref

) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX844B, and 8.4 V/7.6 V for the UCX845B. The V

comparator

ref

upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX844B makes it ideally suited in off−line converter applications where efficient bootstrap startup techniques are required (Figure 30). The UCX845B is intended for lower voltage dc−dc converter applications. A 36 V Zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844B is 11 V and 8.2 V for the UCX845B.

Output

These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pulldown resistor.

The SOIC−14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I

pk(max)

clamp level. The separate VC supply input allows the

designer added flexibility in tailoring the drive voltage independent of VCC. A Zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 23 shows proper power and control ground connections in a current−sensing power MOSFET application.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short−circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on wire−wrap or plug−in prototype boards. High frequency

circuit layout techniques are imperative to prevent pulse−width jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low−current signal and high−current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to VCC, VC, and V

may be required depending upon circuit layout.

ref

This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise−generating components.

ref

8(14)

4(7)

0.01

External

Sync Input

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground.

2(3)

1(1)

Bias

Osc

5(9)

8 4

f +

(RA )2RB)C

5.0k

1.44

MC1455

(max)

 +

8(14)

4(7)

2(3)

1(1)

To Additional UCX84XBs

RA )2R

Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and

Multi−Unit Synchronization

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Bias

Osc

5(9)

Page 10

UC3844B, UC3845B, UC2844B, UC2845B

Clamp

8(14)

4(7)

2(3)

1(1)

7(12)

Bias

Osc

1.0 mA

) 1

+ 0.33x10

1.67

≈

5.0V Ref

 [

7(11)

6(10)

5(8)

3(5)

Clamp

Comp/Latch

R1R

R1) R

Where: 0 ≤ V

pk(max)

Clamp

1.0V

5(9)

-3

≤ 1.0 V

8(14)

4(7)

2(3)

1.0M

1(1)

Soft-Start

Bias

Osc

1.0mA

≈ 3600C in mF

Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit

5.0V Ref

1.0V

5(9)

5.0V Ref

Clamp

1.0V

5(9)

Where: 0 ≤ V

C

R1) R

Clamp

R1R

Comp/Latch

≤ 1.0 V

Clamp

SoftStart

8(14)

4(7)

2(3)

1(1)

MPSA63

≈

+*Inƪ1 *

Bias

Osc

1.0 mA

1.67

) 1

Clamp

Figure 22. Adjustable Buffered Reduction of

Clamp Level with Soft−Start

pk(max)

7(12)

 [

7(11)

6(10)

5(8)

3(5)

Clamp

5.0V Ref

Comp/Latch

Control Circuitry Ground:

To Pin (9)

(12)

(11)

(10)

(8)

(5)

1/4 W

Pin5

If: SENSEFET = MTP10N10M

Then : V

SENSEFET

Power Ground:

To Input Source

Return

 [

Pin5

RSIpkr

DM(on)

RS= 200

 [ 0.075I

DS(on)

 )R

Virtually lossless current sensing can be achieved with the implementation of a SENSEFETt power switch. For proper operation during over-current conditions, a reduction of the I Refer to Figures 20 and 22.

clamp level must be implemented.

pk(max)

Figure 23. Current Sensing Power MOSFET

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Page 11

UC3844B, UC3845B, UC2844B, UC2845B

7(12)

5.0V Ref

Comp/Latch

7(11)

6(10)

5(8)

3(5)

The addition of the RC filter will eliminate

instability caused by the leading edge spike on the current waveform.

Figure 24. Current Waveform Spike Suppression

7(12)

5.0V Ref

Comp/Latch

7(11)

6(10)

5(8)

3(5)

Base Charge

Removal

6(10)

5(8)

3(5)

Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the

The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1.

gate-source circuit.

Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive

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Page 12

UC3844B, UC3845B, UC2844B, UC2845B

7(12)

5.0V Ref

Comp/Latch

7(11)

6(10)

5(8)

3(5)

Isolation

Boundary

VGS Waveforms

50% DC 25% DC

Ipk =

(Pin1)

3 R

- 1.4

Figure 27. Isolated MOSFET Drive

8(14)

Bias

From V

Rf ≥ 8.8k

4(7)

2(3)

1(1)

MCR

101

3905

3903

The MCR101 SCR must be selected for a holding of < 0.5 mA @ T simple two transistor circuit can be used in place of the SCR as shown. All

Osc

1.0 mA 2R

5(9)

. The

A(min)

resistors are 10 k.

Figure 28. Latched Shutdown

1(1)

2(3)

2.5V

1.0mA 2R

5(9)

2.5V

2(3)

1(1)

1.0mA 2R

5(9)

From V

Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current.

Figure 29. Error Amplifier Compensation

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Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current.

Page 13

UC3844B, UC3845B, UC2844B, UC2845B

18k

4.7k

8(14)

33k

4(7)

1.0nF

2(3)

150k

1(1)

Primary: 45 Turns #26 AWG

T1 -

100

0.01

4.7W

115 Vac

MDA

202

Bias

Osc

5(9)

Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10" for a primary inductance of 1.0 mH

5.0V Ref

250

Comp/Latch

MBR1635

3300

MTP

4N50

680pF

2200

MUR110

1000

MUR110

2.7k

0.5

4.7k

56k

1N4935 1N4935

7(12)

100

1N4937

7(11)

6(10)

1N5819

5(8)

3(5)

L2, L3

1.0k

470pF

- 15 mH at 5.0 A, Coilcraft Z7156

- 25 mH at 5.0 A, Coilcraft Z7157

1000

1N4937

5.0V/4.0A

5.0V RTN

12V/0.3A

±12V RTN

-12V/0.3A

Figure 30. 7 W Off−Line Flyback Regulator

Test Conditions Results

Line Regulation: 5.0 V

±12 V

Load Regulation: 5.0 V

±12 V

Output Ripple: 5.0 V

±12 V

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents unless otherwise noted.

Vin = 95 Vac to 130 Vac

D = 50 mV or ±0.5% D = 24 mV or ±0.1%

Vin = 115 Vac, I Vin = 115 Vac, I

= 1.0 A to 4.0 A

out

= 100 mA to 300 mA

out

D = 300 mV or ±3.0% D = 60 mV or ±0.25%

Vin = 115 Vac 40 mV

80 mV

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Page 14

UC3844B, UC3845B, UC2844B, UC2845B

= 15V

PWM Latch

7(12)

34V

7(11)

6(10)

5(8)

3(5)

15 10

VO = 2.5

1.0nF

10k

8(14)

4(7)

2(3)

1(1)

2.5V

Error

Amplifier

Osc

Internal

Bias

0.5mA

UC3845B

Reference Regulator

UVLO

1.0V

Current Sense

5(9)

ref

UVLO

Comparator

3.6V

The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown.

Figure 31. Step−Up Charge Pump Converter

1N5819

Connect to Pin 2 for closed loop operation.

) 1

Output Load Regulation

(Open Loop Configuration)

IO (mA) VO (V)

0 2

9 18 36

1N5819

29.9

28.8

28.3

27.4

24.4

VO ≈ 2 (Vin)

7(12)

PWM Latch

1.0nF

10k

8(14)

4(7)

2(3)

1(1)

2.5V

Error

Amplifier

Internal

Osc

Bias

0.5mA 2R

3.6V

UC3845B

1.0V

Current Sense

5(9)

Reference

Regulator

ref

UVLO

Comparator

UVLO

The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

34V

7(11)

6(10)

5(8)

3(5)

= 15V

15 10

Output Load Regulation

IO (mA) VO (V)

0 2

9 18 32

1N5819

−14.4

−13.2

−12.5

−11.7

−10.6

≈ -V

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Page 15

UC3844B, UC3845B, UC2844B, UC2845B

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping

UC384xBDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC384xBDR2G SOIC−14

2500 Tape & Reel

(Pb−Free)

UC384xBD1G SOIC−8

= 0° to +70°C

(Pb−Free)

UC384xBD1R2G SOIC−8

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC384xBNG PDIP−8

50 Units/Rail

(Pb−Free)

UC284xBDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC284xBDR2G SOIC−14

2500 Tape & Reel

(Pb−Free)

UC284xBD1G SOIC−8

= −25° to +85°C

(Pb−Free)

UC284xBD1R2G SOIC−8

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC284xBNG PDIP−8

50 Units/Rail

(Pb−Free)

UC384xBVDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC384xBVDR2G SOIC−14

2500 Tape & Reel

(Pb−Free)

UC384xBVD1G SOIC−8

= −40° to +105°C

(Pb−Free)

UC384xBVD1R2G SOIC−8

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC384xBVNG PDIP−8

50 Units/Rail

(Pb−Free)

NCV3845BVD1R2G*

= −40° to +125°C

SOIC−8

(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D. x indicates either a 4 or 5 to define specific device part numbers. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

†

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Page 16

UC3844B, UC3845B, UC2844B, UC2845B

MARKING DIAGRAMS

PDIP−8 N SUFFIX CASE 626

UC384xBN

AWL

YYWWG

UC384xBDG

AWLYWW

UC384xBVN

CASE 751A

UC384xBVDG

AWL

YYWWG

SOIC−14

D SUFFIX

AWLYWW

SOIC−8

D1 SUFFIX

CASE 751

UC284xBN

AWL

YYWWG

UC284xBDG

AWLYWW

384xB

ALYW

x = 4 or 5 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package

384xB

ALYWV

284xB ALYW

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Page 17

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

PDIP−8

N SUFFIX

CASE 626−05

ISSUE M

NOTE 5

TOP VIEW

e/2

SIDE VIEW

NOTES:

END VIEW

NOTE 3

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2.

4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN NOM MAX

A −−−− −−−− 0.210

A1 0.015 −−−− −−−−

b 0.014 0.018 0.022 C 0.008 0.010 0.014 D 0.355 0.365 0.400

D1 0.005 −−−− −−−−

E 0.300 0.310 0.325 E1 0.240 0.250 0.280 6.10 6.35 7.11 E2 E3 −−−− −−−− 0.430 −−−− −−−− 10.92

e 0.100 BSC

L 0.115 0.130 0.150

INCHES

0.300 BSC 7.62 BSC

MILLIMETERS

MIN NOM MAX

−−−− −−−− 5.33

0.38 −−−− −−−−

0.35 0.46 0.56

0.20 0.25 0.36

9.02 9.27 10.02

0.13 −−−− −−−−

7.62 7.87 8.26

2.54 BSC

2.92 3.30 3.81

SEATING

PLANE

0.010 CA

END VIEW

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Page 18

−T−

SEATING PLANE

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

−A−

−B−

P 7 PL

0.25 (0.010) B

D 14 PL

0.25 (0.010) A

R X 45

SOLDERING FOOTPRINT

7.04

14X

0.58

14X

1.52

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

__ __

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

DIMENSIONS: MILLIMETERS

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1.27 PITCH

Page 19

−Y−

−Z−

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

−X−

0.25 (0.010) Z

0.25 (0.010)

X 45

SXS

SEATING PLANE

0.10 (0.004)

SOLDERING FOOTPRINT*

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020

G 1.27 BSC 0.050 BSC

H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

1.52

0.060

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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Phone: 81−3−5817−1050

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For additional information, please contact your loca Sales Representative

UC3844B/D