Datasheet UC3843AN, UC3843AD, UC3842AN Datasheet (Motorola)

Page 1

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The UC3842A, UC3843A series of high performance fixed frequency current mode controllers are specifically designed for off–line and dc–to–dc converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET.

Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting, programmable output deadtime, and a latch for single pulse metering.

These devices are available in an 8–pin dual–in–line plastic package as well as the 14–pin plastic surface mount (SO–14). The SO–14 package has separate power and ground pins for the totem pole output stage.

The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally suited for off–line converters. The UCX843A is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).

• Trimmed Oscillator Discharge Current for Precise Duty Cycle Control

• Current Mode Operation to 500 kHz

• Automatic Feed Forward Compensation

• Latching PWM for Cycle–By–Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• High Current Totem Pole Output

• Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

• Direct Interface with Motorola SENSEFET Products

Simplified Block Diagram

7(12)

ref

8(14)

RTC

4(7)

Voltage

Feedback

Input

2(3)

Output

Compensation

1(1)

5.0V

Oscillator

+ –

Error

Amplifier

Pin numbers in parenthesis are for the D suffix SO–14 package.

Undervoltage

Lockout

Gnd 5(9)

Reference

ref

Latching

PWM

Undervoltage

Lockout

7(11)

Output

6(10)

Power Ground

5(8)

3(5)

Current Sense Input

Order this document by UC3842A/D

   

HIGH PERFORMANCE

CURRENT MODE

CONTROLLERS

N SUFFIX

PLASTIC PACKAGE

CASE 626

D SUFFIX

PLASTIC PACKAGE

CASE 751A

(SO–14)

Compensation

Voltage Feedback

Current Sense

RT/C

Compensation

Voltage Feedback

Current Sense

RT/C

ORDERING INFORMATION

Device

UC3842AD UC3843AD UC3842AN UC3843AN UC2842AD UC2843AD UC2842AN UC2843AN

Temperature Range

TA = – 25° to +85°C

PIN CONNECTIONS

1 2 3

1 2

3 4

5 6

Operating

TA = 0° to +70°C

(T op View)

(T op V iew)

ref

Output Gnd

ref

Output

Gnd Power Ground

Package

SO–14 SO–14 Plastic Plastic SO–14 SO–14 Plastic Plastic

MOTOROLA ANALOG IC DEVICE DATA

 Motorola, Inc. 1996 Rev 1

Page 2

UC3842A, 43A UC2842A, 43A

MAXIMUM RATINGS

Rating Symbol Value Unit

Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 1) I

Output Energy (Capacitive Load per Cycle) W 5.0 µJ Current Sense and Voltage Feedback Inputs V Error Amp Output Sink Current I

Power Dissipation and Thermal Characteristics

D Suffix, Plastic Package

Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air

N Suffix, Plastic Package

Maximum Power Dissipation @ TA = 25°C

Thermal Resistance, Junction–to–Air Operating Junction Temperature T Operating Ambient Temperature

UC3842A, UC3843A

θJA

UC2842A, UC2843A

Storage Temperature Range T

stg

1.0 A

– 0.3 to + 5.5 V

10 mA

862 145

1.25 100

+ 150 °C

0 to + 70

– 25 to + 85

– 65 to + 150 °C

°C/W

°C

ELECTRICAL CHARACTERISTICS (V

= 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = T

low

to T

high

[Note 3],

unless otherwise noted.)

UC284XA UC384XA

Characteristics Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) V Line Regulation (VCC = 12 V to 25 V) Reg Load Regulation (IO = 1.0 mA to 20 mA) Reg T emperature Stability T Total Output V ariation over Line, Load, Temperature V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) V

ref

line load S

ref

4.95 5.0 5.05 4.9 5.0 5.1 V – 2.0 20 – 2.0 20 mV – 3.0 25 – 3.0 25 mV – 0.2 – – 0.2 – mV/°C

4.9 – 5.1 4.82 – 5.18 V – 50 – – 50 – µV

Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – – 5.0 – mV Output Short Circuit Current I

– 30 – 85 – 180 – 30 – 85 – 180 mA

OSCILLATOR SECTION

Frequency

TJ = 25°C TA = T

low

to T

high

Frequency Change with Voltage (VCC = 12 V to 25 V) ∆f Frequency Change with Temperature

TA = T

low

to T

high

Oscillator Voltage Swing (Peak–to–Peak) V Discharge Current (V

TJ = 25°C

TA = T

NOTES: 1. Maximum Package power dissipation limits must be observed.

to T

low

2.Adjust VCC above the Startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible T

= –20°C for UC3842A, UC3843A T

low

= –25°C for UC2842A, UC2843A T

low

high

osc

= 2.0 V)

osc

47 46

osc/∆V

∆f

osc/∆T

dischg

osc

– 0.2 1.0 – 0.2 1.0 % – 5.0 – – 5.0 – %

– 1.6 – – 1.6 – V

7.5

7.2

= +70°C for UC3842A, UC3843A

high

= +85°C for UC2842A, UC2843A

high

8.4

–

9.3

–

9.5

47 46

7.5

7.2

8.4

–

9.3

–

9.5

kHz

MOTOROLA ANALOG IC DEVICE DATA

Page 3

UC3842A, 43A UC2842A, 43A

ELECTRICAL CHARACTERISTICS (V

= 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = T

low

to T

high

[Note 3],

unless otherwise noted.)

UC284XA UC384XA

Characteristics Symbol Min Typ Max Min Typ Max Unit

ERROR AMPLIFIER SECTION

Voltage Feedback Input (VO = 2.5 V) V Input Bias Current (VFB = 2.7 V) I Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A

FB IB

VOL

2.45 2.5 2.55 2.42 2.5 2.58 V – –0.1 –1.0 – –0.1 –2.0 µA

65 90 – 65 90 – dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – 0.7 1.0 – MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 – 60 70 – dB Output Current

Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V)

Sink

Source

2.0

–0.512–1.0

– –

2.0

–0.512–1.0

– –

Output Voltage Swing

High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to V

, VFB = 2.7 V)

ref

5.0 –

6.2

0.8

1.1

–

5.0 –

0.8

6.2

–

1.1

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 4 & 5) A Maximum Current Sense Input Threshold (Note 4) V Power Supply Rejection Ratio

PSRR

VCC = 12 to 25 V (Note 4) Input Bias Current I Propagation Delay (Current Sense Input to Output) t

PLH(in/out)

2.85 3.0 3.15 2.85 3.0 3.15 V/V

0.9 1.0 1.1 0.9 1.0 1.1 V

– 70 – – 70 – – –2.0 –10 – –2.0 –10 µA – 150 300 – 150 300 ns

OUTPUT SECTION

Output Voltage

Low State (I

High State (I

Output Voltage with UVLO Activated

VCC = 6.0 V, I Output Voltage Rise T ime (CL = 1.0 nF, TJ = 25°C) t Output Voltage Fall T ime (CL = 1.0 nF, TJ = 25°C) t

Sink Sink Sink

Sink

= 20 mA) = 200 mA) = 20 mA) = 200 mA)

= 1.0 mA

OL(UVLO)

r f

–

– 13 12

0.1

1.6

13.5

13.4

0.4

2.2

–

– – –

13 12

0.1

1.6

13.5

13.4

0.4

2.2 – –

– 0.1 1.1 – 0.1 1.1 – 50 150 – 50 150 ns – 50 150 – 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold

UCX842A UCX843A

Minimum Operating Voltage After Turn–On

UCX842A UCX843A

CC(min)

7.8

9.0

7.0

8.4

7.6

9.0

8.2

14.5

7.8

8.5

7.0

8.4

7.6

17.5

9.0

11.5

8.2

PWM SECTION

Duty Cycle

Maximum Minimum

max

min

–

– 0

–

– 0

TOTAL DEVICE

Power Supply Current (Note 2)

Startup: (VCC = 6.5 V for UCX843A,

(VCC = 14 V for UCX842A) Operating

Power Supply Zener Voltage (ICC = 25 mA) V

NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible T

= –20°C for UC3842A, UC3843A T

low

= –25°C for UC2842A, UC2843A T

low

4.This parameter is measured at the latch trip point with VFB = 0 V.

5.Comparator gain is defined as: A

∆V Output Compensation

∆V Current Sense Input

– –

= +70°C for UC3842A, UC3843A

high

= +85°C for UC2842A, UC2843A

high

30 36 – 30 36 – V

0.5 12

1.0 17

– –

0.5 12

1.0 17

MOTOROLA ANALOG IC DEVICE DATA

Page 4

UC3842A, 43A UC2842A, 43A

Figure 1. Timing Resistor versus

Oscillator Frequency

80 50

Ω

8.0

5.0

, TIMING RESISTOR (k )

VCC = 15 V

2.0

0.8 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M

TA = 25

, OSCILLAT OR FREQUENCY (Hz)

OSC

Figure 3. Oscillator Discharge Current

versus T emperature

9.0

VCC = 15 V V

= 2.0 V

8.5

OSC

Figure 2. Output Deadtime versus

Oscillator Frequency

100

VCC = 15 V

5.0

2.0

% DT, PERCENT OUTPUT DEADTIME

1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M

TA = 25

, OSCILLAT OR FREQUENCY (Hz)

OSC

Figure 4. Maximum Output Duty Cycle

versus Timing Resistor

100

VCC = 15 V CT = 3.3 nF

TA = 25

dischg

= 7.2 mA

8.0

, DISCHARGE CURRENT (mA)

7.5

dischg

7.0 –55 –25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (

Figure 5. Error Amp Small Signal

Transient Response

VCC = 15 V

2.55 V

2.5 V

AV = –1.0 TA = 25

, MAXIMUM OUTPUT DUTY CYCLE (%)

max

800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k

= 9.5 mA

dischg

RT, TIMING RESISTOR (Ω)

Figure 6. Error Amp Large Signal

Transient Response

VCC = 15 V

20 mV/DIV

3.0 V

2.5 V

AV = –1.0

TA = 25

200 mV/DIV

2.45 V

0.5 µs/DIV

2.0 V

0.1 µs/DIV

MOTOROLA ANALOG IC DEVICE DATA

Page 5

UC3842A, 43A UC2842A, 43A

Figure 7. Error Amp Open Loop Gain and

Phase versus Frequency

100

, OPEN LOOP VOL TAGE GAIN (dB)

VOL

–20

100 1.0 k 10 k 100 k 1.0 M

Gain

f, FREQUENCY (Hz)

Figure 9. Reference V oltage Change

versus Source Current

–4.0

–8.0

VCC = 15 V

VO = 2.0 V to 4.0 V

RL = 100 K

TA = 25

Phase

VCC = 15 V

120

150 180

10 M10

1.2

1.0

0.8

0.6

0.4

, EXCESS PHASE (DEGREES)

0.2

, CURRENT SENSE INPUT THRESHOLD (V)

110

Figure 8. Current Sense Input Threshold

versus Error Amp Output Voltage

VCC = 15 V

TA = 25°C

TA = 125°C

TA = –55°C

2.0 4.0 6.0 8.0

VO, ERROR AMP OUTPUT VOLTAGE (V)

Figure 10. Reference Short Circuit Current

versus T emperature

VCC = 15 V

≤

0.1

Ω

–12

–16

, REFERENCE VOLTAGE CHANGE (mV)

–20

ref

∆

–24

0 20 40 60 80 100 120

TA = 125°C

TA = 25°C

, REFERENCE SOURCE CURRENT (mA)

ref

TA = 55°C

Figure 11. Reference Load Regulation

VCC = 15 V

IO = 1.0 mA to 20 mA

TA = 25

, REFERENCE SHORT CIRCUIT CURRENT (mA)

–55 –25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (

Figure 12. Reference Line Regulation

VCC = 12 V to 25 V

TA = 25

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

∆

2.0 ms/DIV

MOTOROLA ANALOG IC DEVICE DATA

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

∆

2.0 ms/DIV

Page 6

–1.0 –2.0

Figure 13. Output Saturation Voltage

versus Load Current

TA = 25°C

Source Saturation

(Load to Ground)

TA = –55°C

UC3842A, 43A UC2842A, 43A

VCC = 15 V

s Pulsed Load

120 Hz Rate

90%

Figure 14. Output Waveform

VCC = 15 V CL = 1.0 nF

TA = 25

3.0

2.0

, OUTPUT SA TURATION VOLTAGE (V)

1.0

sat

, OUTPUT VOL TAGEV

, SUPPLY CURRENT

TA = –55°C

Sink Saturation

(Load to VCC)

IO, OUTPUT LOAD CURRENT (mA)

Gnd

Figure 15. Output Cross Conduction

VCC = 30 V CL = 15 pF

TA = 25

100 ns/DIV

TA = 25°C

8006004002000

100 mA/DIV 20 V/DIV

10%

50 ns/DIV

Figure 16. Supply Current versus

Supply V oltatage

, SUPPLY CURRENT (mA)

UCX843A

010203040

UCX842A

VCC , SUPPLY VOLTAGE

RT = 10 k CT = 3.3 nF VFB = 0 V

= 0 V

Sense

TA = 25

MOTOROLA ANALOG IC DEVICE DATA

Page 7

UC3842A, 43A UC2842A, 43A

Figure 17. Representative Block Diagram

7(12)

ref

8(14)

Voltage Feedback

Input

Output Compensation

4(7)

Reference

Regulator

Internal

2.5V R

2(3)

1(1)

–

Error

Amplifier

Pin numbers in parenthesis are for the D suffix SO–14 package.

Bias

Oscillator +

1.0mA

3.6V

1.0V Current Sense

Comparator

5(9)Gnd

–

UVLO

+ –

ref

–

UVLO

– +

PWM Latch

+ –

36V

–

Sink Only

Positive True Logic

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input 3(5)

Capacitor C

Latch

‘‘Set’’ Input

Output/

Compensation

Current Sense

Input

Latch

‘‘Reset’’ Input

Output

Figure 18. Timing Diagram

Large RT/Small C

Small RT/Large C

MOTOROLA ANALOG IC DEVICE DATA

Page 8

UC3842A, 43A UC2842A, 43A

OPERA TING DESCRIPTION

The UC3842A, UC3843A series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 17.

Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor C is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates and internal blanking pulse that holds the center

input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency . The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ± 10% at TJ = 25°C. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 3 and 4.

In many noise sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 21. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 7). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 30). The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft–start interval (Figures 23, 24). The Error Amp minimum feedback resistance is limited by the

amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level:

f(min)

Current Sense Comparator and PWM Latch

The UC3842A, UC3843A operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where:

Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I voltage.

A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 26.

3.0 (1.0 V) + 1.4 V

≈

Ipk =

pk(max)

0.5 mA

(Pin 1)

3 R

– 1.4 V

1.0 V R

= 8800 Ω

pk(max)

clamp

MOTOROLA ANALOG IC DEVICE DATA

Page 9

UC3842A, 43A UC2842A, 43A

PIN FUNCTION DESCRIPTION

8–Pin 14–Pin

1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation. 2 3 Voltage

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this

4 7 RT/C

5 – Gnd This pin is the combined control circuitry and power ground (8–pin package only). 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced

7 12 V 8 14 V

– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back to the

– 11 V

– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected back to the

– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.

Function Description

Feedback

ref

This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.

information to terminate the output switch conduction. The Oscillator frequency and maximum Output duty cycle are programmed by connecting

resistor RT to V

and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through

resistor RT.

power source. It is used to reduce the effects of switching transient noise on the control circuitry . The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With

a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.

power source ground.

and capacitor CT to ground. Operation to 500 kHz is possible.

ref

Undervoltage Lockout

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (V

) are each

ref

monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842A, and 8.4 V/7.6 V for the UCX843A. The V

comparator upper

ref

and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of the UCX842A makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 33). The UCX843A is intended for lower voltage dc to dc converter applications. A 36 V zener is connected as a shunt regulator form VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX842A is 11 V and

8.2 V for the UCX843A.

Output

These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFET s. It is capable of up to±1.0 A peak drive current and

has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor.

The SO–14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I

pk(max)

clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFET s in systems where VCC is greater that 20 V. Figure 25 shows proper power and control ground connections in a current sensing power MOSFET application.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the UC384XA. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.

MOTOROLA ANALOG IC DEVICE DATA

Page 10

UC3842A, 43A UC2842A, 43A

DESIGN CONSIDERATIONS

Do not attempt to construct the converter on

wire–wrap or plug–in prototype boards. High Frequency

circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and V

may be required depending upon circuit layout. This

ref

provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components.

Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed–loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2 until the next oscillator cycle. The unstable condition can be shown if a pertubation is added to the control voltage, resulting in a small ∆I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1. The minimum current at the next cycle (t3) decreases to (∆I +

I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on

∆

each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 19B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the ∆I pertubation will decrease to zero on succeeding cycles. This compensation ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32).

Figure 19. Continuous Current Waveforms

m2 m m

(A)

2 1

∆

I + ∆I

Control Voltage

Inductor

Current

∆

Oscillator Period

∆

I + ∆I

(B)

Control Voltage

∆

Oscillator Period

Inductor

Current

MOTOROLA ANALOG IC DEVICE DATA

Page 11

UC3842A, 43A UC2842A, 43A

Figure 20. External Clock Synchronization

Figure 21. External Duty Cycle Clamp and

Multi Unit Synchronization

ref 8(14)

External Sync Input

0.01

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground.

4(7)

2(3)

1(1)

Bias

Osc

+ –

5(9)

f =

(RA + 2RB)C

5.0k

1.44

+ –

MC1455

max

RA + 2R

Figure 22. Adjustable Reduction of Clamp Level Figure 23. Soft–Start Circuit

Clamp

8(14)

4(7)

2(3)

1(1)

R R

7(12)

5.0V

5(9)

–

Clamp

1.0V

R1 R

R1 + R

ref

+ –

– +

Bias

Osc

1.0mA

1.67 2

–

+ 1

+ 0.33 x 10 – 3I

–

Comp/Latch

pk(max)

–

Where: 0 ≤ V

7(11)

6(10)

5(8)

3(5)

VClamp

Clamp

≤ 1.0 V

8(14)

4(7)

2(3)

1.0M 1(1)

Soft–Start

R R

+ –



3600C in µF

Bias

Osc

1.0mA

8(14)

4(7)

2(3)

1(1)

T o Additional

UCX84XA’ s

5(9)

+ –

–

5.0V

1.0V

Bias

Osc

5(9)

ref

+ –

–

Figure 24. Adjustable Buffered Reduction of

Clamp Level with Soft–Start

5.0V

–

Clamp

1.0V

5(9)

Softstart

ref

+ –

–

Comp/Latch

VClamp

= – In 1 –

8(14)

4(7)

2(3)

1(1)

MPSA63

Clamp

Bias

Osc

1.0mA

+ –

R R

1.67 2

+ 1

pk(max)

MOTOROLA ANALOG IC DEVICE DATA

7(12)

–

Where: 0 ≤ V

Clamp

7(11)

6(10)

5(8)

3(5)

≤ 1.0 V

R1 + R

R1 R

Figure 25. Current Sensing Power MOSFET

5.0V

ref

+ –

–

Comp/Latch

Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the I

pk(max)

(12)

–

(11)

(10)

Control CIrcuitry

Ground:

To Pin (9)

clamp level must be implemented. Refer to Figures 22 and 24.

(8)

(5)

1/4 W

SENSEFET

Power Ground

T o Input Source

RS Ipk r

5 =

Then: V

DM(on)

RS = 200

5 = 0.075 I

If: SENSEFET = MTP10N10M

Return

DS(on) + R

Page 12

UC3842A, 43A UC2842A, 43A

Figure 26. Current Waveform Spike Suppression

7(12)

5.0V

ref

+ –

–

– +

The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform.

+ –

Comp/Latch

–

7(11)

6(10)

5(8)

3(5)

Figure 27. MOSFET Parasitic Oscillations

7(12)

5.0V

ref

+ –

–

– +

Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate–source circuit.

–

Comp/Latch

–

Figure 28. Bipolar Transistor Drive Figure 29. Isolated MOSFET Drive

–

Base Charge

Removal

6(1)

5(8)

3(5)

5.0V

ref

+ –

–

– +

+ –

Comp/Latch

7(12)

–

7(11)

6(1)

5(8)

3(5)

Boundary

Isolation

7(11)

6(10)

5(8)

3(5)

+ 0

–

50% DC 25% DC

Ipk =

VGS Waveforms

+ 0

–

– 1.4

(pin 1)

3 R

The totem–pole output can furnish negative base current for enhanced transistor turn–off, with the addition of capacitor C1.

Figure 30. Latched Shutdown Figure 31. Error Amplifier Compensation

8(14)

4(7)

2(3)

1(1)

MCR

101

The MCR101 SCR must be selected for a holding of less than 0.5 mA at T

. The simple two transistor circuit can be used in place of the SCR as

A(min)

shown. All resistors are 10 k.

3905

3903

Bias

Osc

1.0mA

+ –

5(9)

From V

Error Amp compensation circuit for stabilizing any current–mode topology except for boost and flyback converters operating with continuous inductor current.

From V

Error Amp compensation circuit for stabilizing current–mode boost and flyback topologies operating with continuous inductor current.

2.5V

2(3)

1(1)

2(3)

1(1)

1.0mA

+ –

2.5V

5(9)

1.0mA

+ –

5(9)

MOTOROLA ANALOG IC DEVICE DATA

Page 13

UC3842A, 43A UC2842A, 43A

Figure 32. Slope Compensation

7(12)

8(14)

MPS3904

Slope

From V

The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.

4(7)

2(3)

1(1)

Bias

Osc

1.0mA

–

–3.0 m

5(9)

–m

1.0V

–

5.0V

–

ref

–

Comp/Latch

S R

Figure 33. 27 Watt Off–Line Flyback Regulator

Ω

18k

4.7k

0.01

10k

4700pF

100pF

115Vac

8(14)

4(7)

2(3)

1(1)

150k

4.7

–

Osc

Bias

MDA

202

5(9)

Test Conditions Results

Line Regulation: 5.0 V

Vin = 95 Vac to 130 Vac ∆ = 50 mV or ± 0.5%

± 12 V

Load Regulation: 5.0 V

± 12 V

Output Ripple: 5.0 V

Vin = 115 Vac, I Vin = 115 Vac, I

Vin = 115 Vac 40 mV

± 12 V

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents, unless otherwise noted.

250

5.0V

ref

+ –

–

Comp/Latch

= 1.0 A to 4.0 A

out

= 100 mA to 300 mA

out

56k

7(12)

+ –

∆ = 24 mV or ± 0.1% ∆ = 300 mV or ± 3.0%

∆ = 60 mV or ± 0.25%

100

7(11)

6(10)

5(8) 3(5)

80 mV

+ –

4.7k

1N4935 1N4935

1N4937

Ω

1.0k

470pF

pp pp

3300pF

MTP 4N50

0.5

Ω

7(11)

6(10)

5(8)

3(5)

MBR1635

2200 1000

MUR110

1000

1000 10

MUR110

680pF

2.7k

L1 – 15

L2, L3 – 25

T1 – Primary: 45 Turns # 26 AWG

T1 – Secondary

T1 – (2 strands) Bifiliar Wound

T1 – Secondary 5.0 V: 4 Turns (six strands)

T1 – #26 Hexfiliar Wound

T1 – Secondary Feedback: 10 Turns #30 AWG

T1 – (2 strands) Bifiliar Wound T1 – Core: Ferroxcube EC35–3C8 T1 – Bobbin: Ferroxcube EC35PCB1 T1 – Gap

1N4937

H at 5.0 A, Coilcraft Z7156.

H at 1.0 A, Coilcraft Z7157.

≈

0.01” for a primary inductance of 1.0 mH

5.0V/4.0A

5.0V RTN 12V/0.3A

+L2

12V RTN

–12V/0.3A

12 V: 9 Turns # 30 AWG

MOTOROLA ANALOG IC DEVICE DATA

Page 14

NOTE 2

–T–

SEATING PLANE

–A–

–T–

SEATING PLANE

–A–

14 8

D 14 PL

0.25 (0.010) A

UC3842A, 43A UC2842A, 43A

OUTLINE DIMENSIONS

–B–

0.13 (0.005) B

–B–

7 PL

0.25 (0.010) B

N SUFFIX

PLASTIC PACKAGE

CASE 626–05

ISSUE K

D SUFFIX

PLASTIC PACKAGE

CASE 751A–03

(SO–14) ISSUE F

X 45

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050

J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC M ––– 10 ––– 10 N 0.76 1.01 0.030 0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

____

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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◊

MOTOROLA ANALOG IC DEVICE DATA

UC3842A/D

*UC3842A/D*