Datasheet UC3842BD1G, UC3842BNG Specification

UC3842B, UC3843B, UC2842B, UC2843B

High Performance Current Mode Controllers

The UC3842B, UC3843B series are high performance fixed frequency current mode controllers. They are specifically designed for Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET.

Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single pulse metering.

These devices are available in an 8−pin dual−in−line and surface mount (SOIC−8) plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage.

The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off−line converters. The UCX843B is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and

7.6 V (off).

Features

• Trimmed Oscillator for Precise Frequency Control

• Oscillator Frequency Guaranteed at 250 kHz

• Current Mode Operation to 500 kHz

• Automatic Feed Forward Compensation

• Latching PWM for Cycle−By−Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• High Current Totem Pole Output

• Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

• This is a Pb−Free and Halide−Free Device

V

7(12)

CC

V

ref

8(14)

R

T/CT

4(7)

Voltage

Feedback

Input

2(3)

Output

Compensation

1(1)

Pin numbers in parenthesis are for the D suffix SOIC−14 package.

+

-

Error

Amplifier

R

Oscillator

V

Undervoltage

Lockout

GND 5(9)

5.0V

Reference

ref

Latching

PWM

Figure 1. Simplified Block Diagram

V

CC

Undervoltage

Lockout

V

7(11)

Output

6(10)

5(8)

3(5)

C

Power Ground

Current Sense Input

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PDIP−8

N SUFFIX

8

1

14

1

8

1

CASE 626

SOIC−14

D SUFFIX

CASE 751A

SOIC−8

D1 SUFFIX

CASE 751

PIN CONNECTIONS

(Top View)

8

V

ref

7

V

CC

6

Output

5

GND

14

V

ref

13

NC

12

V

CC

11

V

C

10

Output

9

GND

8

Power Ground

Compensation

Voltage Feedback

Current Sense

R

T/CT

Compensation

NC

Voltage Feedback

NC

Current Sense

NC

RT/C

1

2

3

4

1

2

3

4

5

6

7

T

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking section on page 19 of this data sheet.

July, 2011 − Rev. 15

1 Publication Order Number:

UC3842B/D

UC3842B, UC3843B, UC2842B, UC2843B

MAXIMUM RATINGS

Rating Symbol Value Unit

Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, V

C

Total Power Supply and Zener Current (ICC + IZ) 30 mA

Output Current, Source or Sink I

O

Output Energy (Capacitive Load per Cycle) W 5.0

Current Sense and Voltage Feedback Inputs V

Error Amp Output Sink Current I

in

O

Power Dissipation and Thermal Characteristics

D Suffix, Plastic Package, SOIC−14 Case 751A

Maximum Power Dissipation @ T

= 25°C

A

Thermal Resistance, Junction−to−Air

P

D

R

q

JA

D1 Suffix, Plastic Package, SOIC−8 Case 751

Maximum Power Dissipation @ T Thermal Resistance, Junction−to−Air

N Suffix, Plastic Package, Case 626

Maximum Power Dissipation @ T Thermal Resistance, Junction−to−Air

Operating Junction Temperature T

Operating Ambient Temperature

= 25°C

A

= 25°C

A

P

D

R

q

JA

P

D

R

q

JA

J

T

A

UC3842B, UC3843B UC2842B, UC2843B

UC3842BV, UC3843BV

Storage Temperature Range T

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 4000 V per JEDEC Standard JESD22-A114B Machine Model Method 200 V per JEDEC Standard JESD22-A115-A

2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78

30 V

1.0 A

mJ

− 0.3 to + 5.5 V

10 mA

862 145

702 178

1.25 100

mW

°C/W

mW

°C/W

W

°C/W

+150 °C

°C

0 to 70

− 25 to + 85

−40 to +105

− 65 to +150 °C

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2

UC3842B, UC3843B, UC2842B, UC2843B

ELECTRICAL CHARACTERISTICS (V

is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)

T

A

= 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

CC

UC284XB UC384XB, XBV

Characteristics Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (I

Line Regulation (VCC = 12 V to 25 V) Reg

Load Regulation (IO = 1.0 mA to 20 mA) Reg

Temperature Stability T

Total Output Variation over Line, Load, and Temperature V

Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) V

= 1.0 mA, TJ = 25°C) V

O

ref

S

ref

n

line

load

4.95 5.0 5.05 4.9 5.0 5.1 V

− 2.0 20 − 2.0 20 mV

− 3.0 25 − 3.0 25 mV

− 0.2 − − 0.2 − mV/°C

4.9 − 5.1 4.82 − 5.18 V

− 50 − − 50 −

Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV

Output Short Circuit Current I

SC

− 30 − 85 −180 − 30 − 85 −180 mA

OSCILLATOR SECTION

Frequency

T

= 25°C

J

= T

T

to T

A

low

high

TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)

Frequency Change with Voltage (VCC = 12 V to 25 V)

Frequency Change with Temperature, TA = T

low

to T

high

Oscillator Voltage Swing (Peak−to−Peak) V

Discharge Current (V

= 25°C, TA = T

T

J

OSC

low

= 2.0 V)

to T

high

UC284XB, UC384XB

= T

T

to T

A

low

UC384XBV

high

Df

f

OSC

I

dischg

/DV

/DT

49 48

225

52

−

250

55 56

275

49 48

225

52

−

250

55 56

275

− 0.2 1.0 − 0.2 1.0 %

− 1.0 − − 0.5 − %

− 1.6 − − 1.6 − V

7.8

7.5

8.3

−

8.8

−

8.8

−

7.8

7.6

−

7.2

8.3

8.8

−

8.8

−

8.8

ERROR AMPLIFIER SECTION

Voltage Feedback Input (V

Input Bias Current (VFB = 5.0 V) I

Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A

= 2.5 V) V

O

FB

IB

VOL

2.45 2.5 2.55 2.42 2.5 2.58 V

− − 0.1 −1.0 − − 0.1 − 2.0

65 90 − 65 90 − dB

Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz

Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB

Output Current

Sink (V

O

Source (V

= 1.1 V, VFB = 2.7 V)

= 5.0 V, VFB = 2.3 V)

O

I

Sink

I

Source

2.0

− 0.512−1.0

−

2.0

− 0.512−1.0

−

Output Voltage Swing

High State (R Low State (R

= 15 k to ground, VFB = 2.3 V)

L

= 15 k to V

L

, VFB = 2.7 V)

ref

UC284XB, UC384XB

UC384XBV

V

OH

V

OL

5.0

6.2

−

0.8

−

1.1

−

5.0

−

6.2

−

0.8

−

0.8

−

1.1

1.2

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 5 and 6)

UC284XB, UC384XB

UC384XBV

Maximum Current Sense Input Threshold (Note 5)

UC284XB, UC384XB

UC384XBV

A

V

th

2.85−3.0−3.15−2.85

2.85

0.9

−

1.0−1.1

0.9

−

0.85

3.0

1.0

3.15

3.25

1.1

Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5) PSRR − 70 − − 70 − dB

Input Bias Current I

Propagation Delay (Current Sense Input to Output) t

PLH(In/Out)

IB

− − 2.0 −10 − − 2.0 −10

− 150 300 − 150 300 ns

3. Adjust VCC above the Startup threshold before setting to 15 V.

4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV

T

low

T

= +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BV

high

5. This parameter is measured at the latch trip point with V

6. Comparator gain is defined as: A

DV Output Compensation

V

DV Current Sense Input

FB

= 0 V.

mV

kHz

mA

V

V/V

V

mA

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3

UC3842B, UC3843B, UC2842B, UC2843B

ELECTRICAL CHARACTERISTICS (V

T

is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)

A

= 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

CC

UC284XB UC384XB, XBV

Characteristics Symbol Min Typ Max Min Typ Max Unit

OUTPUT SECTION

Output Voltage

Low State (I

= 20 mA)

Sink

= 200 mA) UC284XB, UC384XB

(I

Sink

UC384XBV

High State (I

= 20 mA) UC284XB, UC384XB

Source

UC384XBV

= 200 mA)

(I

Source

Output Voltage with UVLO Activated (VCC = 6.0 V, I

= 1.0 mA) V

Sink

OL(UVLO)

Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) t

Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) t

V

OL

V

OH

r

f

−

13

12

0.1

−

1.6

−

13.5

−

13.4

0.4

2.2

−

13

12.9 12

0.1

1.6

13.5

13.4

− 0.1 1.1 − 0.1 1.1 V

− 50 150 − 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold (V

Minimum Operating Voltage After Turn−On (VCC)

CC

)

UCX842B, BV UCX843B, BV

V

CC(min)

th

15

7.8168.4179.0

9.0

7.0107.6118.2

14.5

7.8168.4

8.5

7.0107.6

PWM SECTION

Duty Cycle

Maximum UC284XB, UC384XB

Maximum UC384XBV

Minimum

DC

(max)

(min)

94

96

−

94

−

0

93

96 96

−

TOTAL DEVICE

Power Supply Current

Startup (V

Startup V

= 6.5 V for UCX843B,

CC

14 V for UCX842B, BV)

CC

(Note 7)

Power Supply Zener Voltage (ICC = 25 mA) V

I

+ I

CC

C

−

0.3120.5

−

Z

30 36 − 30 36 − V

17

−

0.3120.5

7. Adjust VCC above the Startup threshold before setting to 15 V.

8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV

T

low

= +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BV

T

high

0.4

V

2.2

2.3

−

V

17.5

9.0

V

11.5

8.2

%

−

0

mA

17

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4

UC3842B, UC3843B, UC2842B, UC2843B

Ω

, TIMING RESISTOR (k ) R

T

80

50

20

8.0

5.0

2.0

0.8

9.0

8.5

VCC = 15 V TA = 25°C

f

, OSCILLATOR FREQUENCY (kHz)

OSC

Figure 2. Timing Resistor

versus Oscillator Frequency

VCC = 15 V V

OSC

= 2.0 V

100

1. CT = 10 nF

2. C

= 5.0 nF

50

T

3. C

= 2.0 nF

T

4. C

= 1.0 nF

T

5. C

= 500 pF

20

T

6. C

7. CT = 100 pF

10

= 200 pF

T

1

5.0

2.0

% DT, PERCENT OUTPUT DEADTIME

1.0 M500 k200 k100 k50 k20 k10 k

1.0

f

, OSCILLATOR FREQUENCY (kHz)

OSC

2

5

VCC = 15 V T

= 25°C

A

4

3

7

6

1.0 M500 k200 k100 k50 k20 k10 k

Figure 3. Output Deadtime

versus Oscillator Frequency

100

90

80

8.0

, DISCHARGE CURRENT (mA)

7.5

dischg

I

7.0

2.55 V

2.50 V

2.45 V

-55

-25 0 25 50 75 100 125 T

, AMBIENT TEMPERATURE (°C)

A

Figure 4. Oscillator Discharge Current

versus Temperature

VCC = 15 V A

= -1.0

V

TA = 25°C

, MAXIMUM OUTPUT DUTY CYCLE (%)

D

3.0 V

2.5 V

20 mV/DIV

2.0 V

max

I

= 8.54 mA

70

60

50

40

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

0.8

dischg

, TIMING RESISTOR (kW)

R

T

VCC = 15 V C T

Figure 5. Maximum Output Duty Cycle

versus Timing Resistor

= 3.3 nF

T

= 25°C

A

VCC = 15 V A

= -1.0

V

TA = 25°C

20 mV/DIV

Figure 6. Error Amp Small Signal

Transient Response

1.0 ms/DIV0.5 ms/DIV

Figure 7. Error Amp Large Signal

Transient Response

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5

UC3842B, UC3843B, UC2842B, UC2843B

ÄÄÄ

100

80

60

40

20

, OPEN LOOP VOLTAGE GAIN (dB)

0

VOL

A

-20

Figure 8. Error Amp Open Loop Gain and

0

-4.0

-8.0

VCC = 15 V V

= 2.0 V to 4.0 V

O

Gain

RL = 100 K T

= 25°C

A

Phase

100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Phase versus Frequency

VCC = 15 V

0

30

60

90

120

150

180

10 M10

1.2

1.0

0.8

0.6

0.4

, EXCESS PHASE (DEGREES)

0.2

φ

, CURRENT SENSE INPUT THRESHOLD (V)

th

V

110

90

VCC = 15 V

TA = 25°C

TA = 125°C

TA = -55°C

0

2.0 4.0 6.0 8.0

, ERROR AMP OUTPUT VOLTAGE (V)

V

O

Figure 9. Current Sense Input Threshold

versus Error Amp Output Voltage

VCC = 15 V

≤ 0.1 W

R

L

-12 TA = 125°C

-16

-20

, REFERENCE VOLTAGE CHANGE (mV)

ref

V

Δ

-24 0

20 40 60 80 100 120

I

ref

Figure 10. Reference Voltage Change

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

Δ

Figure 12. Reference Load Regulation Figure 13. Reference Line Regulation

TA = -55°C

TA = 25°C

, REFERENCE SOURCE CURRENT (mA)

versus Source Current

VCC = 15 V I

= 1.0 mA to 20 mA

O

TA = 25°C

2.0 ms/DIV 2.0 ms/DIV

70

, REFERENCE SHORT CIRCUIT CURRENT (mA)

50

-55

SC

I

-25 0 25 50 75 100 125

Figure 11. Reference Short Circuit Current

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

Δ

, AMBIENT TEMPERATURE (°C)

T

A

versus Temperature

VCC = 12 V to 25 T

= 25°C

A

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6

UC3842B, UC3843B, UC2842B, UC2843B

0

-1.0

-2.0

3.0

2.0

1.0

, OUTPUT SATURATION VOLTAGE (V)

sat

V

0

, OUTPUT VOLTAGE

O

V, SUPPLY CURRENT

CC

I

V

CC

TA = 25°C

Source Saturation (Load to Ground)

VCC = 15 V

80 ms Pulsed Load

120 Hz Rate

TA = -55°C

TA = 25°C

Sink Saturation (Load to V

CC

GND

)

200 400 600

, OUTPUT LOAD CURRENT (mA)

I

O

Figure 14. Output Saturation Voltage

versus Load Current

VCC = 30 V C

= 15 pF

L

T

= 25°C

A

100 ns/DIV

8000

100 mA/DIV 20 V/DIV

90%

10%

25

20

15

10

, SUPPLY CURRENT (mA)

CC

I

VCC = 15 V C

= 1.0 nF

L

T

= 25°C

A

50 ns/DIV

Figure 15. Output Waveform

RT = 10 k C

= 3.3 nF

T

V

= 0 V

5

0

UCX843B

UCX842B

10 20 30 40

V

, SUPPLY VOLTAGE (V)

CC

FB

I

Sense

T

= 25°C

A

= 0 V

Figure 16. Output Cross Conduction

Figure 17. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

8−Pin 14−Pin Function Description

1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.

2 3 Voltage

Feedback

3 5 Current

Sense

4 7 RT/C

T

5 GND This pin is the combined control circuitry and power ground.

6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced

7 12 V

8 14 V

CC

ref

8 Power

Ground

11 V

C

9 GND This pin is the control circuitry ground return and is connected back to the power source ground.

2,4,6,1

NC No connection. These pins are not internally connected.

3

This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.

A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.

The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor

to V

R

and capacitor CT to ground. Operation to 500 kHz is possible.

T

ref

and sunk by this pin.

This pin is the positive supply of the control IC.

This is the reference output. It provides charging current for capacitor CT through resistor RT.

This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry.

The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.

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7

UC3842B, UC3843B, UC2842B, UC2843B

OPERATING DESCRIPTION

The UC3842B, UC3843B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost−effective solution with minimal external components. A representative block diagram is shown in Figure 19.

Oscillator

The oscillator frequency is programmed by the values chosen for the timing components R noted that the value of R

and CT. It must also be

T

uniquely determines the

T

maximum duty ratio of UC384xx. The oscillator configuration depicting the connection of the timing components to the R Figure 18. Capacitor C through resistor R

pin of the controller is shown in

T/CT

gets charged from the V

T

to its peak threshold V

T

source,

ref

RT/CT(peak)

typically 2.8 V. Upon reaching this peak threshold volage, an internal 8.3 mA current source, I voltage across C across C

T

typically 1.2 V, I charge up again from V resulting waveform on the R

begins to decrease. Once the voltage

T

reaches its valley threshold, V

turns off. This allows capacitor C

dischg

. This entire cycle repeats, and the

ref

T/CT

, is enabled and the

dischg

RT/CT(valley)

T

pin has a sawtooth shape.

Typical waveforms are shown in Figure 20.

The oscillator thresholds are temperature compensated to within ±6%

at 50 kHz. Considering the general industry

trend of operating switching controllers at higher frequencies, the UC384xx is guaranteed to operate within ±10% at 250 kHz

. These internal circuit refinements

minimize variations of oscillator frequency and maximum duty ratio.

The charging and discharging times of the timing capacitor CT are calculated using Equations 1 and 2. These equations do not take into account the propagation delays of the internal comparator. Hence, at higher frequencies, the calculated value of the oscillator frequency differs from the actual value.

t

RTńCT(chg)

t

RTńCT(dischg)

+ RTCTln

ǒ

RTI

The maximum duty ratio, D

D

+

max

t

RTńCT(chg)

V

RTńCT(valley)

ǒ

V

RTńCT(peak)

RTI

dischg

max

t

RTńCT(chg)

* V

ref

Ǔ

* V

ref

) V

RTńCT(peak)

RTńCT(valley)

* V

ref

is given by Equation 3.

) t

RTńCT(dischg)

(eq. 1)

Ǔ

ref

(eq. 2)

(eq. 3)

Substituting Equations 1 and 2 into Equation 3, and after algebraic simplification, we obtain

V

RTńCT(valley)

ǒ

ln

V

D

+

max

V

ǒ

ln

V

RTńCT(valley)

RTńCT(peak)

*V

ref

RTńCT(peak)

@

RTI

dischg

*V

ref

*V

ref

)V

RTńCT(peak)

)V

RTńCT(valley)

Ǔ

*V

ref

Ǔ

*V

ref

(eq. 4)

Clearly, the maximum duty ratio is determined by the timing resistor R achieve a desired maximum duty ratio. Once R selected, C

. Therefore, RT is chosen such as to

T

has been

T

can now be chosen to obtain the desired

T

switching frequency as per Equation 5.

f +

RTCTln

V

RTńCT(valley)

ǒ

V

RTńCT(peak)

,

*V

1

RTI

ref

@

RTI

ref

dischg

RTńCT(peak)

)V

RTńCT(valley)

)V

dischg

*V

ref

Ǔ

ref

(eq. 5)

Figure 2 shows the frequency and maximum duty ratio variation taken to ensure that the absolute minimum value of R should not be less than 542 W. However, considering a 10%

,

to

tolerance for the timing resistor, the nearest available

versus R

for given values of CT. Care should be

T

standard resistor of 680 W is the absolute minimum that can be used to guarantee normal oscillator operation. If a timing resistor smaller than this value is used, then the charging current through the R

, CT path will exceed the pulldown

T

(discharge) current and the oscillator will get permanently locked/latched to an undefined state.

In many noise-sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 22. For reliable synchronization, the free-running oscillator frequency should be set about 10% less than the clock frequency. A method for multi-unit synchronization is shown in Figure 23. By tailoring the clock waveform, accurate Output duty ratio clamping can be achieved.

V

ref

R

T

RT/C

T

I

Enable

dischg

C

Figure 18. Oscillator Configuration

2.8 V

1.2 V

T

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8

UC3842B, UC3843B, UC2842B, UC2843B

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 90 dB, and a unity gain bandwidth of

1.0 MHz with 57 degrees of phase margin (Figure 8). The non−inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 33). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the non−inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when pin 1 is at its lowest state (V

OL

This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 25, 26). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (V

) to reach the

OH

comparator’s 1.0 V clamp level:

R

f(min)

Current Sense Comparator and PWM Latch

3.0 (1.0 V) + 1.4 V

≈

0.5 mA

= 8800 W

The UC3842B, UC3843B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse

appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground−referenced sense resistor R

in series with the

S

source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where:

− 1.4 V

V

Ipk =

(Pin 1)

3 R

S

Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:

).

I

pk(max)

1.0 V

=

R

S

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of R

to a reasonable

S

level. A simple method to adjust this voltage is shown in Figure 24. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I

pk(max)

clamp

voltage.

A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 28).

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9

UC3842B, UC3843B, UC2842B, UC2843B

V

ref

8(14)

R

T

2.5V

R

Internal

Bias

R

3.6V

Oscillator

4(7)

C

T

Voltage

+

1.0mA

2R

Feedback

Input

Output/

Compensation

2(3)

1(1)

Error

Amplifier

GND

R

1.0V

5(9)

Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SOIC-14 package.

Reference

Regulator

+

V

ref

UVLO

Current Sense

Comparator

S

R

V

CC

UVLO

Q

PWM Latch

V

CC

V

CC

7(12)

V

in

36V

(See

+

Text)

-

V

C

7(11)

Output

Q1

6(10)

Power Ground

5(8)

Current Sense Input

3(5)

R

S

= Sink Only Positive True Logic

Capacitor C

T

Latch “Set" Input

Output/ Compensation

Current Sense Input

Latch “Reset" Input

Output

Figure 19. Representative Block Diagram

Large RT/Small C

T

Figure 20. Timing Diagram

Small RT/Large C

T

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10

UC3842B, UC3843B, UC2842B, UC2843B

Undervoltage Lockout

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (V

) and the reference output (V

CC

ref

) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The V

comparator

CC

upper and lower thresholds are 16 V/10 V for the UCX842B, and 8.4 V/7.6 V for the UCX843B. The V

comparator

ref

upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX842B makes it ideally suited in off−line converter applications where efficient bootstrap startup techniques are required (Figure 35). The UCX843B is intended for lower voltage DC−to−DC converter applications. A 36 V Zener is connected as a shunt regulator from V

to ground. Its

CC

purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage (V

) for the UCX842B is 11 V and 8.2 V for the

CC

UCX843B.

These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull−down resistor.

The SOIC−14 surface mount package provides separate pins for V

(output supply) and Power Ground. Proper

C

implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I

pk(max)

clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of V

. A Zener clamp is typically connected

CC

to this input when driving power MOSFETs in systems where V

is greater than 20 V. Figure 27 shows proper

CC

power and control ground connections in a current−sensing power MOSFET application.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at T

= 25°C on the UC284XB, and ±2.0% on the

J

UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short− circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on

wire−wrap or plug−in prototype boards. High frequency

circuit layout techniques are imperative to prevent pulse−width jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low−current signal and high−current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to V and V

may be required depending upon circuit layout.

ref

CC

, VC,

This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise−generating components.

Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulator’s closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 21A shows the phenomenon graphically. At t

, switch

0

conduction begins, causing the inductor current to rise at a slope of m divided by the inductance. At t

. This slope is a function of the input voltage

1

, the Current Sense Input

1

reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m

, until the next oscillator cycle. The unstable

2

condition can be shown if a perturbation is added to the control voltage, resulting in a small DI (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn−on (t by DI + DI m

) decreases to (DI + DI m2/m1) (m2/m1). This perturbation

(t

3

is multiplied by m

. The minimum current at the next cycle

2/m1

on each succeeding cycle, alternately

2/m1

) is increased

2

increasing and decreasing the inductor current at switch turn−on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m

is greater than 1, the converter

2/m1

will be unstable. Figure 21B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the DI perturbation will decrease to zero on succeeding cycles. This compensating ramp (m have a slope equal to or slightly greater than m stability. With m

/2 slope compensation, the average

2

) must

3

/2 for

2

inductor current follows the control voltage, yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 34).

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11

UC3842B, UC3843B, UC2842B, UC2843B

Control Voltage

Inductor Current

Control Voltage

DI

(A)

Dl ) Dl

m

2

m

2

m

1

Dl ) Dl

m

2



m

1

m

1

Oscillator Period

t

0

t

1

2

(B)

m

3

m

1

m

2

Oscillator Period

t

4

t

5

Figure 21. Continuous Current Waveforms

t

3

Inductor

Current

V

ref

8(14)

R

T

External

Sync Input

t

6

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C

to go more than 300 mV below ground.

T

C

0.01

4(7)

T

2(3)

47

1(1)

R

Bias

R

Osc

+

2R

EA

R

5(9)

Figure 22. External Clock Synchronization

3

7

R

B

RA)2R

8(14)

4(7)

2(3)

1(1)

B

To Additional

UCX84XBs

R

A

8 4

R

B

6

5

2

C

1.44

f +

(RA )2RB)C

5.0k

R

5.0k

1

Q

S

MC1455

D

(max)

+

Figure 23. External Duty Cycle Clamp and

Multi−Unit Synchronization

V

CC

7(12)

8(14)

R

Bias

R

Osc

+

2R

EA

R

5(9)

4(7)

R

2

2(3)

1(1)

R

1

V

Clamp

R

Bias

R

Osc

+

1.0 mA

) 1

2R

+ 0.33x10

Ǔ

EA

1.67

≈

R

2

ǒ

R

1

5.0V Ref

+

-

Clamp

V

≤ 1.0 V

Clamp

R

S

7(11)

6(10)

5(8)

3(5)

+

-

V

Clamp

R

1.0V

5(9)

-3

ǒ

R1) R

R1R

2

Ǔ

2

S

Q

R

Comp/Latch

Where: 0 ≤ V

I

pk(max)

 [

V

in

Q1

R

S

Figure 24. Adjustable Reduction of Clamp Level

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12

UC3842B, UC3843B, UC2842B, UC2843B

V

CC

7(12)

V

R

Where: 0 ≤ V

ƫ

+

-

Clamp

1.0V

5(9)

C

R1)R

5.0V Ref

R1R

Clamp

2

S

Q

R

Comp/Latch

≤ 1.0 V

I

pk(max)

 [

+

-

7(11)

6(10)

5(8)

3(5)

V

Clamp

R

S

8(14)

4(7)

2(3)

1.0M

1(1)

C

t

Soft-Start

R

+

EA

≈ 3600C in mF

Osc

Bias

1.0mA

2R

R

5.0V Ref

+

-

S

Q

1.0V

R

5(9)

C

4(7)

2(3)

R

2

1(1)

R

1

t

Soft

MPSA63

V

Clamp

Start

R

EA

[

+*In

Bias

Osc

+

1.0 mA

2R

1.67

R

2

ǒ

Ǔ

) 1

R

1

V

C

ƪ

1 *

3V

Clamp

V

in

Q1

R

S

Figure 25. Soft−Start Circuit Figure 26. Adjustable Buffered Reduction of

Clamp Level with Soft−Start

V

CC

(12)

5.0V Ref

+

-

S

R

Comp/Latch

Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over-current conditions, a reduction of the I

pk(max)

+

-

(11)

(10)

Q

Control Circuitry Ground:

To Pin (9)

clamp level must be implemented. Refer to Figures 24 and 26.

(8)

(5)

G

R

S

1/4 W

V

in

V

Pin 5

If: SENSEFET = MTP10N10M R

= 200

S

Then : V

D

SENSEFET

S

K

M

Power Ground: To Input Source

Return

Figure 27. Current Sensing Power MOSFET

[

Pin5

RSIpkr

r

DM(on)

 [ 0.075I

DS(on)

) R

pk

V

7(12)

+

-

CC

7(11)

6(10)

5(8)

3(5)

S

5.0V Ref

+

-

S

Q

R

Comp/Latch

The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform.

V

in

Q1

R

C

R

S

Figure 28. Current Waveform Spike Suppression

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13

UC3842B, UC3843B, UC2842B, UC2843B

V

CC

7(12)

5.0V Ref

+

-

S

Q

R

Comp/Latch

Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit.

+

-

7(11)

R

6(10)

5(8)

3(5)

Figure 29. MOSFET Parasitic Oscillations

V

CC

7(12)

5.0V Ref

+

-

S

Q

R

Comp/Latch

+

-

7(11)

6(10)

5(8)

3(5)

C

Isolation

Boundary

R

Q1

N

S

V

in

g

Q1

R

S

V

in

VGS Waveforms

+

0

50% DC 25% DC

V

(Pin1)

Ipk +

3R

N

P

* 1.4

S

I

B

+

0

-

The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1.

Base Charge Removal

6(10)

5(8)

3(5)

V

in

C1

Q1

R

S

Figure 30. Bipolar Transistor Drive

8(14)

4(7)

+

0

-

N

S

ǒ

Ǔ



N

p

MCR

101

The MCR101 SCR must be selected for a holding of < 0.5 mA @ T transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.

3905

2(3)

1(1)

2N

3903

R

Bias

R

Osc

+

1.0 mA 2R

EA

A(min)

R

5(9)

. The simple two

Figure 31. Isolated MOSFET Drive Figure 32. Latched Shutdown

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14

UC3842B, UC3843B, UC2842B, UC2843B

From V

O

R

i

C

f

R

d

R

≥ 8.8 k

f

Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current.

From V

O

R

p

R

i

C

p

Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current.

C

f

R

d

Figure 33. Error Amplifier Compensation

1(1)

2(3)

2.5V

R

f

2.5V

R

f

+

1.0mA 2R

EA

+

EA

1.0mA

R

5(9)

2R

R

5(9)

From V

O

MPS3904

R

Slope

R

i

R

d

8(14) R

T

R

Bias

R

EA

- 3.0m

+

Osc

1.0mA 2R

4(7)

C

T

2(3)

C

f

R

f

1(1)

5.0V Ref

+

-

-m

R

1.0V

S

Q

R

Comp/Latch

m

5(9)

The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.

Figure 34. Slope Compensation

V

CC

7(12)

V

in

36V

+

-

7(11)

6(10)

5(8)

3(5)

R

S

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15

UC3842B, UC3843B, UC2842B, UC2843B

18k

4.7k

100

pF

0.01

4700pF

150k

10k

115 Vac

8(14)

4(7)

2(3)

1(1)

4.7

W

MDA

202

R

Bias

R

Osc

+

250

5.0V Ref

+

-

+

S

Q

EA

5(9)

R

Comp/Latch

Figure 35. 27 W Off−Line Flyback Regulator

MBR1635

4.7k

56k

1N4935 1N4935

7(12)

+

-

7(11)

6(10)

5(8)

3(5)

68

++

100

1N4937

22

1N5819

1.0k

470pF

3300 pF

47

MTP 4N50

T1

2200

MUR110

1000

MUR110

680pF

2.7k

L1

- 15 mH at 5.0 A, Coilcraft Z7156

L2, L3

- 25 mH at 5.0 A, Coilcraft Z7157

Primary: 45 Turns #26 AWG

T1 -

0.5

Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound

L1

++

1000

L2

++

L3

1N4937

5.0V/4.0A

5.0V RTN

12V/0.3A

10

±12V RTN

10

-12V/0.3A

Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10" for a primary inductance of 1.0 mH

Test Conditions Results

Line Regulation: 5.0 V

±12 V

Load Regulation: 5.0 V

±12 V

Output Ripple: 5.0 V

±12 V

Vin = 95 to 130 Vac

D = 50 mV or ± 0.5% D = 24 mV or ± 0.1%

Vin = 115 Vac,

= 1.0 A to 4.0 A

I

out

= 115 Vac,

V

in

= 100 mA to 300 mA

I

out

D = 300 mV or ± 3.0%

D = 60 mV or ± 0.25%

Vin = 115 Vac 40 mV

80 mV

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents, unless otherwise noted

pp

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16

UC3842B, UC3843B, UC2842B, UC2843B

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping

UC2842BDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC2842BD1G

UC2842BD1R2G

T

= −25° to +85°C

A

SOIC−8

(Pb−Free)

SOIC−8

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC2842BNG

UC3842BNG

UC3842BDG

PDIP−8

(Pb−Free)

PDIP−8

(Pb−Free)

SOIC−14

1000 Units/Rail

55 Units/Rail

(Pb−Free)

UC3842BDR2G

UC3842BD1G

T

= 0° to +70°C

A

SOIC−14

(Pb−Free)

SOIC−8

2500 Tape & Reel

98 Units/Rail

(Pb−Free)

UC3842BD1R2G

UC3842BVDR2G

UC3842BVD1G

UC3842BVD1R2G

T

= −40° to +105°C

A

SOIC−8

(Pb−Free)

SOIC−14

(Pb−Free)

SOIC−8

(Pb−Free)

SOIC−8

2500 Tape & Reel

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC2843BDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC2843BDR2G

UC2843BD1G

T

= −25° to +85°C

A

SOIC−14

(Pb−Free)

SOIC−8

2500 Tape & Reel

98 Units/Rail

(Pb−Free)

UC2843BD1R2G

UC2843BNG

T

= −25° to +85°C

A

SOIC−8

(Pb−Free)

PDIP−8

2500 Tape & Reel

1000 Units/Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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17

UC3842B, UC3843B, UC2842B, UC2843B

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping

UC3843BDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC3843BDR2G SOIC−14

2500 Tape & Reel

(Pb−Free)

UC3843BD1G SOIC−8

98 Units/Rail

(Pb−Free)

T

= 0° to +70°C

UC3843BD1R2G SOIC−8

UC3843BDR2G SOIC−14

UC3843BNG PDIP−8

A

(Pb−Free)

2500 Tape & Reel

1000 Units/Rail

(Pb−Free)

UC3843BVDG

SOIC−14

55 Units/Rail

(Pb−Free)

UC3843BVDR2G SOIC−14

2500 Tape & Reel

(Pb−Free)

UC3843BVD1G SOIC−8

T

= −40° to +105°C

A

(Pb−Free)

UC3843BVD1R2G SOIC−8

98 Units/Rail

2500 Tape & Reel

(Pb−Free)

UC3843BVNG PDIP−8

1000 Units/Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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18

UC3842B, UC3843B, UC2842B, UC2843B

MARKING DIAGRAMS

PDIP−8

N SUFFIX

CASE 626

14

1

8

UC384xBN

AWL

YYWWG

1

UC384xBDG

AWLYWW

8

UC3843BVN

1

CASE 751A

14

UC384xBVDG

1

D1 SUFFIX

AWL

YYWWG

SOIC−14

D SUFFIX

AWLYWW

SOIC−8

CASE 751

8

UC284xBN

AWL

YYWWG

1

14

UC284xBDG

AWLYWW

1

8

384xB ALYW

G

1

8

384xB

ALYWV

G

1

x = 2 or 3 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package

8

284xB ALYW

G

1

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19

NOTE 2

−T−

SEATING PLANE

H

UC3842B, UC3843B, UC2842B, UC2843B

58

−B−

14

F

−A−

C

N

D

G

0.13 (0.005) B

PACKAGE DIMENSIONS

PDIP−8

N SUFFIX

CASE 626−05

ISSUE L

L

J

K

M

A

T

M

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070

G 2.54 BSC 0.100 BSC

H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC

M --- 10 --- 10

N 0.76 1.01 0.030 0.040

INCHESMILLIMETERS

__

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20

−Y−

−Z−

UC3842B, UC3843B, UC2842B, UC2843B

PACKAGE DIMENSIONS

SOIC−8

D1 SUFFIX

CASE 751−07

ISSUE AJ

−X−

B

H

A

58

1

4

G

D

0.25 (0.010) Z

M

S

Y

0.25 (0.010)

C

SXS

SEATING PLANE

0.10 (0.004)

M

Y

K

N

X 45

_

M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

http://onsemi.com

21

−T−

SEATING PLANE

UC3842B, UC3843B, UC2842B, UC2843B

PACKAGE DIMENSIONS

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE J

−A−

14

1

G

D 14 PL

0.25 (0.010) A

8

−B−

P

7 PL

M

0.25 (0.010) B

7

R

C

X 45

K

M

S

B

T

S

M

_

M

J

SOLDERING FOOTPRINT

7X

7.04

1

14X

0.58

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL

F

CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

__ __

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

14X

1.52

INCHESMILLIMETERS

1.27

PITCH

DIMENSIONS: MILLIMETERS

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UC3842B/D