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UC1727
UC2727
UC3727
查询UC1727供应商
Isolated High Side IGBT Driver
FEATURES DESCRIPTION
• Receives Power and Signal from Single
Isolation Transformer
• Generates Split Rail for 4A Peak Bipolar
Gate Drive
• 16V High Level Gate Drive
• Low Level Gate Drive more Negative
than -5V
• Undervoltage Lockout
• Desaturation Detection and Fault
Processing
• Separate Output Enable Input
The UC1727 and its companion chip, the UC1726, provide all the
necessary features to drive an isolated IGBT transistor from a TTL input signal. A unique modulation scheme is used to transmit both
power and signal across an isolation boundary with a minimum of external components.
Protection features include under voltage lockout and desaturation
detection. High level gate drive signals are typically 16V. Intermediate
high drive level s can be programmed for various periods of time to
limit surge current at turn on and in the event of desaturation due to a
short circuit.
The chip generates a bipolar supply so that the gate can be driven to
a negative vol tage insuring the I GBT remains off in the presence of
high common mode slew rates.
• Programmable Stepped Gate Drive for
Soft Turn On
• Programmable Stepped Gate Drive for
Soft Fault
BLOCK DIAGRA M
Uses include isolated off-line full bridge and half bridge drives for motors, switches, and any other load requiring full electrical isolation.
12/94
UDG-94005-2
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ABSOLUTE MAXI MUM RATING S
Supply voltage (V CC - VEE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Power Inpu ts (|A - B|). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45V
Analog Input Voltage (
Analog Input Voltage ( D
Analog Input Curren t (D
ENBL, CLAMP). . . . . . . . . . . . . . . . . . -0.3 To Vcc+0.3
SAT+, DSAT-) . . . . . . . . . . . . . . . . VEE-0.3 to VCC+0.3
SAT+, DSAT-) . . . . . . . . . . . . . . . . . . . . . . -10 to 10mA
Output Current, (OUT)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A
FRPLY Output Curr ent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Note: All voltages ar e w ith respe ct to CO M. Curre nt s are pos itive int o the
specified terminal.
CONNECTION DIAGRAMS
DIL-18 (Top View)
J Package
DIL-20 (Top View)
N Package
UC1727
UC2727
UC3727
SOIC-28 (Top View)
DWP Package
PLCC-28 (Top View)
QP Package
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C 1
V
EE 2
N/C 3-4
COM 5
CLAMP 6
B7
A8
V
CC 9
PV
CC 10
OUT 11
PV
EE 12-18
D
SAT+ 19
D
SAT- 20
ENBL 21
NC 22
TRC 23
FRC 24
FRPLY 25
N/C 26
N/C 27
N/C 28
LCC-28 (Top View )
LP Package
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C 1
V
EE 2
N/C 3-4
COM 5
CLAMP 6
B7
A8
V
CC 9
PV
CC 10
OUT 11
N/C 12-13
PV
EE 14
N/C 15-18
D
SAT+ 19
D
SAT- 20
ENBL 21
NC 22
TRC 23
FRC 24
FRPLY 25
N/C 26-28
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Unless otherw ise stat ed, these sp ecif icat io ns apply for TA = −55 °C to 125°C for the
UC1727, TA = −40°C to 85°C for the UC2727, TA = 0°C to 70° C for the UC3727,
R(TRC) = 54.9k, C(TRC) = 180pF , R(FRC) = 309K, C(FRC) = 200pF, VCC - VEE =
25V, CLAMP = 9V, TA = TJ, and all voltage s are mea sur ed with respect to COM.
See Application Note U-143A "Ne w Chi p Pair Pro vides Iso lated Driv e for High Volta ge IGBTs"
PIN DESCRIP TI ONS
A, B: Signal and power input pins. Connect these pins to
the secondary of the transformer driven by UC1726.
CLAMP: Analog programming pin for intermediate drive
level to be used at turn on or in response to a desaturation event. Requires a bypass capacitor to COM.
FRPLY: Fault Reply pin. Open coll ector output. Normally
connected to V
EE. When desaturation is detected, the pin
opens.
OUT: Gate drive output. Connect to gate of IGBT with a
series damping resistor greater than 3 ohms.
UC1727
UC2727
UC3727
COM: Self generated common for bipolar supply. This
pin will be 16.5V below PV
D
SA T + , DSAT-: Inputs to the desaturation comparator. De-
saturation is detected when D
CC.
SA T+ is greater than D SAT-.
ENBL: Negative true enable input. Tie to VCC to disable
the chip. Connect to COM to enable the chip. If the
ENBL
pin is used as the primary input to the chip, connect B to
V
CC and A to V EE.
FRC: Fault Resistor and Capacitor. Programs the duration that OUT will be held at CLAMP potential during a desaturation event before it is driven fully low. Also sets the
period of time tha t OUT will be held low before allowing it
to be driven high again.
TRC: Timing Resistor and Capacitor. Programs the duration that OUT will be held at CLAMP potential and the period of time the desaturation comparator will be ignored
during the rising edge.
V
CC: Positive supply voltag e. Bypass to COM with a low
ESL/ESR 1µF capacitor.
EE: Negative supply voltage. Bypass to COM with a low
V
ESL/ESR 1µF capacitor.
EE: Output driver negative supply. Connect to VEE
PV
with a 3.3 ohm resistor and bypass to COM with a low
ESL/ESR 1µF capacitor.
CC: Output driver positive supply. Connect to VCC with
PV
a 3.3 ohm resistor and bypass to COM with a low
ESL/ESR 1µF capacitor.
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Power Input Receivers
Forward Diode Dro p I
V
CC Regulator
V
CC 25 ≤ (VCC - VEE) ≤ 36V,I(COM) ≤ 15mA 15.5 16.5 17.5 V
Hysteresi s Compar at or
Input Open Circuit Voltag e (Measured with respe ct to V
Input Impedance 100 kΩ
Hysteresis 44 47 50 V
Enable Input
High Level Input Voltage 12 V
Low Level Input Volta ge 5V
Input Bias Cur rent
Output Driver
Saturation to V
Saturation to V
Saturation to V
Saturation to V
CC I(OU T ) = -20 mA 1.7 2.3 V
CC I(OU T ) = -50 0m A 2 2.5 V
EE I(OU T) = 20mA 2 3 V
EE I(OU T) = 500mA 2.4 3.6 V
F = 50mA 0.5 0.65 V
I
F = 500mA 1.2 2 V
EE)12V
ENBL = COM −460 −900 µA
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UC1727
UC2727
UC3727
ELECTRICAL CHARACTERISTICS:
Unless other wise stat ed, these specif icat ions ap ply fo r T
UC1727, T
A = −40°C to 85°C for the UC2727, T A = 0 ° C to 70°C for the UC3727,
R(TRC) = 54.9k, C(TRC) = 180pF, R(FRC) = 309K, C(FRC) = 200pF, V
25V, CLAMP = 9V, T
A = TJ, and a ll volta g es ar e me asur ed with respect to CO M.
A = −55°C to 125°C for the
CC - VEE =
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Output Driver (cont.)
Turn on Clamp Voltage I(OUT) = -100mA 7 9 11 V
Fault Clamp Voltage |I(OUT)| = 100mA 8 10 12.5 V
UVLO Saturat ion to V
Rise and Fall Times Cl = 1n, CLAMP = V
EE I(OU T) = 20mA,VCC no connection 2 3 V
CC, ROUT = 3Ω (Note 1) 75 150 ns
Turn On Sequence Timer
Clamped Driver Time (Note 1) 0.4 1 1.7 µs
Blanking Time (Note 1) 3 5 7 µs
Fault Manager
Clamped Driver Time (Note 1) 0.4 1 1.7 µs
Fault Lock O ff Time (Note 1) 15 25 35 µs
FRPLY Saturation I(FRPLY) = 10mA 1.8 3 V
FRPLY Leakage FRPLY = V
CC 010 µA
Desaturation Dete ctio n Comp ara tor
Input Offs et Vo lta ge (|vio|) V
CM = VEE+2, VCM = VCC-2 0 20 mV
Input Bias Cur rent −1.5 10 µA
Delay to Output C(FRC) = 0 (Note 1) 150 ns
Undervoltage Lock Out
V
CC Threshold 14 15.5 17 V
V
CC Hysteresis 0.35 V
V
EE Threshold −4.5 −5.5 −6.5 V
V
EE Hysteresis 0.5 1 1.5 V
Thermal Shutdown
Thres ho l d Not tested 175 °C
Hysteresis Not tested 45 °C
Total Standby Current
I(V
CC) 24 30 mA
Note 1: Guaranteed by design, but not 100% test ed in pr oduc tion .
APPLICATION INF ORMATI ON
Figure 1 shows the rectification and detection scheme
used in the UC1727 to derive both power and signal information from the input waveform. V
peak detecting the input signal via the internal bridge rectifier and stori ng it on externa l ca paci tor s. COM is generated by an internal amplifier that maintains PV
16.5V.
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting (or
resetting) the comparator only if the input signal exceeds
0.95VCC-VEE. In some cases it may be necessary to
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis comparator as shown in Figure 3.
CC-VEE is generated by
CC-COM =
Figure 1. Input Stage & Bipolar Supply
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APPLICATION INF ORMATI ON (cont.)
UC1727
UC2727
UC3727
Figure 2. Input Waveform
Figure 3. Output Pulsing Caused By Transform er R inging
GATE DRIVE WAVEFORM
The rising edge of OUT can be programmed for a two
step sequence as shown in Figure 4. The plateau voltage
is programmed by a resistive divider from V
applied at CLAMP. CLAMP must be bypassed to COM.
The plateau voltage is approximately OUT = CLAM P. The
plateau time is set by a resistor from TRC to V
capacitor to COM as:
R
−7.6
k
Tp
= RC ln
TRC also programs a blanking time during which the chip
ignores the desaturation comparator. The blanking time
is:
Tb = Tp + 0.4RC.
R
−12.4
.
k
CC to COM
CC and a
Figure 4. Rising Edge Wavefor m
Figure 5. Transient Desaturation Response
In the event that desaturation is detected outside the
blanking interval, OUT will be driven back to the CLAMP
plateau for a fault time set by a resistor from FRC to V
and a capacitor to COM as:
R
−7.6
k
Tf
= RC ln
If the event is transient, OUT will return high at the end of
Tf as shown in Figure 5. During Tf, FRPLY is open. After
Tf, FRPLY is connected to COM.
Desaturation shown in Fig ure 6 that persists longer than
Tf will cau se OUT to be driven low. The chip will not accept a command to drive OUT high for a delay period of
Td = 0.4RC
FRPLY will be open during this entire period.
R
−12.4
.
k
CC
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Figure 6. Desaturation Response
UC1727
UC2727
UC3727
EXTERNAL BIPOLAR SUPPLIE S
If it is desired to drive an emitter grounded IGBT from external supplies, the configuration in Figure 8 should be
used. COM shoul d never be connected to ground. V
must be ≥ 12V and VCC-VEE must be ≥ 23.5V.
CC
ENABLE
ENBL provides an alte rnate mea ns of control li ng the output. If
ENBL is used as the primary input, B must be connected to V
output of an optoisolator from
Figure 7. If
CC and A to VEE. ENBL can be driven by the
ENBL to COM as shown in
ENBL is not used, it should be connected to
COM.
Figure 8. Using External Supplies
Figure 7. Using ENBL as Primary Input
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • • MERRIMACK, NH 03054
TEL. (603) 424-2410 •• FAX (603) 424-3460
Figure 9. Input t o O ut put Delay
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