Datasheet UC3845N, UC3845DR2, UC3845D, UC3844N, UC3844DR2 Datasheet (Motorola)

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The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for Off–Line and
dc–to–dc converter applications offering the designer a cost effective
solution with minimal external components. These integrated circuits feature
an oscillator, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole output
ideally suited for driving a power MOSFET.

Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
a latch for single pulse metering, and a flip–flop which blanks the output off
every other oscillator cycle, allowing output deadtimes to be programmed for
50% to 70%.

These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.

The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX845 is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).

• Current Mode Operation to 500 kHz Output Switching Frequency

• Output Deadtime Adjustable from 50% to 70%

• Automatic Feed Forward Compensation

• Latching PWM for Cycle–By–Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• High Current Totem Pole Output

• Input Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

• Direct Interface with Motorola SENSEFET Products

Simplified Block Diagram

V

7(12)

CC

8(14)

RTC

4(7)

Voltage

Feedback

2(3)

1(1)
Output
Comp.

V

ref

R

V

R

T

Oscillator

+
–

Error

Amplifier

Pin numbers in parenthesis are for the D suffix SO–14 package.

ref

Undervoltage

Lockout

Gnd 5(9)

5.0V

Reference

Latching

Flip

Flop

&

PWM

V

CC

Undervoltage

Lockout

V

C

7(11)

Output

6(10)

PWR GND

5(8)

Current
Sense

3(5)

Order this document by UC3844/D

 
 

HIGH PERFORMANCE

CURRENT MODE

CONTROLLERS

N SUFFIX

PLASTIC PACKAGE

CASE 626

D SUFFIX

PLASTIC PACKAGE

CASE 751A

(SO–14)

PIN CONNECTIONS

Compensation

Voltage Feedback

Current Sense

Compensation

Voltage Feedback

Current Sense

ORDERING INFORMATION

Device

UC3844D
UC3845D
UC3844N
UC3845N
UC2844D
UC2845D
UC2844N
UC2845N

1
2
3

45

RT/C

T

(T op View)

1
2

NC

3
4

NC

5
6

NC

RT/C

7

T

(T op V iew)

Operating

Temperature Range

TA = 0° to +70°C

TA = – 25° to +85°C

8

1

14

8

V

ref

7

V

CC

6

Output
Gnd

14

V

ref

13

NC

12

V

CC

11

V

C

10

Output

9

Gnd
Power Ground

8

1

Package

SO–14
SO–14
Plastic
Plastic
SO–14
SO–14
Plastic
Plastic

MOTOROLA ANALOG IC DEVICE DATA

 Motorola, Inc. 1996 Rev 1

1

UC3844, 45 UC2844, 45

MAXIMUM RATINGS

Rating Symbol Value Unit

Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) I

O

Output Energy (Capacitive Load per Cycle) W 5.0 µJ
Current Sense and Voltage Feedback Inputs V
Error Amp Output Sink Current I

in

O

Power Dissipation and Thermal Characteristics

D Suffix, Plastic Package, Case 751A

Maximum Power Dissipation @ TA = 25°C
Thermal Resistance Junction–to–Air

N Suffix, Plastic Package, Case 626

Maximum Power Dissipation @ TA = 25°C

Thermal Resistance Junction–to–Air
Operating Junction Temperature T
Operating Ambient Temperature

UC3844, UC3845

P

D

R

θJA

P

D

R

θJA

J

T

A

UC2844, UC2845

Storage Temperature Range T

stg

1.0 A

– 0.3 to + 5.5 V

10 mA

862
145

1.25
100

+ 150 °C

0 to + 70

– 25 to + 85

– 65 to + 150 °C

mW

°C/W

W

°C/W

°C

ELECTRICAL CHARACTERISTICS (V

= 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = T

CC

low

to T

high

[Note 3],

unless otherwise noted.)

UC284X UC384X

Characteristics Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) V
Line Regulation (VCC = 12 V to 25 V) Reg
Load Regulation (IO = 1.0 mA to 20 mA) Reg
T emperature Stability T
Total Output V ariation over Line, Load, Temperature V
Output Noise Voltage (f = 10 Hz to kHz, TJ = 25°C) V

ref

line
load
S

ref

n

4.95 5.0 5.05 4.9 5.0 5.1 V
– 2.0 20 – 2.0 20 mV
– 3.0 25 – 3.0 25 mV
– 0.2 – – 0.2 – mV/°C

4.9 – 5.1 4.82 – 5.18 V
– 50 – – 50 – µV

Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – – 5.0 – mV
Output Short Circuit Current I

SC

– 30 – 85 – 180 – 30 – 85 – 180 mA

OSCILLATOR SECTION

Frequency

TJ = 25°C
TA = T

low

to T

high

Frequency Change with Voltage (VCC = 12 V to 25 V) ∆f
Frequency Change with Temperature

TA = T

low

to T

high

Oscillator Voltage Swing (Peak–to–Peak) V
Discharge Current (V

NOTES: 1. Maximum Package power dissipation limits must be observed.

2.Adjust VCC above the Startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
T

= –20°C for UC3844, UC3845 T

low

T

= –25°C for UC2844, UC2845 T

low

= 2.0 V, TJ = 25°C) I

osc

f

osc

47
46

osc/∆V

∆f

osc/∆T

osc

dischg

= +70°C for UC3844, UC3845

high

= +85°C for UC2844, UC2845

high

– 0.2 1.0 – 0.2 1.0 %
– 5.0 – – 5.0 – %

– 1.6 – – 1.6 – V
– 10.8 – – 10.8 – mA

52

–

60

57

47
46

52

–

60

57

kHz

2

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

ELECTRICAL CHARACTERISTICS (V

= 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = T

CC

low

to T

high

[Note 3],

unless otherwise noted,)

UC284X UC384X

Characteristics Symbol Min Typ Max Min Typ Max Unit

ERROR AMPLIFIER SECTION

Voltage Feedback Input (VO = 2.5 V) V
Input Bias Current (VFB = 2.7 V) I
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A

FB
IB

VOL

2.45 2.5 2.55 2.42 2.5 2.58 V
– –0.1 –1.0 – –0.1 –2.0 µA

65 90 – 65 90 – dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – 0.7 1.0 – MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 – 60 70 – dB
Output Current

Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)

I

Sink

I

Source

2.0

–0.512–1.0

–
–

2.0

–0.512–1.0

–
–

Output Voltage Swing

High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to V

, VFB = 2.7 V)

ref

V

OH

V

OL

5.0

6.2

–

0.8

1.1

–

5.0

6.2

–

0.8

–

1.1

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 4 & 5) A
Maximum Current Sense Input Threshold (Note 4) V
Power Supply Rejection Ratio

PSRR

VCC = 12 V to 25 V (Note 4)
Input Bias Current I
Propagation Delay (Current Sense Input to Output) t

PLH(IN/OUT)

V
th

IB

2.85 3.0 3.15 2.85 3.0 3.15 V/V

0.9 1.0 1.1 0.9 1.0 1.1 V

– 70 – – 70 –
– –2.0 –10 – –2.0 –10 µA
– 150 300 – 150 300 ns

OUTPUT SECTION

Output Voltage

Low State (I

High State (I

Output Voltage with UVLO Activated

VCC = 6.0 V, I
Output Voltage Rise T ime (CL = 1.0 nF, TJ = 25°C) t
Output Voltage Fall T ime (CL = 1.0 nF, TJ = 25°C) t

(I

(I

Sink
Sink
Sink
Sink

Sink

= 20 mA)
= 200 mA)
= 20 mA)
= 200 mA)

= 1.0 mA

V

OL

V

OH

V

OL(UVLO)

r
f

–

12
12

0.1

–

1.6

13.5

13.4

0.4

2.2

–

0.1

–

–

13

–

12

1.6

13.5

13.4

0.4

2.2
–
–

– 0.1 1.1 – 0.1 1.1
– 50 150 – 50 150 ns
– 50 150 – 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold

UCX844
UCX845

Minimum Operating Voltage After Turn–On

UCX844
UCX845

V

V

CC(min)

th

15

7.8

9.0

7.0

16

8.4

10

7.6

17

9.0

11

8.2

14.5

7.8

8.5

7.0

16

8.4

10

7.6

17.5

9.0

11.5

8.2

PWM SECTION

Duty Cycle

Maximum
Minimum

DC

DC

max

min

46

48

–

50

–

47

0

48

–

–

50

0

TOTAL DEVICE

Power Supply Current (Note 2)

Startup:
(VCC = 6.5 V for UCX845A,

(VCC 14 V for UCX844) Operating

Power Supply Zener Voltage (ICC = 25 mA) V

NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
T

= –20°C for UC3844, UC3845 T

low

T

= –25°C for UC2844, UC2845 T

low

4.This parameter is measured at the latch trip point with VFB = 0 V.

5.Comparator gain is defined as: A

∆V Output Compensation

V

∆V Current Sense Input

high

high

I

CC

–
–

Z

= +70°C for UC3844, UC3845

= +85°C for UC2844, UC2845

30 36 – 30 36 – V

0.5
12

1.0
17

–

0.5

–

12

1.0
17

mA

V

dB

V

V

V

V

%

mA

MOTOROLA ANALOG IC DEVICE DATA

3

UC3844, 45 UC2844, 45

Figure 1. Timing Resistor versus

Oscillator Frequency

100

50

Ω

20

10

5.0

, TIMING RESISTOR (k )

T

2.0

R

NOTE: Output switches
at one–half the oscillator
frequency.

1.0
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M

f

, OSCILLAT OR FREQUENCY (Hz)

osc

VCC = 15 V
TA = 25

Figure 3. Error Amp Small Signal

Transient Response

VCC = 15 V

2.55 V

AV = –1.0
TA = 25

Figure 2. Output Deadtime versus

Oscillator Frequency

75

°

C

70

65

60

55

% DT, PERCENT OUTPUT DEADTIME

50

10 k 20 k 50 k 100 k 200 k 500 k 1.0 M

CT = 10 nF

f

, OSCILLAT OR FREQUENCY (Hz)

osc

5.0 nF

500 pF

1.0 nF

2.0 nF

100 pF

200 pF

Figure 4. Error Amp Large Signal

Transient Response

VCC = 15 V

°

C

3.0 V

AV = –1.0

°

TA = 25

C

2.5 V

2.45 V

0.5 µs/DIV

Figure 5. Error Amp Open Loop Gain and

Phase versus Frequency

100

80

60

40

20

, OPEN LOOP VOL TAGE GAIN (dB)

0

VOL

A

–20

100 1.0 k 10 k 100 k 1.0 M

Gain

f, FREQUENCY (Hz)

VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K

°

C

TA = 25

Phase

10 M10

2.5 V

20 mV/DIV

2.0 V

Figure 6. Current Sense Input Threshold

0

30

60

90

120

150
180

1.2
VCC = 15 V

1.0

0.8

0.6

0.4

, EXCESS PHASE (DEGREES)

0.2

φ

, CURRENT SENSE INPUT THRESHOLD (V)

th

0

V

0

200 mV/DIV

1.0 µs/DIV

versus Error Amp Output Voltage

TA = 25°C

TA = 125°C

TA = –55°C

2.0 4.0 6.0 8.0

VO, ERROR AMP OUTPUT VOLTAGE (V)

4

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

Figure 7. Reference V oltage Change

versus Source Current

0

VCC = 15 V

–4.0

–8.0

–12

–16

, REFERENCE VOLTAGE CHANGE (mV)

–20

ref

V

∆

–24

0 20 40 60 80 100 120

TA = 125°C

TA = –55°C

TA = 25°C

I

, REFERENCE SOURCE CURRENT (mA)

ref

Figure 9. Reference Load Regulation Figure 10. Reference Line Regulation

VCC = 15 V
IO = 1.0 mA to 20 mA

°

C

TA = 25

Figure 8. Reference Short Circuit Current

versus T emperature

110

VCC = 15 V

≤

0.1

RL

90

70

, REFERENCE SHORT CIRCUIT CURRENT (mA)

50

SC

–55 –25 0 25 50 75 100 125

I

TA, AMBIENT TEMPERATURE (

°

C)

VCC = 12 V to 25 V

°

C

TA = 25

Ω

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

∆

Figure 11. Output Saturation Voltage

versus Load Current

, OUTPUT SA TURATION VOLTAGE (V)

sat

V

0
–1.0
–2.0

3.0

2.0

1.0
0

V

CC

TA = 25°C

TA = –55°C

IO, OUTPUT LOAD CURRENT (mA)

2.0 ms/DIV

Source Saturation

(Load to Ground)

TA = –55°C

Sink Saturation

(Load to VCC)

VCC = 15 V

µ

s Pulsed Load

80

120 Hz Rate

TA = 25°C

Gnd

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

∆

2.0 ms/DIV

Figure 12. Output Waveform

VCC = 15 V

90%

10%

8006004002000

50 ns/DIV

CL = 1.0 nF

°

C

TA = 25

MOTOROLA ANALOG IC DEVICE DATA

5

UC3844, 45 UC2844, 45

Figure 14. Supply Current versus

Figure 13. Output Cross Conduction

VCC = 30 V
CL = 15 pF

°

C

TA = 25

, OUTPUT VOL TAGEV

O

25

20

15

Supply V oltage

RT = 10 k
CT = 3.3 nF
VFB = 0 V
I

= 0 V

Sense

°

C

TA = 25

, SUPPLY CURRENT

CC

I

100 ns/DIV

100 mA/DIV 20 V/DIV

10

, SUPPLY CURRENT (mA)

CC

I

5

UCX845

0

010203040

UCX844

VCC, SUPPLY VOLTAGE (V)

PIN FUNCTION DESCRIPTION

Pin

8–Pin 14–Pin

1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this

4 7 RT/C

5 – Gnd This pin is combined control circuitry and power ground (8–pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced

7 12 V
8 14 V
– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back to the

– 11 V

– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected to back to

– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.

Function Description

Feedback

T

CC
ref

C

This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.

information to terminate the output switch conduction.
The Oscillator frequency and maximum Output duty cycle are programmed by connecting

resistor RT to V

and sunk by this pin. The output switches at one–half the oscillator frequency.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT.

power source. It is used to reduce the effects of switching transient noise on the control circuitry .
The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With

a separate power source connection, it can reduce the effects of switching transient noise on the
control circuitry.

the power source ground.

and capacitor CT to ground. Operation to 1.0 MHz is possible.

ref

6

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

OPERA TING DESCRIPTION

The UC3844, UC3845 series are high performance, fixed
frequency, current mode controllers. They are specifically
designed for Off–Line and dc–to–dc converter applications
offering the designer a cost effective solution with minimal
external components. A representative block diagram is
shown in Figure 15.

Oscillator

The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor C
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in a
low state, thus producing a controlled amount of output
deadtime. An internal flip–flop has been incorporated in the
UCX844/5 which blanks the output off every other clock cycle
by holding one of the inputs of the NOR gate high. This in
combination with the CT discharge period yields output
deadtimes programmable from 50% to 70%. Figure 1 shows
RT versus Oscillator Frequency and figure 2, Output
Deadtime versus Frequency, both for given values of CT.
Note that many values of RT and CT will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency .

In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 17. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 18. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved to realize output deadtimes of greater than 70%

Error Amplifier

A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 5). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 µA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 28). The output voltage is offset by two
diode drops (≈ 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (VOL). This occurs when the
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 20, 21). The Error

Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
voltage (VOH) to reach the comparator’s 1.0 V clamp level:

R

f(min)

Current Sense Comparator and PWM Latch

T

The UC3844, UC3845 operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the inductor current on a cycle–by–cycle basis. The current
Sense Comparator PWM Latch configuration used ensures
that only a single pulse appears at the Output during any
given oscillator cycle. The inductor current is converted to a
voltage by inserting the ground referenced sense resistor R
in series with the source of output switch Q1. This voltage is
monitored by the Current Sense Input (Pin 3) and compared
a level derived from the Error Amp Output. The peak inductor
current under normal operating conditions is controlled by the
voltage at pin 1 where:

Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:

When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 19. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.

A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 23.

3.0 (1.0 V) + 1.4 V

≈

Ipk =

V

(Pin 1)

I

pk(max)

0.5 mA

3 R

=

– 1.4 V

S

1.0 V
R

S

= 8800 Ω

pk(max)

S

clamp

MOTOROLA ANALOG IC DEVICE DATA

7

UC3844, 45 UC2844, 45

Figure 15. Representative Block Diagram

V

7(12)

CC

V

CC

V

in

V

ref

8(14)

R

T

C

Voltage Feedback
Input

Output
Compensation

4(7)

T

2(3)

1(1)

Reference
Regulator

R

Internal

2.5V
R

+
–

Error

Amplifier

Pin numbers in parenthesis are for the D suffix SO–14 package.

Bias

Oscillator

+

1.0mA

2R

+
–

+

V

3.6V

R

1.0V
Current Sense

Comparator

5(9)Gnd

ref

–

UVLO

S

–

R

+

V

CC

UVLO

QT

Q

–

PWM
Latch

+
–

+

+

–

Sink Only

=

Positive True Logic

36V

V

C

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)

Q1

R

S

Capacitor C

Latch

‘‘Set’’ Input

Output/

Compensation

Current Sense

Input

Latch

‘‘Reset’’ Input

Output

Figure 16. Timing Diagram

T

Large RT/Small C

T

Small RT/Large C

T

8

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

Undervoltage Lockout

Two undervoltage lockout comparators have been
incorporated to guartantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC and the reference output (V

) are each

ref

monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX844,
and 8.4 V/7.6 V for the UCX845. The V

comparator upper

ref

and lower thresholds are 3.6 V/3/4 V. The large hysteresis
and low startup current of the UCX844 makes it ideally suited
in off–line converter applications where efficient bootstrap
startup techniques later required (Figure 29). The UCX845 is
intended for lower voltage dc–to–dc converter applications. A
36 V zener is connected as a shunt regulator from VCC to
ground. Its purpose is to protect the IC from excessive
voltage that can occur during system startup. The minimum
operating voltage for the UCX844 is 11 V and 8.2 V for the
UCX845.

Output

These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ± 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever and undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.

The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the I

pk(max)

clamp

level. The separate VC supply input allows the designer

added flexibility in tailoring the drive voltage independent of
V

A zener clamp is typically connected to this input when

CC.

driving power MOSFET s in systems where VCC is greater the
20 V. Figure 22 shows proper power and control ground
connections in a current sensing power MOSFET
application.

Reference

The 5.0 V bandgap reference is trimmed to ± 1.0%
tolerance at TJ = 25°C on the UC284X, and ± 2.0% on the
UC384X. Its primary purpose is to supply charging current to
the oscillator timing capacitor. The reference has short circuit
protection and is capable of providing in excess of 20 mA for
powering additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency

circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC, VC,
and V

may be required depending upon circuit layout. This

ref

provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.

Figure 17. External Clock Synchronization

V

ref
8(14)

R

T

External
Sync
Input

0.01

The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.

4(7)

C

T

47

2(3)

1(1)

R

Bias

R

Osc

+

+
–

EA

MOTOROLA ANALOG IC DEVICE DATA

2R

Figure 18. External Duty Cycle Clamp and

Multi–Unit Synchronization

R

A

8

R

B

5.0k

6

5

5.0k

2

R

5(9)

f =

C

1.44

(RA + 2RB)C

5.0k

1

+
–

+
–

4

R

Q

S

MC1455

D

max

=

RA + 2R

R

B

8(14)

3

7

B

4(7)

2(3)

1(1)

R
R

+
–

EA

T o Additional
UCX84XA’ s

Bias

Osc

+

2R

R

5(9)

9

UC3844, 45 UC2844, 45

Figure 19. Adjustable Reduction of Clamp Level Figure 20. Soft–Start Circuit

V

CC

7(12)

V

in

R2

R1

V

Clamp

C

I

pk(max)

t

Softstart

+

–

T

S

Q

R

Comp/Latch

I

pk(max)

Where: 0 ≤ V

8(14)

4(7)

2(3)

1(1)

R
R

1.67
2

1

+ 1

+
–

R

Bias

R

Osc

+

1.0mA

EA

+ 0.33 x 10

2R

5.0V

ref

+
–

+

–

V

Clamp

–
+

R

1.0V

5(9)

R1 R

R1 + R

2

2

–3

Figure 21. Adjustable Buffered Reduction of

Clamp Level with Soft–Start

+

T

S

Q

R

Comp/Latch

2

2

8(14)

4(7)

2(3)

R2

1(1)

MPSA63

R1

V

V

≈

= – In 1 –

Clamp

Clamp

R

S

R

Bias

R

Osc

+

1.0mA

+
–

EA

1.67

R

2

+ 1

R

1

Where: 0 ≤ V

V

C

3V

Clamp

2R

R

5(9)

+ 0.33 x 10

≤ 1.0 V

Clamp

C

R1 + R

+

–

V

Clamp

–3

R1 R

5.0V

1.0V

R1 + R

2

ref

+
–

–
+

R1 R

2

5.0V

5(9)

+

–

1.0V

ref

+
–

T

S

Q

–

R

+

+

–

7(11)

6(10)

5(8)

3(5)

V

Clamp

≈

R

S

Clamp

≤ 1.0 V

Q1

R

S

8(14)

4(7)

2(3)

1.0M
1(1)

C

t

Soft–Start

R
R

+

+
–

EA



3600C in µF

Bias

Osc

1.0mA
2R

R

Figure 22. Current Sensing Power MOSFET

V

V

CC

V

7(12)

–

+

–

7(11)

6(10)

5(8)

3(5)

in

5.0V

ref

+
–

+

Q1

R

S

–

–
+

Virtually lossless current sensing can be achieved with the implement of a SENSEFET
power switch. For proper operation during over current conditions, a reduction of the
I

clamp level must be implemented. Refer to Figures 19 and 21.

pk(max)

+

–

T

S

Q

R

Comp/Latch

Control CIrcuitry

Ground:

To Pin (9)

CC

(12)

+

–

(11)

(10)

(8)

(5)

G

R

1/4 W

D

M

S

V

in

SENSEFET

S

K

Power Ground

T o Input Source

RS Ipk r

DS(on)

≈

V

5

Pin

r

+ R

DM(on)

RS = 200

5 = 0.075 I

pin

S

pk

If: SENSEFET = MTP10N10M

Then: V

Return

10

Figure 23. Current Waveform Spike Suppression

V

5.0V

+

–

ref

+
–

S

–

R

+

Comp/Latch

CC

7(12)

+

–

+

–

7(11)

T

Q

6(10)

5(8)

3(5)

V

in

Q1

R

C

The addition of the RC filter will eliminate

R

S

instability caused by the leading edge spike on
the current waveform.

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

Figure 24. MOSFET Parasitic Oscillations

V

CC

7(12)

5.0V

ref

+
–

+

–

–
+

Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance
in the gate–source circuit.

+

–

T

S

Q

R

Comp/Latch

+

–

7(11)

6(10)

5(8)

3(5)

V

in

R

Q1

g

R

S

Figure 26. Isolated MOSFET Drive

5.0V

+

–

ref

+
–

T

S

–

R

+

Comp/Latch

V

CC

7(12)

+

–

+

–

Q

7(11)

6(10)

5(8)

3(5)

C

Isolation

Boundary

R

R

S

N

V

in

Q1

S

VGS Waveforms

+
0

–

50% DC 25% DC

V

Ipk =

N

p

(pin 1)

3 R

+
0
–

– 1.4

S

Figure 25. Bipolar Transistor Drive

I

B

+

0

–

The totem–pole output can furnish negative base current for enhanced
transistor turn–off, with the addition of capacitor C1.

Base Charge

Removal

6(1)

5(8)

3(5)

C

V

in

1

Q1

R

S

Figure 27. Latched Shutdown

8(14)

4(7)

N

P

N

S

MCR

101

2N

3905

2N

3903

2(3)

1(1)

R
R

+

+
–

EA

Bias

Osc

1.0mA
2R

R

5(9)

Figure 28. Error Amplifier Compensation

From V

O

R

i

R

C

d

I

Rf ≥8.8 k

Error Amp compensation circuit for stabilizing any current–mode topology except
for boost and flyback converters operating with continuous inductor current.

R

2(3)

f

1(1)

2.5V

+

1.0mA

+
–

EA

2R

R

5(9)

MOTOROLA ANALOG IC DEVICE DATA

The MCR101 SCR must be selected for a holding of less than 0.5 mA at
T

. The simple two transistor circuit can be used in place of the SCR as

A(min)

shown. All resistors are 10 k.

From V

O

R

p

R

i

C

R

I

d

C

p

Error Amp compensation circuit for stabilizing current–mode boost and flyback
topologies operating with continuous inductor current.

R

2(3)

f

1(1)

2.5V

+

1.0mA

+
–

EA

2R

R

5(9)

11

UC3844, 45 UC2844, 45

Figure 29. 27 Watt Off–Line Flyback Regulator

Ω

4.7

115Vac

8(14)

0.01

33k

4(7)

1.0nF

18k

4.7k

T1 – Primary: 45 Turns # 26 AWG

T1 – Secondary

T1 – (2 strands) Bifiliar Wound

T1 – Secondary 5.0 V: 4 Turns (six strands)

T1 – #26 Hexfiliar Wound

T1 – Secondary Feedback: 10 Turns #30 AWG

T1 – (2 strands) Bifiliar Wound
T1 – Core: Ferroxcube EC35–3C8
T1 – Bobbin: Ferroxcube EC35PCB1
T1 – Gap

L1 – 15

L2, L3 – 25

2(3)

150k

100pF

1(1)

±

12 V: 9 Turns # 30 AWG

≈

0.01” for a primary inductance of 1.0 mH

µ

H at 5.0 A, Coilcraft Z7156.

µ

H at 1.0 A, Coilcraft Z7157.

+

+
–

EA

Osc

Bias

L1

+

+

++

L3

1N4937

MDA

202

5(9)

5.0V

+

+

250

ref

+
–

–
+

Comp/Latch

Ω

MBR1635

T1

2200 1000

MUR110

1000

1000 10

MUR110

680pF

2.7k

68

22

Ω

1.0k

470pF

3300pF

++

47

MTP

4N50

0.5

4.7k

56k

1N4935 1N4935

7(12)

100

+
–

+

T

S

Q

R

7(11)

6(10)

5(8)
3(5)

1N4937

1N5819

Test Conditions Results

Line Regulation: 5.0 V

± 12 V

Load Regulation: 5.0 V

± 12 V

Output Ripple: 5.0 V

Vin = 95 Vac to 130 Vac ∆ = 50 mV or ± 0.5%

∆ = 24 mV or ± 0.1%

Vin = 115 Vac, I
Vin = 115 Vac, I

= 1.0 A to 4.0 A

out

= 100 mA to 300 mA

out

∆ = 300 mV or ± 3.0%
∆ = 60 mV or ± 0.25%

Vin = 115 Vac 40 mV

± 12 V

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents, unless otherwise noted.

10

5.0V/4.0A

+

5.0V RTN
12V/0.3A

+L2

±

12V RTN

–12V/0.3A

80 mV

pp
pp

12

MOTOROLA ANALOG IC DEVICE DATA

UC3844, 45 UC2844, 45

Figure 30. Step–Up Charge Pump Converter

Vin = 15V

UC3845

8(14)

R

Internal

2.5V

10k

4(7)

1.0nF

2(3)

1(1)

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series
resistor may be required when using tantalum or other low ESR capacitors. The converter’s output can provide
excellent line and load regulation by connecting the R2/R1 resistor divider as shown.

R

+
–

Error

Amplifier

Bias

Oscillator

+

0.5mA
2R

R

3.6V

1.0V
Current Sense

Comparator

5(9)

Reference

Regulator

+
–

+

V

ref

–

UVLO

–
+

T

S
R

V

CC

UVLO

Q

PWM
Latch

7(12)

+

–

34V

+

–

7(11)

6(10)

5(8)

3(5)

VO =

+

1N5819

15 10

Connect to
Pin 2 for
closed loop
operation.

2.5

47

+

R2
R2

Output Load Regulation

(open loop configuration)

IO (mA) VO (V)

0
2

9
18
36

1N5819

+

47

R2

R1

+ 1

29.9

28.8

28.3

27.4

24.4

VO



2 (Vin)

Figure 31. V oltage–Inverting Charge Pump Converter

UC3845

8(14)

R

Internal

2.5V

10k

4(7)

1.0nF

2(3)

1(1)

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.

R

+
–

Error

Amplifier

Bias

Oscillator

+

0.5mA
2R

R

3.6V

1.0V
Current Sense

Comparator

5(9)

Reference

Regulator

+
–

+

V

ref

–

UVLO

–
+

T

S
R

V

CC

UVLO

Q

PWM
Latch

7(12)

+

–

34V

+

–

Vin = 15V

7(11)

6(10)

+

5(8)

3(5)

+

15 10

47

1N5819

18
32

+

0
2
9

–14.4
–13.2
–12.5
–11.7
–10.6

1N5819

Output Load Regulation

IO (mA) VO (V)

47

VO



– (Vin)

MOTOROLA ANALOG IC DEVICE DATA

13

NOTE 2

–T–

SEATING
PLANE

14

F

–A–

–T–

SEATING
PLANE

H

G

–A–

14 8

G

D 14 PL

0.25 (0.010) A

UC3844, 45 UC2844, 45

OUTLINE DIMENSIONS

58

–B–

C

N

D

0.13 (0.005) B

71

M

–B–

T

K

M

M

A

T

P 7 PL

0.25 (0.010) B

C

K

S

B

S

N SUFFIX

PLASTIC PACKAGE

CASE 626–05

ISSUE K

L

J

M

M

D SUFFIX

PLASTIC PACKAGE

CASE 751A–03

(SO–14)
ISSUE F

M

M

X 45

R

_

M

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070

G 2.54 BSC 0.100 BSC

H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC

M ––– 10 ––– 10

N 0.76 1.01 0.030 0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

F

J

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

__

____

INCHESMILLIMETERS

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE /Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: RMF [e-mail] – TOUCHT ONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

14

◊

MOTOROLA ANALOG IC DEVICE DATA

UC3844/D

*UC3844/D*