Datasheet UC2825N Specification

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Page 1

High Speed PWM Controller

FEATURES DESCRIPTION

Compatible with Voltage or Current Mode

•

Topologies Practical Operation Switching Frequencies

•

to 1MHz 50ns Propagation Delay to Output

•

High Current Dual Totem Pole Outputs

•

(1.5A Peak) Wide Bandwidth Error Amplifier

•

Fully Latched Logic with Double Pulse

•

Suppression Pulse-by-Pulse Current Limiting

•

Soft Start / Max. Duty Cycle Control

•

• Under-Voltage Lockout with Hysteresis

• Low Start Up Current (1.1mA)

The UC1825 family of PWM control ICs is optimized for high fre quency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either cur rent-mode or voltage mode systems with the capability for input volt age feed-forward.

Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the out puts are high impedance.

These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level.

application

INFO

available

UC1825 UC2825 UC3825

BLOCK DIAGRAM

SLUS235A - MARCH 1997 - REVISED MARCH 2004

UDG-92030-2

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ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (Pins 13, 15). . . . . . . . . . . . . . . . . . . . . . . . 30V

Output Current, Source or Sink (Pins 11, 14)

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

Pulse (0.5 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A

Analog Inputs

(Pins 1, 2, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

(Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

Clock Output Current (Pin 4). . . . . . . . . . . . . . . . . . . . . . . -5mA

Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA

Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA

Oscillator Charging Current (Pin 5). . . . . . . . . . . . . . . . . . -5mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C

SOIC-16 (Top View) DW Package

CONNECTION DIAGRAMS

DIL-16 (Top View) J or N Package

PLCC-20 & LCC-20 (Top View) Q & L Packages

UC1825 UC2825 UC3825

PACKAGE PIN FUNCTION

FUNCTION

N/C 1 INV 2 NI 3 E/A Out 4 Clock 5 N/C 6 R

T 7

T 8

Ramp 9 Soft Start 10 N/C 11 ILIM/SD 12 Gnd 13 Out A 14 Pwr Gnd 15 N/C 16 V

C 17

Out B 18 V

CC 19

REF 5.1V 20

THERMAL RATINGS TABLE

Package Q

DIL-16J 80-120 28

DIL-16N 90

PLCC-20 43-75(1) 34

LCC-20 70-80 20

SOIC-16 50-120

(1)

(2)

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UC1825 UC2825 UC3825

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC

= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TO.

UC1825

PARAMETERS TEST CONDITIONS UC2825

UC3825

MIN TOP MAX MIN TOP MAX UNITS

Reference Section

Output Voltage T Line Regulation 10V < V Load Regulation 1mA < I Temperature Stability* T

O = 25°C, IO = 1mA 5.05 5.10 5.15 5.00 5.10 5.20 V

CC < 30V 2 20 2 20 mV

O < 10mA 5 20 5 20 mV

MIN < TA <TMAX 0.2 0.4 0.2 0.4 mV/°C

Total Output Variation* Line, Load, Temperature 5.00 5.20 4.95 5.25 V Output Noise Voltage* 10Hz < f < 10kHz 50 50 µV Long Term Stability* T Short Circuit Current V

J = 125°C, 1000hrs. 5 25 5 25 mV REF = 0V -15 -50 -100 -15 -50 -100 mA

Oscillator Section

Initial Accuracy* T Voltage Stability* 10V < V Temperature Stability* T

J = 2°C 360 400 440 360 400 440 kHz

CC < 30V 0.2 2 0.2 2 %

MIN < TA <TMAX 55%

Total Variation* Line, Temperature 340 460 340 460 kHz

Oscillator Section (cont.)

Clock Out High 3.9 4.5 3.9 4.5 V Clock Out Low 2.3 2.9 2.3 2.9 V Ramp Peak* 2.6 2.8 3.0 2.6 2.8 3.0 V Ramp Valley* 0.7 1.0 1.25 0.7 1.0 1.25 V Ramp Valley to Peak* 1.6 1.8 2.0 1.6 1.8 2.0 V

Error Amplifier Section

Input Offset Voltage 10 15 mV Input Bias Current 0.6 3 0.6 3 µA Input Offset Current 0.1 1 0.1 1 µA Open Loop Gain 1V < V CMRR 1.5V < V PSRR 10V < V Output Sink Current V Output Source Current V Output High Voltage I Output Low Voltage I

O < 4V 60 95 60 95 dB

CM < 5.5V 75 95 75 95 dB

CC < 30V 85 110 85 110 dB PIN 3 = 1V 1 2.5 1 2.5 mA PIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA PIN 3 = -0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V

PIN 3 = 1mA 0 0 .5 1.0 0 0.5 1.0 V

Unity Gain Bandwidth* 3 5.5 3 5.5 MHz Slew Rate* 6 12 6 12 V/µs

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UC1825 UC2825 UC3825

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC

= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.

UC1825

PARAMETERS TEST CONDITIONS UC2825

UC3825

MIN TOP MAX MIN TOP MAX UNITS

PWM Comparator Section

Pin 7 Bias Current V

PIN 7 = 0V -1 -5 -1 -5 µA

Duty Cycle Range 0 80 0 85 % Pin 3 Zero DC Threshold V

PIN 7 = 0V 1.1 1.25 1.1 1.25 V

Delay to Output* 50 80 50 80 ns

Soft-Start Section

Charge Current V Discharge Current V

PIN 8 = 0.5V 3 9 20 3 9 20 µA PIN 8 = 1V 1 1 mA

Current Limit / Shutdown Section

Pin 9 Bias Current 0 < V

PIN 9 < 4V 15 10 µA

Current Limit Threshold 0.9 1.0 1.1 0.9 1.0 1.1 V Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V Delay to Output 50 80 50 80 ns

Output Section

Output Low Level I

Output High Level I

Collector Leakage V

OUT = 20mA 0.25 0.40 0.25 0.40 V

OUT = 200mA 1.2 2.2 1.2 2.2 V OUT = -20mA 13.0 13.5 13.0 13.5 V OUT = -200mA 12.0 13.0 12.0 13.0 V

C = 30V 100 500 10 500 µA

Rise/Fall Time* CL = 1nF 30 60 30 60 ns

Under-Voltage Lockout Section

Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V

Supply Current Section

Start Up Current V ICC V

CC = 8V 1.1 2.5 1.1 2.5 mA PIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 22 33 22 33 mA

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Printed Circuit Board Layout Considerations

High speed circuits demand careful attention to layout and component placement. To assure proper perfor mance of the UC1825 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the out put pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve

Error Amplifier Circuit

Simplified Schematic

UC1825 UC2825 UC3825

this purpose. 3) Bypass V

monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground

plane. 4) Treat the timing capacitor, CT, like a bypass ca pacitor.

CC,VC, and VREF. Use 0.1µF

Open Loop Frequency Response Unity Gain Slew Rate

PWM Applications

Conventional (Voltage Mode)

Current-Mode

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Oscillator Circuit

UC1825 UC2825 UC3825

Deadtime vs CT(3k RT100k)

Timing Resistance vs Frequency

Synchronized Operation

Two Units in Close Proximity

Deadtime vs Frequency

160

140

120

T (ns)

100

10k 100k

1.0nF

470pF

FREQ (Hz)

Generalized Synchronization

Page 7

Forward Technique for Off-Line Voltage Mode Application

Constant Volt-Second Clamp Circuit

The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, R sen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime.

T and CR are cho

UC1825 UC2825 UC3825

Output Section

Simplified Schematic Rise/Fall Time (CL=1nF)

Rise/Fall Time (CL=10nF)

Saturation Curves

Page 8

Open Loop Laboratory Test Fixture

This test fixture is useful for exercising many of the UC1825’s functions and measuring their specifications.

UC1825 UC2825 UC3825

UDG-92032-2

As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended.

Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency

UDG-92033-3

Page 9

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-87681012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

5962-8768101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101EA

5962-8768101QFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101QF

UC1825J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1825J

UC1825J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101EA

UC1825L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1825L

UC1825L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

UC1825W883B ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101QF

UC2825DW ACTIVE SOIC DW 16 40 Green (RoHS

UC2825DWG4 ACTIVE SOIC DW 16 40 Green (RoHS

UC2825DWTR ACTIVE SOIC DW 16 2000 Green (RoHS

UC2825DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS

UC2825J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -40 to 85 UC2825J

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

87681012A UC1825L/ 883B

UC1825J/883B

A UC1825W/883B

UC1825J/883B

87681012A UC1825L/ 883B

A UC1825W/883B

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825DW

11-Jul-2015

Samples

(4/5)

UC2825N ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br)

UC2825NG4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br)

Addendum-Page 1

CU NIPDAU N / A for Pkg Type -40 to 85 UC2825N

Page 10

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

UC2825Q ACTIVE PLCC FN 20 46 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU SN Level-2-260C-1 YEAR -40 to 85 UC2825Q

(4/5)

& no Sb/Br)

UC2825QTR OBSOLETE PLCC FN 20 TBD Call TI Call TI -40 to 85 UC2825Q

UC2825QTRG3 ACTIVE PLCC FN 20 TBD Call TI Call TI -40 to 85

UC3825DW ACTIVE SOIC DW 16 40 Green (RoHS

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW

& no Sb/Br)

UC3825DWG4 ACTIVE SOIC DW 16 40 Green (RoHS

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW

& no Sb/Br)

UC3825DWTR ACTIVE SOIC DW 16 2000 Green (RoHS

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW

& no Sb/Br)

UC3825DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW

& no Sb/Br)

UC3825J LIFEBUY CDIP J 16 1 TBD A42 N / A for Pkg Type 0 to 70 UC3825J

UC3825N ACTIVE PDIP N 16 25 Green (RoHS

CU NIPDAU N / A for Pkg Type 0 to 70 UC3825N

& no Sb/Br)

UC3825NG4 ACTIVE PDIP N 16 25 Green (RoHS

CU NIPDAU N / A for Pkg Type 0 to 70 UC3825N

& no Sb/Br)

UC3825Q ACTIVE PLCC FN 20 46 Green (RoHS

CU SN Level-2-260C-1 YEAR 0 to 70 UC3825Q

& no Sb/Br)

UC3825QTR ACTIVE PLCC FN 20 1000 Green (RoHS

CU SN Level-2-260C-1 YEAR 0 to 70 UC3825Q

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

11-Jul-2015

Samples

Addendum-Page 2

Page 11

PACKAGE OPTION ADDENDUM

www.ti.com

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1825, UC2825, UC2825M, UC3825, UC3825M :

Catalog: UC3825, UC2825, UC3825M, UC3825

•

11-Jul-2015

Military: UC2825M, UC1825

•

Space: UC1825-SP

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

•

Addendum-Page 3

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MECHANICAL DATA

MPLC004A – OCT OBER 1994

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

E1E

NO. OF

PINS

D/E

0.032 (0,81)

0.026 (0,66)

0.050 (1,27)

0.008 (0,20) NOM

D1/E1

MINMAXMIN

MAX

D2/E2

MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

D2/E2

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

MAX

20 28 44 52 68 84

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 17

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