Datasheet UC1846 Specification

Current Mode PWM Controller

FEATURES DESCRIPTION

Automatic Feed Forward Compensation

•

Programmable Pulse-by-Pulse Current

•

Limiting

Automatic Symmetry Correction in Push-pull

•

Configuration

Enhanced Load Response Characteristics

•

Parallel Operation Capability for Modular

•

Power Systems

Differential Current Sense Amplifier with

•

Wide Common Mode Range

Double Pulse Suppression

•

500mA (Peak) Totem-pole Outputs

•

±1% Bandgap Reference

•

The UC1846/7 family of control ICs provides all of the necessary
features to implement fixed frequency, current mode control
schemes while maintaining a minimum external parts count. The
superior performance of this technique can be measured in im
proved line regulation, enhanced load response characteristics, and
a simpler, easier-to-design control loop. Topological advantages in
clude inherent pulse-by-pulse current limiting capability, automatic
symmetry correction for push-pull converters, and the ability to par
allel “power modules" while maintaining equal current sharing.

Protection circuitry includes built-in under-voltage lockout and pro
grammable current limit in addition to soft start capability. A shut
down function is also available which can initiate either a complete
shutdown with automatic restart or latch the supply off.

Other features include fully latched operation, double pulse sup
pression, deadline adjust capability, and a ±1% trimmed bandgap
reference.

application

INFO

available

UC1846/7
UC2846/7
UC3846/7

-

-

-

-

-

-

• Under-voltage Lockout

• Soft Start Capability

• Shutdown Terminal

• 500kHZ Operation

BLOCK DIAGRAM

15

VIN

10

SYNC

9

RT

8

CT

3

C/S-

X3

4

C/S+

OSC

+

COMP

0.5 V

5.1 V
REFERENCE
REGULATOR

UVLO

LOCKOUT

S

R

S

The UC1846 features low outputs in the OFF state, while the
UC1847 features high outputs in the OFF state.

2VREF

13

F/F

Q

T

Q

Q

11VCAOUT

UC1846

Output Stage

UC1847

Output Inverted

14

BOUT

0.5 mA

INV

5

NI

E/A

6

7COMP

SLUS352A - JANUARY 1997 - REVISED MARCH 2002

350 mV

6k

12

GND

CURRENT

1

LIMIT ADJUST

SHUTDOWN

16

UDG-02057

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V

Collector Supply Voltage (Pin 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V

Output Current, Source or Sink (Pins 11, 14) . . . . . . . . . . . . . . . . . . . . . . . 500mA

Analog Inputs (Pins 3, 4, 5, 6, 16). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +V

Reference Output Current (Pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30mA

Sync Output Current (Pin 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA

Error Amplifier Output Current (Pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA

Soft Start Sink Current (Pin 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Oscillator Charging Current (Pin 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Power Dissipation at T
Power Dissipation at T

A=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW

C=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000mW

Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . +300°C

Note 1. All voltages are with respect to Ground, Pin 13. Currents are positive into,
negative out of the speficied terminal. Consult Packaging Section of Databook for
thermal limitations and considerations of packages. Pin numbers refer to DIL and
SOIC packages only.

CONNECTION DIAGRAMS

DIL-16, SOIC-16
(TOP VIEW)
J or N Package, DW Package

PLCC-20, LCC-20
(TOP VIEW)
Q, L Packages

UC1846/7
UC2846/7
UC3846/7

IN

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1
C/L SS 2
VREF 3
C/S- 4
C/S+ 5
N/C 6
E/A+ 7
E/A- 8
Comp 9
CT 10
N/C 11
RT 12
Sync 13
A Out 14
Gnd 15
N/C 16
VC 17
B Out 18
VIN 19
Shutdown 20

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS UC2846/UC2847

(Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for
UC1846/7; -40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7;
V

IN=15V, RT=10k, CT=4.7nF, TA=TJ.)

UC1846/UC1847

UC3846/UC3847

MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Reference Section

Output Voltage T

Line Regulation V

Load Regulation I

J=25°C, IO=1mA 5.05 5.10 5.15 5.00 5.10 5.20 V

IN=8V to 40V 5 20 5 20 mV

L=1mA to 10mA 3 15 3 15 mV

Temperature Stability Over Operating Range, (Note 2) 0.4 0.4 mV/°C

Total Output Variation Line, Load, and Temperature (Note 2) 5.00 5.20 4.95 5.25 V
Output Noise Voltage 10Hz ≤ f ≤10kHz, T

Long Term Stability T

Short Circuit Output Current V

J=125°C, 1000 Hrs. (Note 2) 5 5 mV

REF=0V -10 -45 -10 -45 mA

J=25°C (Note 2) 100 100 µV

2

UC1846/7
UC2846/7
UC3846/7

ELECTRICAL
CHARACTERISTICS (cont.)

PARAMETER TEST CONDITIONS UC2846/UC2847

(Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7;

-40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; V
C

T=4.7nF, TA=TJ.)

UC1846/UC1847

IN=15V, RT=10k,

UC3846/UC3847

MIN. TYP. MAX. MIN. TYP. MAX. UNITS

Oscillator Section

Initial Accuracy T

Voltage Stability V

J=25°C 39 43 47 39 43 47 kHz

IN=8V to 40V -1 2 -1 2 %

Temperature Stability Over Operating Range (Note 2) -1 -1 %

Sync Output High Level 3.9 4.35 3.9 4.35 V

Sync Output Low Level 2.3 2.5 2.3 2.5 V

Sync Input High Level Pin 8=0V 3.9 3.9 V

Sync Input Low Level Pin 8=0V 2.5 2.5 V

Sync Input Current Sync Voltage=3.9V, Pin 8=0V 1.3 1.5 1.3 1.5 mA

Error Amp Section

Input Offset Voltage 0.5 5 0.5 10 mV
Input Bias Current -0.6 -1 -0.6 -2 µA

Input Offset Current 40 250 40 250 nA

Common Mode Range V
Open Loop Voltage Gain ∆V

Unity Gain Bandwidth T

CMRR V

PSRR V

Output Sink Current V

Output Source Current V

High Level Output Voltage R

IN=8V to 40V 0 VIN-2V 0 VIN-2V V

O=1.2 to 3V, VCM=2V 80 105 80 105 dB

J=25°C (Note 2) 0.7 1.0 0.7 1.0 MHz

=0V to 38V, VIN=40V 75 100 75 100 dB

CM
IN=8V to 40V 80 105 80 105 dB

ID=-15mV to -5V, VPIN 7=1.2V 2 6 2 6 mA

ID=15mV to 5V, VPIN 7=2.5V -0.4 -0.5 -0.4 -0.5 mA
L=(Pin 7) 15kΩ 4.3 4.6 4.3 4.6 V

Low Level Output Voltage 0.7 1 0.7 1 V

Current Sense Amplifier Section

Amplifier Gain V

PIN 3=0V, Pin 1 Open (Notes 3 & 4) 2.5 2.75 3.0 2.5 2.75 3.0 V

Maximum Differential Input Pin 1 Open (Note 3)

Signal (V

Input Offset Voltage V

CMRR V

PSRR V

Input Bias Current V

Input Offset Current V

Input Common Mode Range 0 V

Delay to Outputs T

PIN 4-VPIN 3)RL (Pin 7)=15kW 1.1 1.2 1.1 1.2 V

PIN 1=0.5V, Pin 7 Open (Note 3) 5 25 5 25 mV

CM=1V to 12V 60 83 60 83 dB

IN=8V to 40V 60 84 60 84 dB
PIN 1=0.5V, Pin 7 Open (Note 3) -2.5 -10 -2.5 -10 µA
PIN 1=0.5V, Pin 7 Open (Note 3) 0.08 1 0.08 1 µA

IN-3 0 VIN-3 V

J=25°C, (Note 2) 200 500 200 500 ns

Current Limit Adjust Section

Current Limit Offset V

PIN 3=0V, VPIN 4=0V, Pin 7 Open

(Note 3) 0.45 0.5 0.55 0.45 0.5 0.55 V

Input Bias Current V

PIN 5=VREF,VPIN 6=0V -10 -30 -10 -30 µA

Shutdown Terminal Section

Threshold Voltage 250 350 400 250 350 400 mV

Input Voltage Range 0 V

IN 0VIN V

Minimum Latching Current (Note 6)

PIN 1) 3.0 1.5 3.0 1.5 mA

(I

3

UC1846/7
UC2846/7
UC3846/7

ELECTRICAL
CHARACTERISTICS (cont.)

PARAMETER TEST CONDITIONS UC2846/UC2847

Shutdown Terminal Section (cont.)

Maximum Non-Latching (Note 7)

Current (I

Delay to Outputs T

Output Section

Collector-Emitter Voltage 40 40 V

Collector Leakage Current V

Output Low Level I

Output High Level I

Rise Time C

Fall Time C

Under-Voltage Lockout Section

Start-Up Threshold 7.7 8.0 7.7 8.0 V

Threshold Hysteresis 0.75 0.75 V

Total Standby Current

Supply Current 17 21 17 21 mA

Note 2. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 3. Parameter measured at trip point of latch with VPIN 5 = VREF, VPIN 6 = 0V.

Note 4. Amplifier gain defined as:

Note 5. Applies to UC1846/UC2846/UC3846 only due to polarity of outputs.
Note 6. Current into Pin 1 guaranteed to latch circuit in shutdown state.
Note 7. Current into Pin 1 guaranteed not to latch circuit in shutdown state.

PIN 1) 1.5 0.8 1.5 0.8 mA

(Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7;

-40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; V
C

T=4.7nF, TA=TJ.)

UC1846/UC1847

IN=15V, RT=10k,

UC3846/UC3847

MIN. TYP. MAX. MIN. TYP. MAX. UNITS

J=25°C (Note 2) 300 600 300 600 ns

C=40V (Note 5) 200 200 µA

SINK=20mA 0.1 0.4 0.1 0.4 V

SINK=100mA 0.4 2.1 0.4 2.1 V

I

SOURCE=20mA 13 13.5 13 13.5 V

SOURCE=100mA 12 13.5 12 13.5 V

I

L=1nF, TJ=25°C (Note 2) 50 300 50 300 ns

L=1nF, TJ=25°C (Note 2) 50 300 50 300 ns

V

∆

PIN

7

V

G

=

;

V

∆

PIN

4

= 0 to 1.0V

PIN4

APPLICATIONS DATA

Oscillator Circuit

Output deadtime is determined by the external capacitor, CT, according to the formula:

ID= Oscillator discharge current at 25°C is typically 7.5.

T

For large values of R

:

τµ µ

ds Tf

() ()≈

145C

Oscillator frequency is approximated by the formula:

.

fT kHz

()

≈

2.2

Ωµ

RT k CT f

() ()

•

4

τµ µ

ds Tf

() ()=

145C

.










ID -

ID

3.6

Ω

RT (k )






.






APPLICATIONS DATA (cont.)

UC1846/7
UC2846/7
UC3846/7

Error Amp Output Configuration

Error Amp Open-Logic D.C. Gain vs Load Resistance

Error Amp Gain and Phase vs Frequency

Parallel Operation

5

APPLICATIONS DATA (cont.)

Peak Current (IS) is determined by the formula:

Pulse by Pulse Current Limiting

RVREF

2

RR

+

12

IS

=

Soft Start and Shutdown /Restart Functions

3R

UC1846/7
UC2846/7
UC3846/7

−

0.5

S

6

APPLICATIONS DATA (cont.)

A small RC filter may be required in some applications to reduce switch transients.
Differential input allows remote, noise free sensing.

UC1846/7
UC2846/7
UC3846/7

Current Sense Amp Connection

UC1846 Open Loop Test Circuit

7

PACKAGE OPTION ADDENDUM

www.ti.com

2-May-2005

PACKAGING INFORMATION

Orderable Device Status

5962-86806012A ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
5962-8680601EA ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC

5962-8680601V2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC

5962-8680601VEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

UC1846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC
UC1846J/80257 OBSOLETE CDIP J 16 TBD Call TI Call TI
UC1846J/80364 OBSOLETE CDIP J 16 TBD Call TI Call TI
UC1846J/80619 OBSOLETE CDIP J 16 TBD Call TI Call TI

UC1846J883B ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC

UC1846JQMLV ACTIVE CDIP J 16 TBD Call TI Call TI

UC1846L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC

UC1846LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI

UC1847J OBSOLETE CDIP J 16 TBD Call TI Call TI

UC1847J883B OBSOLETE CDIP J 16 TBD Call TI Call TI

UC1847L OBSOLETE LCCC FK 20 TBD Call TI Call TI

UC1847L883B OBSOLETE LCCC FK 20 TBD Call TI Call TI

UC2846DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR

UC2846DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR

UC2846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC

UC2846N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA

UC2846Q ACTIVE PLCC FN 20 46 TBD Call TI Level-2-220C-1 YEAR

UC2846QTR ACTIVE PLCC FN 20 1000 TBD Call TI Level-2-220C-1 YEAR

UC2847DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR

UC2847DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR

UC2847N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA

UC3846DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR

UC3846DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR

UC3846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC

UC3846N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA
UC3846Q ACTIVE PLCC FN 20 46 TBD Call TI Level-2-220C-1 YEAR

UC3846QTR ACTIVE PLCC FN 20 1000 TBD Call TI Level-2-220C-1 YEAR

UC3847DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR

UC3847DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR

UC3847J OBSOLETE CDIP J 16 TBD Call TI Call TI

UC3847N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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2-May-2005

Addendum-Page 2

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