Datasheet U62H64SA35 Datasheet (ZMD)

U62H64SA

Automotive Fast 8K x 8 SRAM

Features

p

Fast 8192 x 8 bit static CMOS RAM

p

35 ns Access Time

p

Bidirectional data inputs and data outputs

p

Three-state outputs

p

Data retention current at 3 V: < 50 µA

p

Standby current < 100 µA

p

TTL/CMOS-compatible

p

Automatic reduction of power dissipation in long Read or Write cycles

p

Power supply voltage 5 V

p

Operating temperature range

-40 to 125 °C

p

Quality assessment according to CECC 90000, CECC 90100 and CECC 90111

p

ESD protection> 2000 V

(MIL STD 883C M3015.7)

p

Latch-up immunity> 200 mA

p

Package: SOP28 (300 mil)

Description

The U62H64SA is a static RAM manufactured using a CMOS process technology with the following operating modes:

- Read - Standby

- Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 edge of E1 address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state (E1

= L and E2 = H), each address change leads to a new Read or Write cycle. In a Read cycle, the data outputs are activated by the falling edge of G data word read will be available at

= L), or the falling

(at E2 = H). The

, afterwards the

the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new re ad information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W rating current (at I the value of the operating current in

or G, the ope-

= 0 mA) drops to

O

the Standby mode. The Read cycle is finished by the falling edge of E2 or W

, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E1

and E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too.

Pin Configuration

1

n.c.

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3 A2 A1

A0 DQ0 DQ1 DQ2 VSS

SOP

8 9 10 11 12 13 14

Top View

December 12, 1997 1

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VCC W (WE) E2 (CE2) A8 A9 A11 G (OE) A10 E1 (CE1) DQ7 DQ6 DQ5 DQ4 DQ3

Pin Description

Signal Name Signal Description

A0 - A12 Address Inputs DQ0 - DQ7 Data In/Out E1 E2 G W VCC Power Supply Voltage VSS Ground n.c.

Chip Enable 1 Chip Enable 2 Output Enable Write Enable

not connected

U62H64SA

Block Diagram

A6 A7 A8 A9 A10 A11 A12

A0 A1 A2 A3 A4 A5

Inputs

Row Address

Inputs

Column Address

Address Change Detector

Row Decoder

Column Decoder

Memory Cell

Array

128 Rows

64 x 8 Columns

Sense Amplifier/

Write Control Logic

Clock

Generator

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5

Bidirectional Data I/O

DQ6 DQ7

E2 E1

V

CC

W G

SS

V

Truth Table

Operating Mode E1 E2 W G DQ0 - DQ7

Standby/not

selected

* L * * High-Z

H * * * High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z

H or L

*

Characteristics

All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V input levels of V with the exception of the t

= 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,

IL

-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.

dis

,as well as

I

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage V Input Voltage V Output Voltage V Operating Temperat ure T Storage Temperature T Output Short-Circuit Current

at V

= 5 V and VO = 0 V

CC

* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.

*

CC

I

O

a

stg

|IOS|200mA

-0.3 7 V

-0.3 VCC + 0.5 V

-40 125 °C

-65 150 °C

December 12, 19972

U62H64SA

Recommended Operating Conditions

Power Supply Voltage V Data Retention Voltage V

Input Low Voltage

*

Input High Voltage V

*

-2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns

Symbol Conditions Min. Max. Unit

CC

CC(DR)

V

IL

IH

4.5 5.5 V

2.0

-

-0.3 0.8 V

2.2 VCC+0.3 V

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode (CMOS level)

Supply Current - Standby Mode (TTL level)

Supply Current - Data Retention Mode

Output High Voltage Output Low Voltage

Output High Current Output Low Current

Input High Leakage Current Input Low Leakage Current

I

CC(OP)

I

CC(SB)

I

CC(SB)1

I

CC(DR)

V

OH

V

OL

I

OH

I

OL

I

IH

I

IL

V

CC

V

IL

V

IH

t

cW

V

CC

V

E1

VCC V

E1

V

CC(DR)

V

E1

V

CC

I

OH

V

CC

I

OL

V

CC

V

OH

V

CC

V

OL

V

CC

V

IH

V

CC

V

IL

= V

= 5.5 V = 0.8 V = 2.2 V =35 ns

= 5.5 V = V

E2

= 5.5 V = 2.2 V

E2

= 3.0 V = V

E2

= 4.5 V = -4.0 mA = 4.5 V = 8.0 mA

= 4.5 V = 2.4 V = 4.5 V = 0.4 V

= 5.5 V =5.5 V = 5.5 V = 0 V

- 0.2 V

CC

CC(DR)

- 0.2 V

2.4

8.0

-2

-

50

100

5

(typ. 2)

50

-

0.4

-4.0

-

2

-

Output Leakage Current

High at Three-State Outputs Low at Three-State Outputs

I

OHZ

I

OLZ

V

CC

V

OH

V

CC

V

OL

= 5.5 V = 5.5 V = 5.5 V = 0 V

-

-2

2

-

V

mA

µA

mA

µA

V V

mA mA

µA µA

December 12, 1997 3

U62H64SA

Switching Characteristics

Time to Output in Low-Z from

E1

LOW or E2 HIGH

G

LOW

W

HIGH

Cycle Time

Write Cycle Time Read Cycle Time

Access Time

E1

LOW or E2 HIGH to Data Valid

G

LOW to Data Valid

Address to Data Valid

Pulse Widths

Write Pulse Width Chip Enable to End of Write

Setup Times

Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time

Data Hold Time Address Hold from End of Write

Output Hold Time from Address Change t

E1

HIGH or E2 LOW to Output in High-Z

W

LOW to Output in High-Z

G

HIGH to Output in High-Z

E1

LOW or E2 HIGH to Power-Up t

E1 HIGH or E2 LOW to Power-Down t

Symbol Min. Max. Unit

Alt. IEC 35 35

t

LZCE

t

LZOE

t

LZWE

t t

t

ACE

t t

t t t t

t t

t

HZCE

t

HZWE

t

HZOE

WC RC

OE

AA

WP CW

AS CW WP

DS

DH

AH

OH

PU

PD

t

en(E)

t

en(G)

t

en(W)

t

cW

t

cR

t

a(E)

t

a(G)

t

a(A)

t

w(W)

t

w(E)

t

su(A)

t

su(E)

t

su(W)

t

su(D)

t

h(D)

t

h(A)

t

v(A)

t

dis(E)

t

dis(W)

t

dis(G)

5 0 0

35 35

35 15 35

20 25

0 25 20 15

0

5ns

15 15 12

0ns

35 ns

ns ns ns

ns ns

ns ns ns

ns ns

ns ns ns ns

ns ns

ns ns ns

Data Retention Mode E1-Controlled Data Retention Mode E2-Controlled

V

4.5 V V

≥ 2 V

CC(DR)

2.2 V

0 V

V

E2(DR)

V

CC(DR)

t

DR

≥ V

CC(DR)

- 0.2 V ≤ V

Data Retention

- 0.2 V or V ≤ V

E1(DR)

E2(DR)

CC(DR)

≤ 0.2 V

+ 0.3 V

t

rec

CC

4.5 V V

≥ 2 V

CC(DR)

2.2 V E1

0 V

V

E1(DR)

V

E2(DR)

0.8 V

≥ V ≤ 0.2 V

t

DR

CC(DR)

Data Retention

- 0.2 V or V

E1(DR)

Chip Deselect to Data Retention Time tDR: min 0 ns Operating Recovery Time at V

CC(DR)

t

: min tcR

rec

t

rec

≤ 0.2 V

December 12, 19974

V

CC

E2

0.8 V

Test Configuration for Functional Check

U62H64SA

5 V

481

V

O

Simultaneou s meas ur e-

ment of all 8 output pins

255

30 pF

1)

In measurement of t

dis(E)

V

A0 A1 A2 A3 A4

relevant test measur em ent

en(E)

, t

A5 A6 A7 A8 A9 A10 A11 A12

E1 E2 W G

en(W)

V

IH

V

IL

Input l ev el a cc ord ing to th e

, t

dis(G)

, t

dis(W)

CC

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

V

SS

, t

the capacitance is 5 pF.

en(G)

Capacitance Conditions Symbol Min. Max. Unit

V

= 5.0 V

Input Capacitance

Output Capacitance

CC

V

= V

I

SS

f = 1 MHz T

= 25 °C

a

C

I

C

O

8pF

10 pF

All pins not under test must be connected with ground by capacitors.

IC Code Number

Example

SU62H64

A

35

Type

Package

S = SOP

Access Time

35 = 35 ns

Operating Temperature Range

A = -40 to 125 °C

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week.

December 12, 1997 5

U62H64SA

AAAA

AAA

A

AAAA

AA

A

AAAA

AAA

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AAA

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Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled)

t

cR

Ai

DQi

Output

Previous Data Valid

Read Cycle 2 (during Read cycle:W = VIH, G-, E1- or E2-controlled)

Ai

t

su(A)

E1

t

E2

su(A)

G

DQi

Output

I

CC(OP)

I

CC(SB)

High-Z

*

t

PU

50 %

t

a(A)

t

v(A)

Addresses Valid

t

a(E)

t

en(E)

t

en(E)

t

en(G)

Addresses Valid

t

cR

t

a(E)

t

a(G)

Output Data Valid

t

dis(E)

t

dis(G)

Output Data Valid

t

dis(E)

*

t

PD

50 %

* The same applies to E1

Write Cycle 1 (W-controlled)

Ai

E1

E2

W

DQi

Input

DQi

Output

G

t

su(A)

t

dis(W)

t

cW

Addresses Valid

t

su(E)

t

su(E)

t

w(W)

t

su(D)

Input Data Valid

High-Z

t

h(D)

en(W)

h(A)

December 12, 19976

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AA

AAAA

A

AAAA

A

AAAA

Write Cycle 2 (E1-controlled)

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AAA

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AAA

Ai

E1

E2

W DQi

Input

DQi

Output

G

Write Cycle 3 (E2-controlled)

t

en(E)

t

su(A)

t

cW

Addresses Valid

t

w(E)

t

su(E)

t

su(W)

t

su(D)

t

dis(W)

t

Input Data Valid

High-Z

h(A)

U62H64SA

t

h(D)

t

cW

Ai

E1

t

su(A)

Addresses Valid

t

su(E)

t

w(E)

E2

t

su(W)

W

DQi

Input

DQi

Output

t

en(E)

t

dis(W)

G

AAA

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AAA

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undefined

AAA

t

su(D)

t

h(A)

t

h(D)

Input Data

Valid

High-Z

L- or H-level

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December 12, 1997 7

Memory Products 1998

Automotive Fast 8K x 8 SRAM U62H64SA

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

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Grenzstraße 28

Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de

• D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Internet Web Site: http://www.zmd.de

Datasheet U62H64SA35 Datasheet (ZMD)

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