Datasheet TU24C64CS3, TU24C64CP3 Datasheet (Turbo IC)

Turbo IC, Inc.

24C64

CMOS I²C 2-WIRE BUS

64K ELECTRICALLY ERASABLE PROGRAMMABLE R OM

8K X 8 BIT EEPROM

FEA TURES :

• Extended Pow er Supply Voltage
Single Vcc f or Read and Prog ramming
(Vcc = 2.7 V to 5.5 V)

• Low P o w er (Isb = 2µa @ 5.5 V)

• Extended I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (32 Bytes)

• Automatic P age write Operation (maxim um 10 ms)
Internal Control Timer
Internal Data Latches for 32 Bytes

• Hardware Data Protection by Write Protect Pin

• High Reliability CMOS Technology with EEPROM Cell
Endurance : 1,000,000 Cycles

Data Retention : 100 Years

PIN DESCRIPTION

A0
A1
A2

GND

1
2
3
4

8 pin SOIC

PIN DESCRIPTION

8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2

GND

8

1

7

2

6

3

5

4

8 pin PDIP

VCC
WP
SCL
SDA

DESCRIPTION:
The Turbo IC 24C64 is a serial 64K EEPROM fabricated
with Turbo’s proprietary, high reliability, high performance
CMOS technology . It’s 64K of memory is organized as 8,192
x 8 bits. The memory is configured as 256 pages with each
page containing 32 bytes. This device off ers significant ad­vantages in low power and lo w voltage applications .

The Turbo IC 24C64 uses the extended I²C addressing pro­tocol and 2-wire serial interface which includes a bidirec­tional serial data bus synchronized by a clock. It offers a
flexible b yte write and a faster 32-byte page write. The data
in the upper quadrant of memory can be protected by a
write protect pin.

The Turbo IC 24C64 is assembled in either a 8-pin PDIP or
8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are
device address input pins which are hardwired by the user .
Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA)
pin used for bidirectional transf er of data. Pin #6 is the serial
clock (SCL) input pin. Pin #7 is the write protect (WP) input
pin, and Pin #8 is the power supply (Vcc) pin.

All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C64 (slave) for a read or
write operation, the controller (master) issues a start condi­tion by pulling SDA from high to lo w while SCL is high. The
master then issues the device address byte which consists
of 1010 (A2) (A1) (A0) (R/W). The 4 most significant bits
(1010) are a device type code signifying an EEPROM de­vice. The A[2:0] bits represent the input levels on the 3 de­vice address input pins. The read/write bit determines
whether to do a read or write operation. After each byte is
transmitted, the receiver has to provide an ac knowledge by
pulling the SDA bus low on the ninth clock cycle. The ac­knowledge is a handshake signal to the transmitter indicat­ing a successful data transmission.

DEVICE ADDRESSES (A2-A0)

The address inputs are used to define the 3 least
significant bits of the 7-bit device address code ­1010 (A2) (A1) (A0). These pins can be con­nected either high or low. A maximum of eight
Turbo IC 24C64 can be connected in parallel,
each with a unique device address. When these
pins are left unconnected, the device addresses
are interpreted as zero.

WRITE PROTECT (WP)

When the write protect input is connected to Vcc,
the upper quadrant of memory (1800-1FFFH) is
protected against write operations. For normal
write operation, the write protect pin should be
grounded. When this pin is left unconnected, WP
is interpreted as zero.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C64. The pin is an
open-

1

drain output. A pullup resistor m ust be connected
from SDA to Vcc.

SERIAL CLOCK (SCL)
The SCL input synchronizes the data on the SD A
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C64.

Turbo IC, Inc.

24C64

DESCRIPTION (Continued)

For a write operation, the master issues a start condition,
device address byte , 2 memory address bytes, and then up
to 32 data bytes. The Turbo IC 24C64 acknowledges after
each byte transmission. To terminate the transmission, the
master issues a stop condition by pulling SDA from low to
high while SCL is high.

DEVICE OPERA TION:

For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C64 acknowledges,
and then transmits a data byte, which is accessed from the
EEPROM memory . The master acknowledges , indicating that
it requires more data bytes. The Turbo IC 24C64 transmits
more data bytes, with the memory address counter auto­matically incrementing for each data byte, until the master
does not acknowledge, indicating that it is terminating the
transmission. The master then issues a stop condition.

BIDIRECTIONAL BUS PROTOCOL:

The Turbo IC 24C64 follows the extended I²C bus protocol.
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a re­ceiver. The device controlling the transfer is the master and
the device being controlled is the slave. The master always
initiates the data transfers, and provides the clock for both
transmit and receive operations. The Turbo IC 24C64 acts as
a slave device in all applications. Either the master or the
slave can take control of the SDA bus, depending on the
requirement of the protocol.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SD A
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA b us is recognized as a STOP con­dition which terminates the communication and places the
T urbo IC 24C64 into standby mode . All other data tr ansitions
on the SDA bus must occur while SCL cloc k is low to ensure
proper operation.

ACKNO WLEDGE:

All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshak e sig­nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C64), releases the bus after sending a byte of data on the
SDA bu s. The receiver pulls the SD A bus low during the ninth
clock cycle to acknowledge the successful transmission of a
byte of data. If the SDA is not pulled low during the ninth
clock cycle, the Turbo IC 24C64 ter minates the data trans­mission and goes into standby mode.

For the write operation, the Turbo IC 24C64 acknowledges
after the device address byte, acknowledges after each
memory address byte, and acknowledges after each subse­quent data byte.

For the read operation, the Turbo IC 24C64 acknowledges
after the device address byte . Then the T urbo IC 24C64 trans­mits each subsequent data byte, and the master acknowl­edges after each data byte transf er, indicating that it requires
more data bytes. The Turbo IC 24C64 monitors the SDA bus
for the acknowledge . To terminate the transmission, the mas­ter does not acknowledge, and then sends a stop condition.

Write Cycle Timing

SCL

SDA

Note: The write cycle time t

WC

8th BIT ACK

t

WORD n

is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

STOP

CONDITION

2

WC

START

CONDITION

Turbo IC, Inc.

Data Valid

Start and Stop Definition

24C64

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

Output Acknowledge

SCL

DATA IN

DATA OUT

SDA

SCL

START

STOP

189

ACKNOWLEDGESTART

3

Turbo IC, Inc.

24C64

DEVICE ADDRESSING:

Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac­cess the selected Turbo IC 24C64 for a read or write opera­tion. The A[2:0] bits must match with the address input pins
of the selected Turbo IC 24C64. If there is a match, the se­lected Turbo IC 24C64 acknowledges during the ninth clock
cycle by pulling the SDA bus low. If there is no match, the
T urbo IC 24C64 does not ackno wledge during the ninth clock
cycle and goes into standby mode. The (R/W) bit is a high (1)
for read and low (0) for write .

DATA INPUT DURING WRITE OPERATION:

During the write operation, the Turbo IC 24C64 latches the
SDA b us signal on the rising edge of the SCL clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, the Turbo IC 24C64 serially shifts
the data onto the SDA bus on the falling edge of the SCL
clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2
memory address bytes. The memory address bytes can only
be sent as part of a write operation. The most significant
address byte XXX (B12) (B11) (B10) (B9) (B8) is sent first,
where X represents “don’t care”. Then the least significant
address byte (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) is sent
last.

BYTE WRITE OPERA TION:

The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol­lowed by one data byte , follow ed by an ackno wledge, then a
stop condition. After each b yte transfer, the Turbo IC 24C64
acknowledges the successful data transmission by pulling
the SDA bus low. The stop condition starts the internal
EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle. If the WP pin is high (1) and the
memory address is within the upper quadrant (1800-1FFFH)
of memory, then the stop condition does not start the inter­nal write cycle and the Turbo IC 24C64 is immediately ready
for the next command.

address counter is automatically incremented by one. The
stop condition starts the internal EEPROM write cycle only if
the stop condition occurs in the clock cycle immediately fol­lowing the acknowledge (10th cloc k cycle). All inputs are dis­abled until the completion of the write cycle. If the WP pin is
high (1) and the memory address is within the upper quad­rant (1800-1FFFH) of memory , then the stop condition does
not start the internal write cycle, and the Turbo IC 24C64 is
immediately ready for the next command.

POLLING ACKNO WLEDGE:

During the internal write cycle of a write operation in the T urbo
IC 24C64, the completion of the write cycle can be detected
by polling acknowledge. The master starts acknowledge poll­ing by issuing a start condition, then followed by the device
address byte 1010 (A2) (A1) (A0) 0. If the internal write cycle
is finished, the Turbo IC 24C64 acknowledges by pulling the
SDA bus low. If the internal write cycle is still ongoing, the
Turbo IC 24C64 does not acknowledge because it’s inputs
are disabled. Therefore, the device will not respond to any
command. By using polling acknowledge, the system delay
for write operations can be reduced. Otherwise, the system
needs to wait for the maxim um internal write cycle time, tWC,
given in the spec.

POWER ON RESET :

The Turbo IC 24C64 has a Power On Reset circuit (POR) to
prevent data corruption and accidental write operations dur­ing power up. On power up, the internal reset signal is on
and the Turbo IC 24C64 will not respond to any command
until the VCC v oltage has reached the POR threshold value.

P AGE WRITE OPERATION:

The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol­lowed by up to 32 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo
IC24C64 acknowledges the successful data transmission b y
pulling SDA low. After each data byte transfer, the memory

4

Device Address

Byte Write

Turbo IC, Inc.

24C64

1010A2A1A0R/W

MSB LSB

Page Write

SDA LINE

SDA LINE

S

T
A
R

T

S
T
A
R
T

DEVICE
ADDRESS

M
S
B

DEVICE
ADDRESS

M
S
B

W
R

I

T

FIRST

E

WORD ADDRESS

L

R

A

S

/

C

B

W

K

W

R

I

T

FIRST

E

WORD ADDRESS (n)

* * *

L

R

A

S

/

C

B

W

K

* * *

M
S
B

M
S
B

SECOND
WORD ADDRESS (n)

A
C
K

SECOND
WORD ADDRESS

A
C
K

L
S
B

S
T
O

DATA

A

L

C

S

K

B

DATA (n)

A
C
K

A
C
K

P

A
C
K

DATA (n + x)

//
//

S
T
O
P

A
C
K

* = Don't care bits

5

Turbo IC, Inc.

24C64

CURRENT ADDRESS READ:

The internal memory address counter of the T urbo IC 24C64
contains the last memory address accessed during the pre­vious read or write operation, incremented by one. To start
the current address read operation, the master issues a start
condition, followed b y the device address byte 1010 (A2) (A1)
(A0) 1. The Turbo IC 24C64 responds with an ackno wledge
by pulling the SDA bus low, and then serially shifts out the
data byte accessed from memory at the location correspond­ing to the memory address counter. The master does not
acknowledge, then sends a stop condition to terminate the
read operation. It is noted that the memory address counter
is incremented by one after the data byte is shifted out.

RANDOM ADDRESS READ:

The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed by the 2 memory ad­dress bytes. Following the acknowledge from the Turbo IC
24C64, the master starts the current read operation by issu­ing a start condition, followed by the device address byte
1010 (A2) (A1) (A0) 1. The Turbo IC 24C64 responds with

an acknowledge by pulling the SDA bus low, and then ser i­ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.

SEQUENTIAL READ:

The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C64 seri­ally shifts out the first data byte, the master acknowledges
by pulling the SDA bus low, indicating that it requires addi­tional data bytes. After the data b yte is shifted out, the Turbo
IC 24C64 increments the memory address counter by one.
Then the Turbo IC 24C64 shifts out the next data byte. The
sequential reads continues for as long as the master keeps
acknowledging. When the memory address counter is at the
last memory location, the counter will ‘roll-over’ when
incremented by one to the first location in memory (address
zero). The master terminates the sequential read operation
by not acknowledging, then sends a stop condition.

Current Address Read

Random Read

SDA LINE

S
T
A
R
T

M
S
B

SDA LINE

DEVICE
ADDRESS

S
T
A

R

T

M

S
B

W
R

I

T

E

L

R

S

/

B

W

DUMMY WRITE

ADDRESS N

A
C
K

WORD

DEVICE
ADDRESS

//
//

L
S
B

A
C
K

R
E
A
D

R

A

/

C

W

K

DATA

M

S
B

DEVICE

ADDRESS

S
T
O
P

N

O
A

C
K

R
E
A
D

A
C
K

DATA n

S

T
O
P

N

O
A

C
K

6

Sequential Read

SDA LINE

Turbo IC, Inc.

S
T
A
R
T

M
S
B

DEVICE
ADDRESS

R
E
A
D

L

R

S

/

B

W

DATA n

A
C
K

24C64

DATA n +1

A
C
K

A
C
K

DATA n + 2

A
C
K

DATA n + 3

S
T
O
P

N
O

A
C
K

ABSOLUTE MAXIMUM RATINGS
TEMPERATURE

Storage: -65° C to 150° C
Under Bias: -55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation sec­tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
Temperature Range: Commercial: 0° C to 70° C

Vcc Supply Voltage: 2.7 to 5.5 Volts
Endurance: 1,000,000 Cycles/Byte (Typical)

Data Retention: 100 Years

D.C. CHARA CTERISTICS

Symbol Parameter Condition Min Max Units

I
I

I

cc1
cc2

sb

Active Vcc Current READ at 100 KHZ 0.4 1 mA
Active Vcc Current WRITE at 100 KHZ 3 mA
Standby Current Vcc = 2. 7 v 0.5 uA

Vcc = 5.5 v 2.0 uA

I

li

I

lo

V

il

V

ih

V

ol2

V

ol1

Input Leakage Current Vin=Vcc Max 3 uA
Output Leakage Current 3 uA
Input Low Voltage -1.0 V
Input High Voltage Vcc+0.5 V
Output Low Vcc=3.0v Iol=2.1 mA 0.4 V
Output Low Vcc=2.7v Iol=-0.15 mA 0.25 V

7

Bus Timing

Turbo IC, Inc.

SCL

t

F

t

LOW

24C64

t

HIGH

t

LOW

t

R

t

SU.STA t

HD.STA

t

HD.DAT

t

SU.DAT

t

SU.STO

SDA IN

t

AA

t

DH

t

BUF

SDA OUT

A.C. CHARA CTERISTICS

Symbol Parameter 2.7 volt 5.5 volt Units

Min Max Min Max

SCL SCL Clock Frequency 100 400 kHZ
T Noise Suppression Time (1) 100 100 ns
t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.D AT

t

SU.D AT

t

R

t

F

t

SU.ST O

t

DH

t

WC

Clock Low Period 4.7 1.2 us
Clock High Period 4.0 0.6 us
SCL Low to SDA Data Out 0.1 4.5 0.1 0.9 us
Bus Free to New Start (1) 4.7 1.2 us
Start Hold Time 4.0 0.6 us
Start Setup Time 4.7 0.6 us
Data-in Hold Time 0 0 us
Data-in Set-up Time 200 100 ns
SCL and SDA Rise Time (1) 1.0 0.3 us
SCL and SDA F all Time (1) 300 300 ns
Stop Setup Time 4.7 0.6 us
Data-out Hold Time 100 50 ns
Write Cycle Time 10 10 ms

Note: 1 This parameter is characterized and not 100% tested.

TURBO IC PRODUCTS AND DOCUMENTS

1. All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.

2. T urbo IC does not assume any responsibility f or an y damage to the user that ma y result from
accidents or operation under abnormal conditions.

3. Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4. Turbo IC products are not authorized for use in life support systems or other critical systems
where component failure may endanger life. System designers should design with error
detection and correction, redundancy and backup features.

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: [phone] Fax: [phone]

See us at www.turbo-ic.com

Part Numbers & Order Information

TU24C64CP3

Revision C

8K X 8

Serial
EEPROM

Package

P -PDIP

S -SOIC

Voltage

3 - 2.7 to 5.5 V

Rev . 5.0 - 11/27/02