Datasheet TU24C256SI-2.7, TU24C256SI, TU24C256SC-2.7, TU24C256SC, TU24C256PI-2.7 Datasheet (TURBO IC)

CMOS I²C 2-WIRE BUS

128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

16K/32K X 8 BIT EEPROM

Turbo IC, Inc.

24C128/24C256

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C128/24C256. The
pin is an open-drain output. A pull-up resistor

WRITE PROTECT (WP)

When the write protect input is connected to Vcc,
the entire memory is protected against write op­erations. For normal write operation, the write
protect pin should be grounded. When this pin is
left unconnected, WP is interpreted as zero.

PIN DESCRIPTION

DEVICE ADDRESSES (A2-A0)

The address inputs are used to define the 3 least
significant bits of the 7-bit device address code ­1010 (A2) (A1) (A0). These pins can be con­nected either high or low. A maximum of eight
Turbo IC 24C128/24C256 can be connected in
parallel, each with a unique device address. When
these pins are left unconnected, the device ad­dresses are interpreted as zero.

must be connected from SDA to Vcc.
SERIAL CLOCK (SCL)

The SCL input synchronizes the data on the SD A
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C128/24C256.

1
2
3
4

5

6

7

8

A0
A1
A2

GND

VCC
WP
SCL
SDA

8 pin PDIP

1
2
3
4

5

6

7

8

A0
A1
A2

GND

VCC
WP
SCL
SDA

8 pin SOIC

PIN DESCRIPTION

DESCRIPTION:

The Turbo IC 24C128/24C256 is a serial 128K/256K
EEPROM fabricated with Turbo’s proprietary, high reliabil­ity, high performance CMOS technology. It’s 128K/256K of
memory is organized as 16384/32768 x 8 bits. The memory
is configured as 256/512 pages with each page containing
64 bytes. This device offers significant advantages in low
power and low voltage applications .

The Turbo IC 24C128/24C256 uses the extended I²C ad­dressing protocol and 2-wire serial interface which includes
a bidirectional serial data bus synchronized by a clock. It
offers a flexible byte write and a faster 64-byte page write.
The entire memory can be protected by the write protect
pin.

The Turbo IC 24C128/24C256 is assembled in either a 8­pin PDIP or 8-pin SOIC package. Pin #1 (A0), #2 (A1), and
#3 (A2) are device address input pins which are hardwired
by the user. Pin #4 is the ground (Vss). Pin #5 is the serial
data (SDA) pin used f or bidirectional transfer of data. Pin #6
is the serial clock (SCL) input pin. Pin #7 is the write protect
(WP) input pin, and Pin #8 is the power supply (Vcc) pin.

All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C128/24C256 (slave) for a
read or write operation, the controller (master) issues a start
condition by pulling SDA from high to lo w while SCL is high.
The master then issues the device address byte which con­sists of 1010 (A2) (A1) (A0) (R/W). The 4 most significant
bits (1010) are a device type code signifying an EEPROM
device. The A[2:0] bits represent the input levels on the 3
device address input pins. The read/write bit determines
whether to do a read or write operation. After each byte is
transmitted, the receiver has to provide an ac knowledge by
pulling the SDA bus low on the ninth clock cycle. The ac­knowledge is a handshake signal to the transmitter indicat­ing a successful data transmission.

FEA TURES :

• Extended Pow er Supply Voltage
Single Vcc f or Read and Prog ramming
(Vcc = 2.7 V to 5.5 V)(Vcc = 4.5V to 5.5V)

• Low P o w er (Isb = 2µa @ 5.5 V)

• Extended I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (64 Bytes)

• Automatic P age write Operation (maxim um 10 ms)
Internal Control Timer
Internal Data Latches for 64 Bytes

• Hardware Data Protection by Write Protect Pin

• High Reliability CMOS Technology

EEPROM Cell

Endurance : 100,000 Cycles
Data Retention : 100 Years

• 8 pin JDEC 300 mil wide PDIP AND 8 pin 150 mil wide

SOIC packages

1

PRODUCT PRELIMINAR Y

DESCRIPTION (Continued)

For a write operation, the master issues a start condition,
device address byte, 2 memory address bytes, and then up
to 64 data bytes. The T urbo IC 24C128/24C256 ac knowledges
after each byte transmission. To terminate the transmission,
the master issues a stop condition by pulling SDA from low
to high while SCL is high.

For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C128/24C256 ac­knowledges, and then transmits a data byte, which is ac­cessed from the EEPROM memory. The master acknowl­edges, indicating that it requires more data bytes. The Turbo
IC 24C128/24C256 transmits more data bytes, with the
memory address counter automatically incrementing for each
data byte, until the master does not ackno wledge, indicating
that it is terminating the transmission. The master then is­sues a stop condition.

DEVICE OPERA TION:

BIDIRECTIONAL BUS PROTOCOL:

The Turbo IC 24C128/24C256 follows the extended I²C b us
protocol. The protocol defines any device that sends data
onto the SDA bus as a tr ansmitter, and the receiving device
as a receiver. The de vice controlling the transf er is the mas­ter and the device being controlled is the slave. The master
always initiates the data transf ers, and provides the clock f or
both transmit and receive operations. The Turbo IC 24C128/
24C256 acts as a slave device in all applications . Either the
master or the slave can take control of the SDA bus, de­pending on the requirement of the protocol.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SD A
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA b us is recognized as a STOP con­dition which terminates the communication and places the
Turbo IC 24C128/24C256 into standb y mode. All other data
transitions on the SDA bus must occur while SCL clock is
low to ensure proper operation.

ACKNO WLEDGE:

All data is serially transmitted in bytes (8 bits) on the SDA
bus. The ac knowledge protocol is used as a handshake sig­nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C128/24C256), releases the bus after sending a byte of
data on the SDA bus. The receiver pulls the SDA bus low
during the ninth clock cycle to acknowledge the successful
transmission of a byte of data. If the SDA is not pulled low
during the ninth clock cycle, the Turbo IC 24C128/24C256
terminates the data transmission and goes into standby mode.

For the write operation, the Turbo IC 24C128/24C256 ac­knowledges after the device address byte, acknowledges
after each memory address byte, and acknowledges after
each subsequent data byte.

For the read operation, the Turbo IC 24C128/24C256 ac­knowledges after the device address byte . Then the Turbo IC
24C128/24C256 transmits each subsequent data byte, and
the master acknowledges after each data byte tr ansfer , indi­cating that it requires more data bytes. The Turbo IC 24C128/
24C256 monitors the SDA bus for the acknowledge. To ter­minate the transmission, the master does not acknowledge,
and then sends a stop condition.

Write Cycle Timing

Note: The write cycle time t

WC

is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

SCL

SDA

WORD n

8th BIT ACK

STOP

CONDITION

START

CONDITION

t

WC

Turbo IC, Inc.

2

24C128/24C256

PRODUCT PRELIMINAR Y

Data Valid

Turbo IC, Inc.

Output Acknowledge

Start and Stop Definition

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

SDA

SCL

START

STOP

SCL

DATA IN

DATA OUT

189

ACKNOWLEDGESTART

3

24C128/24C256

PRODUCT PRELIMINAR Y

DEVICE ADDRESSING:

Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac­cess the selected Turbo IC 24C128/24C256 for a read or
write operation. The A[2:0] bits must match with the address
input pins of the selected Turbo IC 24C128/24C256. If there
is a match, the selected Turbo IC 24C128/24C256 acknowl­edges during the ninth clock cycle by pulling the SDA bus
low . If there is no match, the Turbo IC 24C128/24C256 does
not acknowledge during the ninth clock cycle and goes into
standby mode. The (R/W) bit is a high (1) f or read and low (0)
for write.

DATA INPUT DURING WRITE OPERATION:

During the write operation, the Turbo IC 24C128/24C256
latches the SDA bus signal on the rising edge of the SCL
clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, the Turbo IC 24C128/24C256 se­rially shifts the data onto the SDA bus on the f alling edge of
the SCL clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2
memory address bytes. The memory address bytes can only
be sent as part of a write operation. The most significant
address byte B(14) B(13) (B12) (B11) (B10) (B9) (B8) is sent
first, where B(14) is a “don’t care” bit in the 24C128. Then the
least significant address byte (B7) (B6) (B5) (B4) (B3) (B2)
(B1) (B0) is sent last.

BYTE WRITE OPERA TION:

The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol­lowed by one data byte, then a stop condition. After each
byte transfer, the Turbo IC 24C128/24C256 acknowledges
the successful data transmission by pulling the SDA b us low .
The stop condition starts the internal EEPROM write cycle,
and all inputs are disabled until the completion of the write
cycle. If the WP pin is high, then the stop condition does not
start the internal write cycle and the Turbo IC 24C128/24C256
is immediately ready for the next command.

P AGE WRITE OPERATION:

The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol­lowed by up to 64 data bytes, then a stop condition. After
each byte transfer, the Turbo IC 24C128/24C256 acknowl­edges the successful data transmission by pulling SD A low.
After each data byte transfer, the

memory address counter is automatically incremented by
one. The stop condition starts the internal EEPROM write
cycle only if the stop condition occurs in the clock cycle im­mediately following the acknowledge (10th clock cycle). All
inputs are disabled until the completion of the write cycle. If
the WP pin is high (1), then the stop condition does not start
the internal write cycle, and the Turbo IC 24C128/24C256 is
immediately ready for the next command.

POLLING ACKNO WLEDGE:

During the internal write cycle of a write operation in the Turbo
IC 24C128/24C256, the completion of the write cycle can be
detected by polling acknowledge. The master starts acknowl­edge polling by issuing a start condition, then followed by the
device address byte 1010 (A2) (A1) (A0) 0. If the internal
write cycle is finished, the Turbo IC 24C128/24C256 acknowl­edges by pulling the SDA b us low . If the internal write cycle is
still ongoing, the Turbo IC 24C128/24C256 does not acknowl­edge because it’s inputs are disab led. Theref ore, the de vice
will not respond to any command. By using polling ackno wl­edge, the system delay f or write operations can be reduced.
Otherwise, the system needs to wait for the maxim um inter­nal write cycle time, tWC, given in the spec.

POWER ON RESET :

The Turbo IC 24C128/24C256 has a Power On Reset circuit
(POR) to prevent data corruption and accidental write op­erations during power up. On power up, the internal reset
signal is on and the Turbo IC 24C128/24C256 will not re­spond to any command until the VCC voltage has reached
the POR threshold value.

Turbo IC, Inc.

4

24C128/24C256

PRODUCT PRELIMINAR Y

Turbo IC, Inc.

Device Address

1010A2A1A0R/W

MSB LSB

* = Don't care bits
! = Don't care bit for 24C128

Page Write

Byte Write

5

24C128/24C256

PRODUCT PRELIMINAR Y

SDA LINE

DEVICE
ADDRESS

FIRST
WORD ADDRESS

SECOND
WORD ADDRESS

DATA

S
T
O
P

A
C
K

A
C
K

L
S
B

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W
R

I
T
E

M
S
B

128K

* !

M
S
B

256K

SDA LINE

DEVICE
ADDRESS

FIRST
WORD ADDRESS (n)

SECOND
WORD ADDRESS (n)

DATA (n)

S
T
O
P

A
C
K

A
C
K

L
S
B

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W

R

I
T
E

* !

M
S
B

256K

A
C
K

//
//

DATA (n + x)

M

S
B

128K

Turbo IC, Inc.

Random Read

Current Address Read

CURRENT ADDRESS READ:

The internal memory address counter of the T urbo IC 24C128/
24C256 contains the last memory address accessed during
the previous read or write operation, incremented by one. To
start the current address read operation, the master issues
a start condition, followed by the device address byte 1010
(A2) (A1) (A0) 1. The Turbo IC 24C128/24C256 responds
with an acknowledge by pulling the SDA bus low, and then
serially shifts out the data byte accessed from memory at
the location corresponding to the memory address counter.
The master does not acknowledge, then sends a stop condi­tion to terminate the read operation. It is noted that the
memory address counter is incremented by one after the
data byte is shifted out.

RANDOM ADDRESS READ:

The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed by the 2 memory ad­dress bytes. Following the acknowledge from the Turbo IC
24C128/24C256, the master starts the current read opera­tion by issuing a start condition, followed by the device ad­dress byte 1010 (A2) (A1) (A0) 1. The Turbo IC 24C128/
24C256 responds with

an acknowledge by pulling the SDA bus low, and then seri­ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.

SEQUENTIAL READ:

The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C128/
24C256 serially shifts out the first data byte, the master ac­knowledges by pulling the SD A bus lo w, indicating that it re­quires additional data bytes. After the data byte is shifted
out, the Turbo IC 24C128/24C256 increments the memory
address counter by one. Then the Turbo IC 24C128/24C256
shifts out the next data byte. The sequential reads continues
for as long as the master keeps acknowledging. When the
memory address counter is at the last memory location, the
counter will ‘roll-over’ when incremented by one to the first
location in memory (address zero). The master terminates
the sequential read operation by not acknowledging, then
sends a stop condition.

SDA LINE

DEVICE
ADDRESS

S
T
O
P

N
O

A
C
K

M

S
B

L
S
B

R

/

W

A
C
K

S
T
A

R

T

R
E
A
D

M
S
B

DATA

6

24C128/24C256

PRODUCT PRELIMINAR Y

SDA LINE

DEVICE
ADDRESS

DATA n

S

T
O
P

N
O

A
C
K

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W
R

I
T
E

//

//

R
E
A
D

DEVICE

ADDRESS

WORD

ADDRESS N

DUMMY WRITE

*

!

S
T
A
R
T

Turbo IC, Inc.

D.C. CHARA CTERISTICS

Symbol Parameter Condition Min Max Units

I

cc1

Active Vcc Current READ at 100 KHZ 0.4 1.0 MA

I

cc2

Active Vcc Current WRITE at 100 KHZ 2.0 3.0 MA

I

sb1

Standby Current Vcc = 2.7 v 0.5 uA

Vcc = 5.5 v 2.0 uA

I

sb2

Standby Current Vcc = 4.5 v 20.0 uA

Vcc = 5.5 v 35.0 uA

I

li

Input Leakage Current Vin=Vcc Max 3 uA

I

lo

Output Leakage Current 3 uA

V

il

Input Low Voltage -1.0 V

V

ih

Input High Voltage Vcc+0.5 V

V

ol2

Output Low Vcc=3.0v Iol=2.1 mA 0.4 V

V

ol1

Output Low Vcc=2.7v Iol=-0.15 mA 0.25 V

Sequential Read

SDA LINE

DEVICE
ADDRESS

DATA n

DATA n +1

DATA n + 2

S
T
O
P

A
C
K

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

R
E
A
D

N
O

A
C
K

DATA n + 3

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation sec­tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS
TEMPERATURE

Storage: -65° C to 150° C
Under Bias: -55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

RECOMMENDED OPERATING CONDITIONS
Temperature Range: Commercial: 0° C to 70° C

Industrial: -40° C to 85° C

Vcc Supply Voltage: 2.7 to 5.5 Volts

4.5 to 5.5 Volts

Endurance: 100,000 Cycles/Byte (Typical)
Data Retention: 100 Y ears

7

24C128/24C256

PRODUCT PRELIMINAR Y

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: [phone] Fax: [phone]

See us at www.turbo-ic.com

Rev. 2.0 - 10/28/01

TURBO IC PRODUCTS AND DOCUMENTS

1. All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.

2. Turbo IC does not assume an y responsibility f or an y damage to the user that ma y result from
accidents or operation under abnormal conditions.

3. Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4. Turbo IC products are not authorized for use in life support systems or other critical systems
where component failure may endanger life. System designers should design with error
detection and correction, redundancy and backup features.

Turbo IC, Inc.

t

SU.STA t

HD.STA

t

F

t

LOW

t

HIGH

t

LOW

t

HD.DAT

t

SU.DAT

t

R

t

SU.STO

t

BUF

t

DH

t

AA

SCL

SDA IN

SDA OUT

Bus Timing

Part Numbers & Order Inf ormation

TU24C128/256PC-2.7

Operating Voltage
blank 4.5 to 5.5 V

-2.7 2.7 to 5.5 V

Temperature
C -Commercial
I -Industrial

Package

P -PDIP

S -SOIC

16/32K X 8

Serial
EEPROM

A.C. CHARA CTERISTICS

Symbol Parameter 2.7 volt 5.5 volt Units

Min Max Min Max

SCL SCL Cloc k Frequency 400 1000 kHZ
t

LOW

Clock Low Period 1.2 0.6 us

t

HIGH

Clock High Period 0.6 0.4 us

t

AA

SCL Low to SDA Data Out 0.9 0.55 us

t

BUF

Bus Free to New Start (1) 1.2 0.5 us

t

HD.STA

Start Hold Time 0.6 0.25 us

t

SU.STA

Start Setup Time 0.6 0.25 us

t

HD.D AT

Data-in Hold Time 0 0 us

t

SU.D AT

Data-in Set-up Time 100 100 ns

t

R

SCL and SDA Rise Time (1) 0.3 0.3 us

t

F

SCL and SDA F all Time (1) 300 100 ns

t

SU.ST O

Stop Setup Time 0.6 0.25 us

t

DH

Data-out Hold Time 50 50 ns

t

WC

Write Cycle Time 10 10 ms

Note: 1 This parameter is characterized and not 100% tested.

24C128/24C256

PRODUCT PRELIMINAR Y