Datasheet TU24C01BP3, TU24C01BP, TU24C02BSI, TU24C02BS3I, TU24C02BS3 Datasheet (TURBO IC)

CMOS I²C 2-WIRE BUS

1K/2K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

128/256 X 8 BIT EEPROM

Turbo IC, Inc.

24C01/24C02

PRODUCT INTRODUCTION

PIN DESCRIPTION

DESCRIPTION:

The Turbo IC 24C01/24C02 is a serial 1K/2K EEPROM
fabricated with Turbo’s proprietary , high reliability, high per­formance CMOS technology . It’s 1K/2K of memory is orga­nized as 128/256 x 8 bits. The memory is configured as 16/
32 pages with each page containing 8 bytes. This device
offers significant advantages in lo w power applications.

The Turbo IC 24C01/24C02 uses the I²C addressing proto­col and 2-wire serial interface which includes a bidirec­tional serial data bus synchronized by a clock. It offers a
flexible b yte write and a faster 8-b yte page write.

The Turbo IC 24C01/24C02 is assembled in either a 8-pin
PDIP or 8-pin SOIC package. Pin #1 is the A0 device ad­dress input for the device . Pin #2 is the A1 device address
input for the de vice. Pin #3 is the A2 device address input
for the device, such that a total of eight 24C01/24C02 de­vices can be connected on a single bus. Pin #4 is the ground
(Vss). Pin #5 is the serial data (SDA) pin used for bidirec­tional transfer of data. Pin #6 is the serial cloc k (SCL) input
pin. Pin #7 is the write protect (WP) pin used to protect hard­ware data. Pin #8 is the po wer supply (Vcc) pin.

All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C01/24C02 (slave) for a read
or write operation, the controller (master) issues a start con­dition by pulling SDA from high to lo w while SCL is high. The
master then issues the device address byte which consists
of 1010 (A2) (A1) (A0) (R/W). The most significant bits (1010)
are a device type code signifying an EEPROM device. A0,
A1, and A2 are the device address select bits which has to
match the A0, A1, and A2 pin inputs on the device. The B[7]
bit (or B[6] bit in the 24C01) is the most significant bit of the
memory address. The read/write bit determines whether to
do a read or write operation. After each b yte is transmitted,
the receiver has to provide an acknowledge by pulling the
SDA bus lo w on the ninth clock cycle. The acknowledge is a
handshake signal to the transmitter indicating a successful
data transmission.

FEA TURES :

• Power Supply V oltage
Single Vcc f or Read and Prog ramming
(Vcc = 2.7 V to 5.5 V)

• Low P o w er (Isb = 2µa @ 5.5 V)

• I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (8 Bytes)

• Automatic P age write Operation (maxim um 10 ms)
Internal Control Timer
Internal Data Latches for 8 Bytes

• High Reliability CMOS Technology with EEPROM Cell
Endurance : 1,000,000 Cycles

Data Retention : 100 Years

1

SERIAL CLOCK (SCL)

The SCL input synchronizes the data on the SD A
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C01/24C02.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C01/24C02. The pin
is an open-drain output. A pullup resistor must
be connected from SDA to Vcc.

PIN DESCRIPTION

DEVICE ADDRESS (A0 & A1 & A2)

A0, A1, and A2 are device address inputs that
enables a total of eight 24C01/24C02 devices to
connect on a single bus. If the address input pin
is left unconnected, it is interpreted as zero.

WRITE PROTECT (WP)

When the write protect input is connected to Vcc,
the entire memory array is protected against write
operations. F or normal write operations, the write
protect pin should be grounded. When the pin is
left unconnected, WP is interpreted as zero.

1
2
3
4

5

6

7

8

A0
A1
A2

GND

VCC
WP
SCL
SDA

8 pin PDIP

1
2
3
4

5

6

7

8

A0
A1
A2

GND

VCC
WP
SCL
SDA

8 pin SOIC

24C01/24C02

PRODUCT INTRODUCTION

Turbo IC, Inc.

Note: The write cycle time t

WC

is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

DESCRIPTION (Continued):

For a write operation, the master issues a start condition, a
device address byte, a memory address byte, and then up to
8 data bytes. The Turbo IC 24C01/24C02 acknowledges
after each byte transmission. To terminate the transmission,
the master issues a stop condition by pulling SDA from low
to high while SCL is high.

For a read operation, the master issues a start condition and
a device address byte . The Turbo IC 24C01/24C02 acknowl­edges, and then transmits a data byte, which is accessed
from the EEPROM memory . The master ac knowledges, indi­cating that it requires more data bytes. The Turbo IC 24C01/
24C02 transmits more data bytes, with the memory address
counter automatically incrementing for each data byte , until
the master does not acknowledge, indicating that it is termi­nating the transmission. The master then issues a stop con­dition.

DEVICE OPERA TION:

BIDIRECTIONAL BUS PROTOCOL:

The Turbo IC 24C01/24C02 follows the I²C bus protocol. The
protocol defines any device that sends data onto the SDA
bus as a transmitter , and the receiving de vice as a receiver.
The device controlling the transfer is the master and the de­vice being controlled is the slave. The master always initiates
the data transfers, and provides the clock for both transmit
and receive operations. The Turbo IC 24C01/24C02 acts as
a slave device in all applications. Either the master or the
slave can take control of the SDA bus, depending on the
requirement of the protocol.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SD A
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA b us is recognized as a STOP con­dition which terminates the communication and places the
Turbo IC 24C01/24C02 into standby mode. All other data
transitions on the SDA bus must occur while SCL clock is
low to ensure proper operation.

ACKNO WLEDGE:

All data is serially transmitted in bytes (8 bits) on the SDA
bus. The ac knowledge protocol is used as a handshake sig­nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C01/24C02), releases the bus after sending a byte of data
on the SDA bus. The receiver pulls the SDA bus low during
the ninth clock cycle to acknowledge the successful trans­mission of a byte of data. If the SD A is not pulled lo w during
the ninth clock cycle, the Turbo IC 24C01/24C02 terminates
the data transmission and goes into standby mode.

For the write operation, the T urbo IC 24C01/24C02 ac knowl­edges after the device address byte, ac knowledges after the
memory address byte, and acknowledges after each subse­quent data byte.

For the read operation, the Turbo IC 24C01/24C02 acknowl­edges after the device address byte. Then the Turbo IC 24C01/
24C02 transmits each subsequent data byte, and the mas­ter acknowledges after each data byte transfer, indicating
that it requires more data bytes. The Turbo IC 24C01/24C02
monitors the SDA bus f or the acknowledge. T o terminate the
transmission, the master does not acknowledge, and then
sends a stop condition.

Write Cycle Timing

2

24C01/24C02

PRODUCT INTRODUCTION

Data Valid

Turbo IC, Inc.

Start and Stop Definition

Output Acknowledge

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

SDA

SCL

START

STOP

SCL

DATA IN

DATA OUT

189

ACKNOWLEDGESTART

3

24C01/24C02

PRODUCT INTRODUCTION

Turbo IC, Inc.

DEVICE ADDRESSING:

Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac­cess the selected Turbo IC 24C01/24C02 for a read or write
operation. A0, A1, and A2 are the device address select bits
which have to match the A0, A1, and A2 pin inputs on the
24C01/24C02 device. The B[7] bit (B[6] bit in the 24C01) is
the most significant bit of the memory address. The (R/W)
bit is a high (1) for read and low (0) for write. If A0, A1, or
A2 are left unconnected, the Turbo IC 24C01/24C02 device
shall interpret as Vil input(s).

DATA INPUT DURING WRITE OPERA TION:

During the write operation, the Turbo IC 24C01/24C02 latches
the SDA bus signal on the rising edge of the SCL clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, the Turbo IC 24C01/24C02 seri­ally shifts the data onto the SDA bus on the falling edge of
the SCL clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2
bytes. De vice address A2, A1, and A0 is included in the first
byte. The remaining memory address bits B[7:0] are included
in the second byte of the device address of the 24C02. The
memory address byte can only be sent as part of a wr ite
operation. On the other hand, in the 24C01, the first b yte is
the same as in the 24C02; how e ver, the second byte of the
24C01 contains remaining address bits B[6:0]. The B[7] bit
in the 24C01 is treated as a 'don't care' bit.

BYTE WRITE OPERA TION:

The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed b y the memory address byte, fol­lowed by one data byte, f ollow ed by an ackno wledge, then a
stop condition. After each b yte transfer , the Turbo IC 24C01/
24C02 acknowledges the successful data transmission by
pulling the SDA bus lo w. The stop condition starts the inter­nal EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle.

4

P AGE WRITE OPERATION:

The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed b y the memory address byte, fol­lowed by up to 8 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo IC
24C01/24C02 acknowledges the successful data transmis­sion by pulling SDA low. After each data byte transfer, the
memory address counter is automatically incremented by
one. The stop condition starts the internal EEPROM write
cycle only if the stop condition occurs in the clock cycle im­mediately following the acknowledge (10th clock cycle). All
inputs are disabled until the completion of the write cycle.

POLLING ACKNO WLEDGE:

During the internal write cycle of a write operation in the Turbo
IC 24C01/24C02, the completion of the write cycle can be
detected by polling acknowledge. The master starts acknowl­edge polling by issuing a start condition, then followed by the
device address byte 1010 (A2) (A1) (A0) 0. If the internal
write cycle is finished, the Turbo IC 24C01/24C02 acknowl­edges by pulling the SDA b us low . If the internal write cycle is
still ongoing, the Turbo IC 24C01/24C02 does not acknowl­edge because it’s inputs are disab led. Therefore, the de vice
will not respond to any command. By using polling ackno wl­edge, the system delay f or write operations can be reduced.
Otherwise, the system needs to wait for the maxim um inter­nal write cycle time, tWC, given in the spec.

POWER ON RESET :

The Turbo IC 24C01/24C02 has a Power On Reset circuit
(POR) to prevent data corruption and accidental write op­erations during power up. On power up, the internal reset
signal is on and the Turbo IC 24C01/24C02 will not respond
to any command until the VCC v oltage has reached the POR
threshold value.

24C01/24C02

PRODUCT INTRODUCTION

Turbo IC, Inc.

Device Address

Byte Write

SDA LINE

DEVICE
ADDRESS

WORD ADDRESS

DATA

S
T
O
P

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W
R

I
T
E

Page Write

SDA LINE

DEVICE
ADDRESS

WORD ADDRESS

DATA (n)

S
T
O
P

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W
R

I
T
E

A
C
K

//
//

DATA (n + x)

5

24C01/24C02

Turbo IC, Inc.

Random Read

CURRENT ADDRESS READ:

The internal memory address counter of the Turbo IC 24C01/
24C02 contains the last memory address accessed during
the previous read or write operation, incremented by one. To
start the current address read operation, the master issues
a start condition, followed by the device address byte 1010
(A2) (A1) (A0) 1. The Turbo IC 24C01/24C02 responds with
an acknowledge by pulling the SDA bus low, and then seri­ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.

RANDOM ADDRESS READ:

The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed b y the memory address
bytes. F ollo wing the ackno wledge from the Turbo IC 24C01/
24C02, the master starts the current read operation by issu­ing a start condition, followed by the device address byte
1010 (A2) (A1) (A0) 1. The Turbo IC 24C01/24C02 responds
with

an acknowledge by pulling the SDA bus low, and then seri­ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.

SEQUENTIAL READ:

The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C01/
24C02 serially shifts out the first data byte, the master ac­knowledges by pulling the SD A bus lo w, indicating that it re­quires additional data bytes. After the data byte is shifted
out, the Turbo IC 24C01/24C02 increments the memory ad­dress counter by one. Then the Turbo IC 24C01/24C02 shifts
out the next data byte. The sequential reads continues f or as
long as the master keeps ackno wledging. When the memory
address counter is at the last memory location, the counter
will ‘roll-o ver’ when incremented by one to the first location in
memory (address zero). The master terminates the sequen­tial read operation by not acknowledging, then sends a stop
condition.

Current Address Read

SDA LINE

DEVICE
ADDRESS

S
T
O
P

N
O

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A

R

T

R
E
A
D

DATA

PRODUCT INTRODUCTION

6

SDA LINE

DEVICE
ADDRESS

DATA n

S
T
O
P

N
O

A
C
K

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

W
R

I
T
E

//

//

R
E
A
D

DEVICE

ADDRESS

WORD

ADDRESS N

DUMMY WRITE

24C01/24C02

Turbo IC, Inc.

Sequential Read

SDA LINE

DEVICE
ADDRESS

DATA n

DATA n +1

DATA n + 2

S
T
O
P

A
C
K

A
C
K

A
C
K

M
S
B

L
S
B

R

/

W

A
C
K

S
T
A
R
T

R
E
A
D

N
O

A
C
K

DATA n + 3

D.C. CHARA CTERISTICS

Symbol Parameter Condition Min Max Units

I

cc1

Active Vcc Current READ at 100 KHZ 1.0 MA

I

cc2

Active Vcc Current WRITE at 100 KHZ 3.0 MA

I

sb1

Standby Current Vcc = 4.5 v 2.0 uA

Vcc = 5.5 v 2.0 uA

I

il

Input Leakage Current Vin=Vcc Max 3 uA

I

ol

Output Leakage Current 3 uA

V

il

Input Low V oltage -1.0 0.8 V

V

ih

Input High Voltage Vccx0.7 Vcc+0.5 V

V

ol1

Output Low Vcc=4.5v Iol=2.1 mA 0.4 V

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation sec­tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

TEMPERATURE

Storage: -65° C to 150° C
Under Bias: -55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

RECOMMENDED OPERATING CONDITIONS
Temperature Range: Commercial: 0° C to 70° C

Industrial: -40° C to 85° C
Military: -55° C to 125° C

Vcc Supply Voltage: 2.7 to 5.5 Volts
Endurance: 1,000,000 Cycles/Byte

Data Retention: 100 Y ears

PRODUCT INTRODUCTION

ABSOLUTE MAXIMUM RATINGS

7

24C01/24C02

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: [phone] Fax: [phone]

See us at www.turbo-ic.com

Rev . 4.0-10/28/01

TURBO IC PRODUCTS AND DOCUMENTS

1. All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.

2. Turbo IC does not assume an y responsibility f or an y damage to the user that ma y result from
accidents or operation under abnormal conditions.

3. Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4. Turbo IC products are not authorized for use in life support systems or other critical systems
where component failure may endanger life. System designers should design with error
detection and correction, redundancy and back-up features.

Turbo IC, Inc.

Bus Timing

t

SU.STA t

HD.STA

t

F

t

LOW

t

HIGH

t

LOW

t

HD.DAT

t

SU.DAT

t

R

t

SU.STO

t

BUF

t

DH

t

AA

SCL

SDA IN

SDA OUT

Part Numbers & Order Information

TU24C02BS3I

T emperature

-Commercial

I -Industrial

Package

P -PDIP

S -SOIC

PRODUCT INTRODUCTION

A.C. CHARA CTERISTICS

Symbol Parameter 2.7 volt 5.5 volt

Min Max Min Max Units

SCL SCL Clock F requency 10 0 40 0 kHZ
T Noise Suppression Time (1) 10 0 50 ns
t

LOW

Clock Low Period 4.7 1.2 us

t

HIGH

Clock High Period 4.0 0.6 us

t

AA

SCL Low to SDA Data Out 0.1 4.5 0.1 0.9 us

t

BUF

Bus Free to Ne w Start (1) 4.7 1. 2 us

t

HD.STA

Start Hold Time 4.0 0. 6 us

t

SU.STA

Start Set-up Time 4.7 0.6 u s

t

HD.DAT

Data-in Hold Time 0 0 us

t

SU.DAT

Data-in Set-up Time 20 0 100 ns

t

R

SCL and SDA Rise Time (1) 1. 0 0.3 us

t

F

SCL and SDA F all Time (1) 30 0 3 00 ns

t

SU.STO

Stop Set-up Time 4.7 0.6 u s

t

DH

Data-out Hold Time 10 0 50 ns

t

WC

Write Cycle Time 10 1 0 ms

Note: 1 This parameter is characterized and not 100% tested.

256 X 8

Serial
EEPROM

V oltage

3 - 2.7V to 5.5V

- 4.5V to 5.5 V

2nd generation