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TSL210
Datasheet (TAOS)
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Datasheet TSL210 Datasheet (TAOS)

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Page 1
TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
640 × 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range...2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply
Description
The TSL210 linear sensor array consists of five sections of 128 photodiodes, each with associated charge amplifier circuitry , running from a common clock. These sections can be connected to form a contiguous 640 × 1 pixel array. Device pixels measure 120 µm (H) by 70 µm (W) with 125-µm center-to-center pixel spacing. Operation is simplified by internal logic that requires only a serial input (SI1 through SI5) for each section and a common clock for the five sections.
The device is intended for use in a wide variety of applications including contact imaging, mark and code reading, bar-code reading, edge detection and positioning, OCR, level detection, and linear and rotational encoding.
PACKAGE
(TOP VIEW)
1 V
DD
2 CLK 3 SI1 4 AO1 5 SO1 6 SI2 7 AO2 8 SO2 9 GND 10 SI3 11 AO3 12 SO3 13 SI4 14 AO4 15 SO4 16 SI5 17 AO5 18 SO5
Functional Block Diagram (each section)
Pixel 1
Integrator
Reset
_ +
Sample/
Output
Switch Control Logic
CLK 128-Bit Shift Register
SI
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Pixel
2
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759
www.taosinc.com
Pixel
3
Q3Q2Q1
Q128
Pixel
128
Analog
Bus
Output Amplifier
Gain Trim
V
DD
AO
R
L
(External
GND
330 Load)
SO
1
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
Terminal Functions
TERMINAL
NAME NO.
AO1 4 O Analog output of section 1. AO2 7 O Analog output of section 2. AO3 11 O Analog output of section 3. AO4 14 O Analog output of section 4. AO5 17 O Analog output of section 5. CLK 2 I Clock input for all sections. The clock controls the charge transfer, pixel output, and reset. GND 9 Ground (substrate). All voltages are referenced to the substrate. SI1 3 I SI1 defines the start of the data out sequence for section 1. SI2 6 I SI2 defines the start of the data out sequence for section 2. SI3 10 I SI3 defines the start of the data out sequence for section 3. SI4 13 I SI4 defines the start of the data out sequence for section 4. SI5 16 I SI5 defines the start of the data out sequence for section 5. SO1 5 O SO1 provides the signal to drive the SI2 input in serial mode or SO2 8 O SO2 provides the signal to drive the SI3 input in serial mode or SO3 12 O SO3 provides the signal to drive the SI4 input in serial mode or SO4 15 O SO4 provides the signal to drive the SI5 input in serial mode or SO5 18 O SO5 provides the signal to drive the SI input of another device for cascading or as an VDD 1 Supply voltage for both analog and digital circuits.
I/O DESCRIPTION
end of data end of data end of data end of data
for section 1 in parallel mode. for section 2 in parallel mode. for section 3 in parallel mode. for section 4 in parallel mode.
end of data
indication.
Detailed Description
The device consists of five sections of 128 photodiodes (called pixels — 640 total in the device) arranged in a linear array. Each section has its own signal input and output lines, and all five sections are connected to a common clock line. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The voltage output developed for each pixel is according to the following relationship:
V
= V
where:
out
V
out
V
drk
R E
e
t
int
is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(µJ/cm2)
e
is the incident irradiance in µW/cm is integration time in seconds
+ (Re) (Ee) (t
drk
2
)
int
2
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is then reset, and the next integration period begins for that pixel. On the 129th clock rising edge, the SO pulse is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The SO of each section can be connected to SI on the next section in the array (Figure 4). SO can be used to signify the read is complete.
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state.
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
Absolute Maximum Ratings
†
Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high impedance or
power-off state, VO –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(V
= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VDD or GND –100 mA to 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature on connection pad for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Wavelength of light source, λ 400 1000 nm Clock frequency, f Sensor integration time, serial, t Sensor integration time, parallel, t Load capacitance, C Load resistance, R Operating free-air temperature, T
NOTE 1: SI must go low before the rising edge of the next clock pulse.
DD
I
IH
IL
clock
int
int
L
L
A
4.5 5 5.5 V 0 V 2 V 0 0.8 V
5 5000 kHz
0.128 100 ms
0.026 100 ms
300 4700 Ω
0 70 °C
DD DD
330 pF
V V
4
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
Electrical Characteristics at f R
= 330 Ω, Ee = 18µW/cm2 (unless otherwise noted) (see Note 3)
L
= 200 kHz, VDD = 5 V, TA = 25°C, λp = 640 nm, t
clock
= 5 ms,
int
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V V
Analog output voltage (white, average over 640 pixels) See Note 2 1.6 2 2.4 V
OUT
Analog output voltage (dark, average over 640 pixels) Ee = 0 0 0.05 0.15 V
DRK
PRNU Pixel response nonuniformity See Note 4 ±20 %
Nonlinearity of analog output voltage See Note 5 ±0.4% FS Output noise voltage See Note 6 1 mVrms
R
Responsivity 16 22 28
e
cm2) SE Saturation exposure See Note 7 155 nJ/cm V DSNU Dark signal nonuniformity All pixels, E
Analog output saturation voltage 2.5 3.4 V
SAT
= 0, See Note 8 0.04 0.12 V
e
IL Image lag See Note 9 0.5 % I
DD
I
IH
I
IL
V
V
C C
Supply current 125 160 mA High-level input current VI = V
DD
Low-level input current VI = 0 10 µA
High-level output voltage, SO1 – SO5
OH
Low-level output voltage, SO1 – SO5
OL
Input capacitance, SI 20 pF
i(SI)
Input capacitance, CLK 50 pF
i(CLK)
p
p
IO = 50 µA 4.5 4.95 IO = 4 mA 4.6 IO = 50 µA 0.01 0.1 IO = 4 mA 0.4
10 µA
NOTES: 2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
3. Clock duty cycle is assumed to be 50%.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Minimum saturation exposure is calculated using the minimum V
, the maximum V
sat
, and the maximum Re.
drk
8. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition:
V/
(µJ/
2
V
V
IL
V
V
out (white)
out (IL)
V
V
drk
Timing Requirements (see Figure 1 and Figure 2)
t
su(SI)
t
h(SI)
t
w
tr, t
NOTES: 10. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
The
Setup time, serial input (see Note 10) 20 ns Hold time, serial input (see Note 10 and Note 11) 0 ns Pulse duration, clock high or low 50 ns Input transition (rise and fall) time 0 500 ns
f
11. SI must go low before the rising edge of the next clock pulse.
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drk
MIN NOM MAX UNIT
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Analog output settling time to ±1% CL = 10 pF 185 ns
s
TYPICAL CHARACTERISTICS
CLK
SI1
CLK
AO
t
su(SI)
SI
AO
129 Clock Cycles
Hi-Z
Figure 1. Timing Waveforms (each section)
t
w
1 2 128 129
50%
t
h(SI)
t
s
Pixel 1
t
s
Figure 2. Operational Waveforms (each section)
Hi-Z
5 V
2.5 V 0 V
5 V
0 V
Pixel 128
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PHOTODIODE SPECTRAL RESPONSIVITY
1
TA = 25°C
0.8
0.6
0.4
Normalized Responsivity
0.2
0 300 500 700 900
λ – Wavelength – nm
TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
TYPICAL CHARACTERISTICS
1100400 600 800 1000
Figure 3
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
APPLICATION INFORMATION
TSL210
SERIAL
1 V
DD
2 CLK 3 SI1 4 AO1 5 SO1 6 SI2 7 AO2 8 SO2 9 GND 10 SI3 11 AO3 12 SO3 13 SI4 14 AO4 15 SO4 16 SI5 17 AO5 18 SO5
R
330 Ω
L
Input
Output
TSL210
1 V
DD
2 CLK 3 SI1 4 AO1 5 SO1 6 SI2 7 AO2 8 SO2 9 GND 10 SI3 11 AO3 12 SO3 13 SI4 14 AO4 15 SO4 16 SI5 17 AO5 18 SO5
PARALLEL
R
L
330 Ω
Input
Output 1
Output 2
Output 3
Output 4
Output 5
Figure 4. Connection Diagrams
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SIDE VIEW
TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
MECHANICAL INFORMATION
TOP VIEW
4.01
3.81
6.15
5.64
SIDE VIEW
CROSS SECTION
1.22
0.97
22.30
21.80
Pixel 1
Cover Glass
Bonded Die
Pin 1
17 2.54
89.92
89.66
47.46
47.20
18
94.125
93.875
Bypass Capacitor
0.69
0.53
0.69
2 2.29
12.95
12.45
Pixel 640
3.30
3.05
NOTES: A. All linear dimensions are in millimeters.
B. Pixel centers are located along the center line of the mounting holes. C. Cover glass index of refraction is 1.52. D. This drawing is subject to change without notice.
Figure 5. TSL210 Mechanical Specifications
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESUL T I N PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
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