Datasheet TSL208R Datasheet (TAOS)

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TSL208R

512  1 LINEAR SENSOR ARRAY

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TAOS031C – OCTOBER 2002

 512 × 1 Sensor-Element Organization
 200 Dots-Per-Inch (DPI) Sensor Pitch

(TOP VIEW)

 High Linearity and Uniformity
 Wide Dynamic Range...2000:1 (66 dB)
 Output Referenced to Ground
 Low Image Lag . . . 0.5% Typ
 Operation to 5 MHz

1

V

 Single 5-V Supply
 Replacement for TSL208

Description

The TSL208R linear sensor array consists of a 512 × 1
array of photodiodes and associated charge amplifier
circuitry. The pixels measure 120 µm (H) by 70 µm (W)
with 125-µm center-to-center spacing and 55-µm
spacing between pixels. Operation is simplified by
internal control logic that requires only a serial-input (SI)
signal and a clock.

The TSL208R is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.

DD

2

SI

3

CLK

4

AO

5

GND

6

SO

7

V

DD

Functional Block Diagram

Pixel 1

_
+

3

CLK 512-Bit Shift Register

2

SI

Integrator

Reset

Sample/

Output

Switch Control Logic

Pixel

2

Pixel

3

1

Pixel

512

Analog

Bus

Q3Q2Q1

Q512

Output
Amplifier

Gain
Trim

R

L

330 

V

AO

GND

SO

DD

4

5

6

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Copyright  2002, TAOS Inc.

1

TSL208R
512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

Terminal Functions

TERMINAL

NAME NO.

AO 4 O Analog output.
CLK 3 I Clock. The clock controls the charge transfer, pixel output and reset.
GND 5 I Ground (substrate). All voltages are referenced to the substrate.
SI 2 I Serial input. SI defines the start of the data out sequence.
SO 6 O Serial output. SO signals the end of the data out sequence.
VDD 1, 7 I Supply voltage for both analog and digital circuits.

I/O DESCRIPTION

Detailed Description

The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse
is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 513th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 513th clock pulse is required to terminate the
output of the 512th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 514th clock pulse, thereby initiating another pixel output cycle.

The voltage developed at analog output (AO) is given by:

V

= V

out

+ (Re) (Ee) (t

drk

)

int

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm

2

is integration time in seconds

AO is driven by a source follower with an internal 330-Ω pulldown resistor (no external resistor is required). The
output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When
the device is not in the output phase, AO is in a high impedance state.

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.

†

For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

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TSL208R

512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

Absolute Maximum Ratings

†

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or

power-off state, VO –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –100 mA to 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature on connection pad for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, t
Operating free-air temperature, T

Load resistance, R
Load capacitance, C

DD

I

IH

IL

clock

int

A

L

L

4.5 5 5.5 V
0 V
2 V
0 0.8 V

5 5000 kHz

0.1026 100 ms
0 70 °C

300 4700 Ω

DD
DD

330 pF

V
V

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TSL208R
512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

Electrical Characteristics at f

= 330 Ω, Ee = 18 µW/cm2 (unless otherwise noted)

R

L

= 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, t

clock

= 5 ms,

int

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V
V

Analog output voltage (white, average over 512 pixels) See Note 1 1.6 2 2.4 V

out

Analog output voltage (dark, average over 512 pixels) 0 50 150 mV

drk

PRNU Pixel response nonuniformity See Notes 2 & 3 ±7% ±20%

Nonlinearity of analog output voltage See Note 3 ±0.4% FS
Output noise voltage See Note 4 1 mVrms

R

Responsivity 16 22 28

e

(µJ/cm2)
SE Saturation exposure See Note 5 155 nJ/cm
V

Analog output saturation voltage 2.5 3.4 V

sat

DSNU Dark signal nonuniformity All pixels See Note 6 25 120 mV
IL Image lag See Note 7 0.5%
I

DD

I

IH

I

IL

V

V

C
C

Supply current, output idle 28 45 mA
High-level input current VI = V

DD

Low-level input current VI = 0 10 µA

High-level output voltage, SO

OH

Low-level output voltage, SO

OL

Input capacitance, SI 40 pF

i(SI)

Input capacitance, CLK 40 pF

i(CLK)

p

p

IO = 50 µA 4.5 4.95
IO = 4 mA 4.6
IO = 50 µA 0.01 0.1
IO = 4 mA 0.4

10 µA

NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.

2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.

3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).

4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.

5. Minimum saturation exposure is calculated using the minimum V

, the maximum V

sat

, and the maximum Re.

drk

6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.

7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:

IL 

V

V

out (white)

out (IL)

 V

 V

drk

 100

drk

V/

2

V

V

Timing Requirements (see Figure 1 and Figure 2)

t

su(SI)

t

h(SI)

t

w

tr, t

NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.

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Setup time, serial input (see Note 8) 20 ns
Hold time, serial input (see Note 8 and Note 9) 0 ns
Pulse duration, clock high or low 50 ns
Input transition (rise and fall) time 0 500 ns

f

9. SI must go low before the rising edge of the next clock pulse.

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MIN NOM MAX UNIT

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TSL208R

512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t
t

Analog output settling time to ±1% CL = 10 pF 185 ns

s

Propagation delay time, SO 50 ns

pd(SO)

TYPICAL CHARACTERISTICS

CLK

SI

513 Clock Cycles

CLK

AO

t

SI

AO

su(SI)

Hi-Z

t

w

Figure 1. Timing Waveforms (each section)

1 2 512 513

50%

t

h(SI)

t

s

Pixel 1

t

s

Pixel 512

Figure 2. Operational Waveforms (each section)

Hi-Z

5 V

2.5 V
0 V

5 V

0 V

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TSL208R
512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

PHOTODIODE SPECTRAL RESPONSIVITY

1

TA = 25°C

0.8

0.6

0.4

Normalized Responsivity

0.2

TYPICAL CHARACTERISTICS

0
300 500 700 900

λ – Wavelength – nm

Figure 3

1100400 600 800 1000

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MECHANICAL INFORMATION

TSL208R

512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

0.091 (2,31)

0.087 (2,21)
Mounting Holes
2 Places

0.230 (5,84)

0.210 (5,33)

0.080 (2,03)

0.060 (1,52)

0.137(3,48)

0.126 (3,22)

DIA

(Index of Refraction = 1.52)

1.1325 (28,77)

1.1125 (28,26)

0.169(4,29)

0.161(4,09)

Pixel 1

Cover Glass

DETAIL A

Plated Hole 7 Places

0.027(0,69)

0.021(0,53)

17

2.855 (72,52)

2.835 (72,01)

3.005 (76,33)

2.995 (76,07)

DIA

TOP VIEW

0.015 (0,38) Typical Free Area

1.210 (30,73)

1.190 (30,23)

0.100 (2,54) BSC

Pixel 512

0.242 (6,15)

0.222(5,64)

0.505 (12,83)

0.495(12,57)

Linear Array

0.045 (1,09)±0.005

Bonded Chip

Bypass Cap

DETAIL A

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Pixel centers are located along the center line of the mounting holes.

Cover Glass

Figure 4. TSL208R Mechanical Specifications

0.027 (0,069)

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TSL208R
512  1 LINEAR SENSOR ARRAY

TAOS031C – OCTOBER 2002

PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.

NOTICE

Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.

TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESUL T I N PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.

LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of
Texas Advanced Optoelectronic Solutions Incorporated.

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