Datasheet TSL2014 Datasheet (TAOS)

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TSL2014

896  1 LINEAR SENSOR ARRAY

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TAOS040 – AUGUST 2002

 896 × 1 Sensor-Element Organization
 200 Dots-Per-Inch (DPI) Sensor Pitch
 High Linearity and Uniformity
 Wide Dynamic Range...2000:1 (66 dB)
 Output Referenced to Ground
 Low Image Lag . . . 0.5% Typ
 Operation to 5 MHz
 Single 5-V Supply
 112 mm Active Length

Description

The TSL2014 linear sensor array consists of two
sections of 448 photodiodes and associated charge
amplifier circuitry that can be connected to form a
contiguous 896 × 1 array. The pixels measure 120 µm
(H) by 70 µm (W) with 125-µm center-to-center spacing
and 55-µm spacing between pixels. Operation is
simplified by internal control logic that requires only a
serial-input (SI) signal and a clock.

The TSL2014 is intended for use in a wide variety of
applications including mark detection and code
reading, optical character recognition (OCR) and
contact imaging, edge detection and positioning as well
as optical linear and rotary encoding.

V

DD

SI1 2
AO1 3
SO1 4

SI2 5
CLK 6

GND 7

AO2 8
SO2 9
V

10

DD

PACKAGE

(TOP VIEW)

1

Functional Block Diagram (each section)

Pixel 1 (449)

Integrator

Reset

_
+

Sample/

Output

Switch Control Logic

CLK 448-Bit Shift Register

SI1 (SI2)

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Pixel

2

(450)

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Pixel

(451)

3

Q3Q2Q1

Pixel

448

(896)

Analog

Bus

Q448 (896)



Output
Amplifier

Gain Trim

V

DD

AO1
(AO2)

R

L

External
Load

SO1
(SO2)

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TSL2014
896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

Terminal Functions

TERMINAL

NAME NO.

AO1 3 O Analog output of section 1.
AO2 8 O Analog output of section 2.
CLK 6 I Clock. The clock controls the charge transfer, pixel output and reset.
GND 7 Ground (substrate). All voltages are referenced to GND.
SI1 2 I Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2 5 I Serial input (section 2). SI2 defines the start of the data-out sequence.

SO1 4 O

SO2 9 O
VDD 1, 10 Supply voltage. Supply voltage for both analog and digital circuits.

I/O DESCRIPTION

Serial output (section 1). SO1 signals the end of the data out sequence and provides a signal to drive the input
of section 2 (SI2) in serial mode.

Serial output (section 2). SO2 signals the end of the data out sequence and provides a signal to drive the input
of another device for cascading.

Detailed Description

The sensor consists of 896 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by two 448-bit shift registers and reset logic. A 448-pixel
output cycle is initiated by clocking in a logic 1 into the SI input of a section for one positive going clock edge
(see Figures1 and 2)†. The two 448-pixel sections may be operated independently using a single clock input
or connected in series to form a 896-pixel array. Each section has an independent output (AO), which may be
connected together for the 896-pixel function.

When operating in the 896-pixel mode, as the SI pulse is clocked through the 896-bit shift register, the charge
on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that
generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 897th clock
rising edge, the SI pulse is clocked out of the shift register (S2) and the output assumes a high-impedance state.
Note that this 897th clock pulse is required to terminate the output of the 896th pixel and return the internal logic
to a known state. A subsequent SI pulse can be presented as early as the 898th clock pulse, thereby initiating
another pixel output cycle.

The voltage developed at analog output (AO) is given by:

V

= V

out

+ (Re) (Ee) (t

drk

)

int

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm

2

is integration time in seconds

AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.

†

For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

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TSL2014

896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

Absolute Maximum Ratings

†

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or

power-off state, VO –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –150 mA to 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature on solder pads for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, serial t
Sensor integration time, parallel t
Operating free-air temperature, T

Load resistance, R
Load capacitance, C

DD

I

IH

IL

clock

int

int
A

L

L

4.5 5 5.5 V
0 V
2 V
0 0.8 V

5 5000 kHz

0.1792 100 ms

0.090 100 ms
0 70 °C

300 4700 Ω

DD
DD

330 pF

V
V

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TSL2014
896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

Electrical Characteristics at f
R

= 330 Ω, Ee = 18µW/cm2 (unless otherwise noted)

L

= 200 kHz, VDD = 5 V, TA = 25°C, λp = 640 nm, t

clock

= 5 ms,

int

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V
V

Analog output voltage (white, average over 896 pixels) See Note 1 1.6 2 2.4 V

out

Analog output voltage (dark, average over 896 pixels) 0 0.05 0.15 V

drk

PRNU Pixel response nonuniformity See Notes 2 & 3 7% 20%

Nonlinearity of analog output voltage See Note 3 ±0.4% FS
Output noise voltage See Note 4 1 mVrms

R

Responsivity 16 22 28

e

(µJ/cm2)
SE Saturation exposure See Note 5 155 nJ/cm
V

Analog output saturation voltage 2.5 3.4 V

sat

DSNU Dark signal nonuniformity All pixels See Note 6 25 120 mV
IL Image lag See Note 7 0.5%
I

DD

I

IH

I

IL

V

V

C
C

Supply current, output idle 53 80 mA
High-level input current VI = V

DD

Low-level input current VI = 0 10 µA

High-level output voltage, SO1 and SO2

OH

Low-level output voltage, SO1 and SO2

OL

Input capacitance, SI 35 pF

i(SI)

Input capacitance, CLK 70 pF

i(CLK)

p

p

IO = 50 µA 4.5 4.95
IO = 4 mA 4.6
IO = 50 µA 0.01 0.1
IO = 4 mA 0.4

10 µA

NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.

2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.

3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).

4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.

5. Minimum saturation exposure is calculated using the minimum V

, the maximum V

sat

, and the maximum Re.

drk

6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.

7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:

IL 

V

V

out (white)

out (IL)

 V

 V

drk

 100

drk

V/

2

V

V

Timing Requirements (see Figure 1 and Figure 2)

t

su(SI)

t

h(SI)

t

w

tr, t

NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.

Copyright  2002, TAOS Inc.

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Setup time, serial input (see Note 8) 20 ns
Hold time, serial input (see Note 8 and Note 9) 0 ns
Pulse duration, clock high or low 50 ns
Input transition (rise and fall) time 0 500 ns

f

9. SI must go low before the rising edge of the next clock pulse.

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MIN NOM MAX UNIT

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TSL2014

896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t
t

Analog output settling time to ±1% RL = 330 Ω CL = 10 pF 185 ns

s

Propagation delay time, SO1 and SO2 50 ns

pd

TYPICAL CHARACTERISTICS

CLK

SI

449 Clock Cycles

AO

CLK

t

su(SI)

SI1 (SI2)

SO1 (SO2)

Hi-Z

t

1 (449) 2 (450) 448 (896) 449 (897)

w

2.5 V

2.5 V 2.5 V

2.5 V

t

h(SI)

t

s

Figure 1. Timing Waveforms (each section)

t

pd(SO)

t

s

t

pd(SO)

Hi-Z

5 V

2.5 V
0 V

5 V

0 V

AO1 (A02)

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Pixel 448 (896)

Figure 2. Operational Waveforms (each section)

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TSL2014
896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

PHOTODIODE SPECTRAL RESPONSIVITY

1

TA = 25°C

0.8

TYPICAL CHARACTERISTICS

ANALOG OUTPUT SETTLING TIME

LOAD CAPACITANCE AND RESISTANCE

600

VDD = 5 V
V

= 1 V

out

500

vs

470 pF

220 pF

0.6

0.4

Normalized Responsivity

0.2

0
300 500 700 900

λ – Wavelength – nm

Figure 3

400

300

200

— Settling Time to 1% — ns

s

t

100

1100400 600 800 1000

0

0 400 800 1200

APPLICATION INFORMATION

TSL2014

100 pF

10 pF

200 600 1000

RL – Load Resistance – Ω

Figure 4

TSL2014

SI Input

AO 1

R

L

330 

Clock Input

AO 2

R

L

330 

PARALLEL

Copyright  2002, TAOS Inc.

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V

DD

SI1 2
AO1 3
SO1 4

SI2 5
CLK 6

GND 7

AO2 8
SO2 9

V

10

DD

V

1

SI Input

AO 1/AO 2

DD

SI1 2
AO1 3
SO1 4

1

SI2 5

Clock Input

CLK 6

GND 7

AO2 8

R

L

330 

SO2 9
V

10

DD

SERIAL

Figure 5. Connection Diagrams

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MECHANICAL INFORMATION

TSL2014

896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

9.525

9.271

C

L

Pixel 896

Cover Glass

3.30

3.05

4.32

3.80

10  

A

A

0.385

0.315

Pin 10

120.14

119.89

3  

1.22

0.96

2.54

1

Pin 1

1.43

1.17

49.02

48.77

Pixel 1

3.05

16.95

16.45

4.32

3.80

0.69

SECTION A–A

SCALE 6 : 1

NOTES: A. All linear dimensions are in millimeters.

B. Cover glass index of refraction is 1.52.
C. This drawing is subject to change without notice.

Figure 6. TSL2014 Mechanical Specifications

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Bonded Array DieBypass Capacitor

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TSL2014
896  1 LINEAR SENSOR ARRAY

TAOS040 – AUGUST 2002

PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.

NOTICE

Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.

TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESUL T I N PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.

LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of
Texas Advanced Optoelectronic Solutions Incorporated.

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