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TSL1401R
Datasheet (TAOS)
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Datasheet TSL1401R Datasheet (TAOS)

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Page 1
TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
128 × 1 Sensor-Element Organization 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity
SI 1
DIP PACKAGE
(TOP VIEW)
8 NC
Wide Dynamic Range...4000:1 (72 dB) Output Referenced to Ground
CLK 2
7 GND
Low Image Lag . . . 0.5% Typ Operation to 8 MHz
AO 3
6 GND
Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO)
DD
4
5 NC
V
No External Load Resistor Required Replacement for TSL1401
Description
The TSL1401R linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 µm (H) by 55.5 µm (W) with 63.5-µm center-to-center spacing and 8-µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock.
NC – No internal connection
Functional Block Diagram
Pixel 1
2
CLK 128-Bit Shift Register
1
SI
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Integrator
Reset
_ +
Sample/
Output
Switch Control Logic
Pixel
2
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759
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Pixel
3
6, 7
4
V
DD
3
AO
GND
1
Pixel
128
Analog
Bus
Q3Q2Q1Hold
Q128
Output Buffer
Gain Trim
Page 2
TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Terminal Functions
TERMINAL
NAME NO.
AO 3 Analog output. CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 6, 7 Ground (substrate). All voltages are referenced to the substrate. NC 5, 8 No internal connection. SI 1 Serial input. SI defines the start of the data-out sequence. V
DD
4 Supply voltage. Supply voltage for both analog and digital circuits.
DESCRIPTION
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock pulse, thereby initiating another pixel output cycle.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by:
where:
V
out
V
drk
R E
e
t
int
is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(µJ/cm2)
e
is the incident irradiance in µW/cm is integration time in seconds
= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
DD
= V
V
out
+ (Re) (Ee)(t
drk
2
int
)
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device. The TSL1401R is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding.
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Absolute Maximum Ratings
†
Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) or (VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high impedance or power-off state, VO –0.3 V to VDD + 0.3 V. . . Continuous output current, I
(V
= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
Continuous current through VDD or GND –40 mA to 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum light exposure at 638 nm 5 mJ/cm
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Wavelength of light source, λ 400 1000 nm Clock frequency, f Sensor integration time, t Setup time, serial input, t Hold time, serial input, t Operating free-air temperature, T
NOTE 1: SI must go low before the rising edge of the next clock pulse.
DD
I
IH
IL
clock
int
su(SI)
(see Note 1) 0 ns
h(SI)
A
3 5 5.5 V 0 V 2 V 0 0.8 V
5 8000 kHz
0.018 100 ms 20 ns
0 70 °C
DD DD
V V
2
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
Electrical Characteristics at f R
= 330 Ω, Ee = 11 µW/cm2 (unless otherwise noted) (see Note 2)
L
= 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, t
clock
= 5 ms,
int
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V V
Analog output voltage (white, average over 128 pixels) See Note 3 1.6 2 2.4 V
out
Analog output voltage (dark, average over 128 pixels) Ee = 0 0 0.1 0.2 V
drk
PRNU Pixel response nonuniformity See Note 4 ±4% ±7.5%
Nonlinearity of analog output voltage See Note 5 ±0.4% FS Output noise voltage See Note 6 1 mVrms
R
V
SE Saturation exposure DSNU Dark signal nonuniformity All pixels, E
Responsivity See Note 7 25 35 45
e
Analog output saturation voltage
sat
VDD = 5 V, RL = 330 Ω 4.5 4.8 VDD = 3 V, RL = 330 Ω 2.5 2.8 VDD = 5 V, See Note 8 136 VDD = 3 V, See Note 8 78
= 0, See Note 9 0.02 0.05 V
e
IL Image lag See Note 10 0.5%
I I
I C
DD
IH IL
Supply current High-level input current VI = V
Low-level input current VI = 0 1 µA Input capacitance 5 pF
i
VDD = 5 V, Ee = 0 2.8 4.5 VDD = 3 V, Ee = 0 2.6 4.5
DD
NOTES: 2. All measurements made with a 0.1 µF capacitor connected between VDD and ground.
3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. R
8. SE(min) = [V
e(min)
= [V
out(min)
sat(min)
– V
– V
drk(max)
drk(min)
] ÷ (Ee × t
] ×〈Ee × t
int
)
int
) ÷[V
out(max)
– V
drk(min)
]
9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition:
IL
V
V
out (white)
out (IL)
V
V
drk
100
drk
V/
(µJ/cm2)
nJ/cm
mA
1 µA
V
2
Timing Requirements (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
t t t tr, t
su(SI) h(SI) w
f
Setup time, serial input (see Note 11) 20 ns Hold time, serial input (see Note 11 and Note 12) 0 ns Pulse duration, clock high or low 50 ns Input transition (rise and fall) time 0 500 ns
NOTES: 11. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
12. SI must go low before the rising edge of the next clock pulse.
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
4
Analog output settling time to ±1% RL = 330 Ω, CL = 10 pF 120 ns
s
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CLK
Internal
Reset
TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
TYPICAL CHARACTERISTICS
SI
Integration
AO
CLK
t
su(SI)
SI
AO
18 Clock Cycles
Not Integrating Integrating
129 Clock Cycles
Figure 1. Timing Waveforms
t
w
1 2 128 129
50%
t
h(SI)
t
s
Pixel 1
Pixel 128
t
int
Hi-ZHi-Z
2.5 V
5 V 0 V
5 V
0 V
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Figure 2. Operational Waveforms
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
TYPICAL CHARACTERISTICS
PHOTODIODE SPECTRAL RESPONSIVITY
1
TA = 25°C
0.8
0.6
0.4
NORMALIZED IDLE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2
1.5
1
Relative Responsivity
0.2
0
400 500 600 700 800 900 1000 1100300
WHITE OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
2
VDD = 5 V t
= 0.5 ms to 15 ms
int
1.5
1
— Output Voltage — V
out
V
0.5
λ – Wavelength – nm
Figure 3
vs
0.5
— Normalized Idle Supply Current
DD
I
0
010 3040 7060
20
TA – Free-Air Temperature – °C
Figure 4
DARK OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
0.10 VDD = 5 V
0.09
0.08
— Output Voltage
out
V
0.07
vs
t
= 0.5 ms
int
t
int
t
= 15 ms
int
t
int
t
= 2.5 ms
int
50
= 1 ms
= 5 ms
0
010 3040 706020
TA – Free-Air Temperature – °C
6
Figure 5
50
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0.06
010 3040 706020
50
TA – Free-Air Temperature – °C
Figure 6
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128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TYPICAL CHARACTERISTICS
TSL1401R
TAOS035B – AUGUST 2002
SETTLING TIME
vs.
LOAD
600
500
400
300
200
Settling Time to 1% — ns
100
VDD = 3 V
V
= 1 V
out
0
0 200 400 600 800 1000
RL — Load Resistance –
Figure 7
470 pF
220 pF
100 pF
10 pF
SETTLING TIME
vs.
LOAD
600
500
400
300
200
Settling Time to 1% — ns
100
VDD = 5 V
V
= 1 V
out
0
0 200 400 600 800 1000
RL — Load Resistance –
Figure 8
470 pF
220 pF
100 pF
10 pF
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Page 8
TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
MECHANICAL INFORMATION
This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated in an electrically nonconductive clear plastic compound.
0.440 (11,18)
0.420 (10,67)
Centerline of Pin 1 Nominally
Lies Between Pixels 5 and 6.
0.260 (6,60)
0.240 (6,61)
C
L
58
67
0.017 (0,43) CLPixels
C
Package
L
0.310 (7,87)
0.290 (7,37)
0.075 (1,91)
0.060 (1,52)
100°
90°
0.260 (6,60)
0.240 (6,10)
10°
8°
0.012 (0,30)
0.008 (0,20)
0.30 (0,76) NOM
0.130 (3,30)
0.120 (3,05) Seating Plane
NOTES: A. All linear dimensions are in inches and (millimeters).
B. Index of refraction of clear plastic is 1.55.
C. This drawing is subject to change without notice.
Figure 9. Packaging Configuration
CLPin 1
0.016 (0,41)
0.014 (0,36)
Die Thickness
0.060 (1,52)
0.040 (1,02)
23
0.10 (2,54)
0.025 (0,64)
0.015 (0,38)
41
8°
8°
0.150 (3,81)
0.125 (3,18)
0.053 (1,35)
0.043 (1,09)
0.175 (9,78)
0.155 (7,75)
8
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consquential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESUL T I N PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
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TSL1401R
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS035B – AUGUST 2002
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