Page 1
TSH321
WIDE BANDWIDTHAND MOS INPUTS
SINGLE OPERATIONALAMPLIFIER
June 1998
ORDERCODES
Part
Number
Temperature
Range
Package
ND
TSH321I -40
o
C, 125oC ••
321-01.TBL
1
2
3
4
8
6
5
7
Inverting Input
Non-invertingInput
Output
Offset Null 2Offset Null 1
N.C.
V
CC
V
CC
+
321-01.EPS
PINCONNECTIONS (top view)
.LOW DISTORTION
.GAIN BANDWIDTH PRODUCT : 300MHz
.GAIN OF 2 STABILITY
.SLEW RATE : 400V/µs
.VERY FASTSETTLING TIME : 60ns (0.1%)
.VERY HIGH INPUT IMPEDANCE
D
SO8
(Plastic Micropackage)
N
DIP8
(Plastic Package)
DESCRIPTION:
The TSH321is a widebandmonolithic operational
amplifier, requiringa minimum close loopgain of 2
for stability.
The TSH321featuresextremelyhigh input impedance (typically greater than 10
12
Ω) allowing direct
interfacingwith high impedance sources.
Low distortion, wide bandwidth and high linearity
make this amplifiersuitableforRF and video applications. Short circuit protection is provided by an
internal current-limiting circuit.
The TSH321 has internal electrostatic discharge
(ESD)protection circuits andfulfillsMILSTD883CClass2.
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3
non inverting
input
2
inverting
input
1
8
Offset N1
Offset N2
7V
CC
+
C
c
6
output
Internal
V
CC
-
4
V
ref
321-02.EPS
SCHEMATICDIAGRAM
ABSOLUTEMAXIMUMRATINGS
Symbol Parameter Value Unit
V
CC
Supply Voltage ± 7V
V
id
Differential Input Voltage ± 5V
V
i
Input Voltage Range ± 5V
I
in
Current On Offset Null Pins ± 20 mA
T
oper
Operating Free-Air Temperature Range TSH321I -40oC, 125oC
o
C
321-02.TBL
N1
N2
TSH321
100k
Ω
V
CC
321-03.EPS
INPUT OFFSET VOLTAGENULL CIRCUIT
OPERATINGCONDITIONS
Symbol Parameter Value Unit
V
CC
Supply Voltage ± 3to±6V
V
ic
Common Mode Input VoltageRange V
CC
-
to V
CC
+
-3 V
321-03.TBL
TSH321
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Page 3
ELECTRICALCHARACTERISTICS
V
CC
= ± 5V, T
amb
=25oC (unless otherwisespecified)
Symbol Parameter Min. Typ. Max. Unit
V
io
Input Offset Voltage
T
min
≤ T
amb
≤ T
max.
0.5 10
12
mV
DV
io
Input Offset Voltage Drift
T
min
≤ T
amb
≤ T
max.
10
µV/
o
C
I
ib
Input Bias Current 2 300 pA
I
io
Input Offset Current 2 200 pA
I
CC
Supply Current, no load
V
CC
= ± 5V
V
CC
= ± 3V
V
CC
= ±6V
T
min
≤ T
amb
≤ T
max.
VCC= ± 5V
23
21
25
30
28
40
32
mA
A
vd
Large Signal VoltageGain
V
o
= ±2.5V
R
L
= ∞
R
L
= 100Ω
R
L
=50Ω
800
300
200
1300
850
650
V/V
V
icm
Input Common Mode Voltage Range -5 to +2 -5.5 to +2.5 V
CMR Common Mode Rejection Ratio V
ic=Vicm min.
60 100 dB
SVR Supply Voltage Rejection Ratio
V
CC
= ± 5V to ± 3V 50 70
dB
V
o
Output Voltage RL= 100Ω
R
L
=50Ω
T
min
≤ T
amb
≤ T
max.
RL= 100Ω
R
L
=50Ω
±3
±2.8
± 2.9
± 2.7
+3.5
-3.7
+3.3
-3.5
V
I
o
Output Short Circuit Current
V
id
= ±1V, Vo=0V ±50 ± 100
mA
GBP Gain Bandwidth Product
A
VCL
= 100, RL= 100Ω,CL= 15pF,f = 7.5MHz 300
MHz
SR Slew Rate
V
in
= ± 1V,A
VCL
=2RL= 100Ω,CL= 15pF 200 400
V/µs
e
n
Equivalent Input VoltageNoise
R
S
=50Ω
fo = 1kHz
fo = 10kHz
fo = 100kHz
fo = 1MHz
20
18.2
18.1
18.2
nV
√Hz
K
ov
Overshoot
V
in
= ± 1V A
VCL
=2,RL= 100Ω,CL= 15pF 15
%
t
s
Settling Time 0.1% - (note1)
V
in
= ± 1V,A
VCL
=-1 60
ns
t
r,tf
Rise and Fall Time - (note1)
V
in
= ±100mV,A
VCL
=2 2
ns
t
d
Delay Time - (note 1)
V
in
= ±100mV,A
VCL
=2 2
ns
∅m Phase Margin
A
VM
=2,RL= 100Ω, CL= 15pF 45
Degrees
THD Total Harmonic Distortion
A
VCL
= 10, f = 1KHz, Vo= ± 2.5V,no load 0.02
%
FPB Full Power Bandwidth - (note 2)
V
o
= 5Vpp, RL= 100Ω
V
o
= 2Vpp, RL= 100Ω
26
64
MHz
Note 1 : See test waveform figure
Note 2 : Full powerbandwidth =
SR
Π V
opp
321-04.TBL
TSH321
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V
in
50%
t
d
t
r
90%
t
s
0.1% of edge amplitude
10%
321-04.EPS
TEST WAVEFORM
Input
50Ω
1kΩ
1kΩ
10nF
10µF
C
F
-5V
+5V
10nF
10µF
50
Ω
Output
321-05.EPS
EVALUATION CIRCUIT
As for any high frequencydevice, a few rules must
be observedwhendesigningthePCBto get the best
performancesfrom this high speed op amp.
From the most to the least important points :
• Each power supply lead has to be bypassed
to ground with a 10nF ceramic capacitor very
close to the deviceand a 10µF tantalum ca-
pacitor.
• To providelow inductanceand lowresistance
common return, use a ground plane or common point return for power and signal.
• All leads must be wideand as short as possi-
ble especially for op amp inputs. This is in
order to decrease parasitic capacitance and
inductance.
• Use small resistor values to decrease time
constantwith parasitic capacitance.
• Choosecomponentsizesassmallaspossible
(SMD).
• On output, decrease capacitor load so as to
avoid circuit stability being degraded which
may cause oscillation. One can also add a
serial resistor in order to minimise its influence.
• One can addin parallelwithfeedbackresistor
a few pF ceramic capacitor C
F
adjusted to
optimizethe settlingtime.
PRINTEDCIRCUIT LAYOUT
TSH321
4/6
Page 5
PM-DIP8.EPS
PACKAGEMECHANICAL DATA
8 PINS - PLASTICDIP
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0260
i 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
DIP8.TBL
TSH321
5/6
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PM-SO8.EPS
PACKAGEMECHANICAL DATA
8 PINS - PLASTICMICROPACKAGE(SO)
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
a1 0.1 0.25 0.004 0.010
a2 1.65 0.065
a3 0.65 0.85 0.026 0.033
b 0.35 0.48 0.014 0.019
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.020
c1 45
o
(typ.)
D 4.8 5.0 0.189 0.197
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F 3.8 4.0 0.150 0.157
L 0.4 1.27 0.016 0.050
M 0.6 0.024
S8
o
(max.)
SO8.TBL
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for useas criticalcomponents inlife supportdevices or systems
without express written approval of STMicroelectronics.
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ORDER CODE :
TSH321
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