Datasheet TSB80L188EC16, TSB80L188EC13, TSB80C188EC20, TSB80C188EC13, TSB80C186EC20 Datasheet (Intel Corporation)

*Other brands and names are the property of their respective owners.

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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

May 1996COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 272434-004

80C186EC/80C188EC AND 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

X

Fully Static Operation

X

True CMOS Inputs and Outputs

Y

Integrated Feature Set:
Ð Low-Power, Static, Enhanced 8086

CPU Core

Ð Two Independent DMA Supported

UARTs, each with an Integral Baud

Rate Generator
Ð Four Independent DMA Channels
Ð 22 Multiplexed I/O Port Pins
Ð Two 8259A Compatible

Programmable Interrupt Controllers
Ð Three Programmable 16-Bit Timer/

Counters
Ð 32-Bit Watchdog Timer
Ð Ten Programmable Chip Selects with

Integral Wait-State Generator
Ð Memory Refresh Control Unit
Ð Power Management Unit
Ð On-Chip Oscillator
Ð System Level Testing Support

(ONCE Mode)

Y

Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I/O

Y

Low-Power Operating Modes:
Ð Idle Mode Freezes CPU Clocks but

Keeps Peripherals Active
Ð Powerdown Mode Freezes All

Internal Clocks
Ð Powersave Mode Divides All Clocks

by Programmable Prescalar

Y

Available in Extended Temperature
Range (

b

40§Ctoa85§C)

Y

Supports 80C187 Numerics Processor
Extension (80C186EC only)

Y

Package Types:
Ð 100-Pin EIAJ Quad Flat Pack (QFP)
Ð 100-Pin Plastic Quad Flat Pack

(PQFP)

Ð 100-Pin Shrink Quad Flat Pack

(SQFP)

Y

Speed Versions Available (5V):
Ð 25 MHz (80C186EC25/80C188EC25)
Ð 20 MHz (80C186EC20/80C188EC20)
Ð 13 MHz (80C186EC13/80C188EC13)

Y

Speed Version Available (3V):
Ð 16 MHz (80L186EC16/80L188EC16)
Ð 13 MHz (80L186EC13/80L188EC13)

The 80C186EC is a member of the 186 Integrated Processor Family. The 186 Integrated Processor Family
incorporates several different VLSI devices all of which share a common CPU architecture: the 8086/8088.
The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common
system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic
silicon die.

80C186EC/80C188EC and 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION

EMBEDDED PROCESSOR

CONTENTS PAGE

INTRODUCTION

ААААААААААААААААААААААААААА 4

80C186EC CORE ARCHITECTURE ААААААА 4

Bus Interface Unit АААААААААААААААААААААААААА 4
Clock Generator ААААААААААААААААААААААААААА 4

80C186EC PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Programmable Interrupt Controllers ААААААААА 7
Timer/Counter Unit АААААААААААААААААААААААА 7
Serial Communications Unit АААААААААААААААА 7
DMA Unit АААААААААААААААААААААААААААААААААА 7
Chip-Select Unit АААААААААААААААААААААААААААА 7
I/O Port Unit ААААААААААААААААААААААААААААААА 7
Refresh Control Unit ААААААААААААААААААААААА 7
Watchdog Timer Unit ААААААААААААААААААААААА 7
Power Management Unit ААААААААААААААААААА 8
80C187 Interface (80C186EC only) ААААААААА 8
ONCE Test Mode АААААААААААААААААААААААААА 8

PACKAGE INFORMATION АААААААААААААААА 8

Prefix Identification ААААААААААААААААААААААААА 8
Pin Descriptions АААААААААААААААААААААААААААА 8
Pinout АААААААААААААААААААААААААААААААААААА 15
Package Thermal Specifications ААААААААААА 24

ELECTRICAL SPECIFICATIONS ААААААААА 25

Absolute Maximum Ratings ААААААААААААААА 25

CONTENTS PAGE

Recommended Connections

АААААААААААААА 25

DC SPECIFICATIONS АААААААААААААААААААА 26

ICCversus Frequency and Voltage ААААААААА 29
PDTMR Pin Delay Calculation ААААААААААААА 29

AC SPECIFICATIONS АААААААААААААААААААА 30

AC CharacteristicsÐ80C186EC25 ААААААААА 30
AC CharacteristicsÐ80C186EC20/13 ААААА 32
AC CharacteristicsÐ80L186EC13 ААААААААА 33
AC CharacteristicsÐ80L186EC16 ААААААААА 34
Relative Timings АААААААААААААААААААААААААА 35
Serial Port Mode 0 Timings АААААААААААААААА 36

AC TEST CONDITIONS АААААААААААААААААА 37

AC TIMING WAVEFORMS ААААААААААААААА 37

DERATING CURVES ААААААААААААААААААААА 40

RESET ААААААААААААААААААААААААААААААААААА 40

BUS CYCLE WAVEFORMS АААААААААААААА 43

EXECUTION TIMINGS ААААААААААААААААААА 50

INSTRUCTION SET SUMMARY АААААААААА 51

ERRATA ААААААААААААААААААААААААААААААААА 57

REVISION HISTORY ААААААААААААААААААААА 57

2

80C186EC/188EC, 80L186EC/188EC

272434–1

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC

Figure 1. 80C186EC/80L186EC Block Diagram

3

80C186EC/188EC, 80L186EC/188EC

INTRODUCTION

Unless specifically noted, all references to the
80C186EC apply to the 80C188EC, 80L186EC, and
80L188EC. References to pins that differ between
the 80C186EC/80L186EC and the 80C188EC/
80L188EC are given in parentheses. The ‘‘L’’ in the
part number denotes low voltage operation. Physi­cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are
identical.

The 80C186EC is one of the highest integration
members of the 186 Integrated Processor Family.
Two serial ports are provided for services such as
interprocessor communication, diagnostics and mo­dem interfacing. Four DMA channels allow for high
speed data movement as well as support of the on­board serial ports. A flexible chip select unit simpli­fies memory and peripheral interfacing. The three
general purpose timer/counters can be used for a
variety of time measurement and waveform genera­tion tasks. A watchdog timer is provided to insure
system integrity even in the most hostile of environ­ments. Two 8259A compatible interrupt controllers
handle internal interrupts, and, up to 57 external in­terrupt requests. A DRAM refresh unit and 24 multi­plexed I/O ports round out the feature set of the
80C186EC.

The future set of the 80C186EC meets the needs of
low-power, space-critical applications. Low-power
applications benefit from the static design of the
CPU and the integrated peripherals as well as low
voltage operation. Minimum current consumption is
achieved by providing a powerdown mode that halts
operaton of the device and freezes the clock cir­cuits. Peripheral design enhancements ensure that
non-initialized peripherals consume little current.

The 80L186EC is the 3V version of the 80C186EC.
The 80L186EC is functionally identical to the
80C186EC embedded processor. Current
80C186EC users can easily upgrade their designs to
use the 80L186EC and benefit from the reduced
power consumption inherent in 3V operation.

Figure 1 shows a block diagram of the 80C186EC/
80C188EC. The execution unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhanced
execution speed for multiple-bit shift and rotate in­structions and for multiply and divide instructions,
string move instructions that operate at full bus
bandwidth, ten new instructions and fully static oper­ation. The bus interface unit (BIU) is the same as
that found on the original 186 family products, ex­cept the queue-status mode has been deleted and
buffer interface control has been changed to ease
system design timings. An independent internal bus
is used for communication between the BIU and on­chip peripherals.

80C186EC CORE ARCHITECTURE

Bus Interface Unit

The 80C186EC core incorporates a bus controller
that generates local bus control signals. In addition,
it employs a HOLD/HLDA protocol to share the local
bus with other bus masters.

The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information and data (for write operations) in­formation. It is also responsible for reading data
from the local bus during a read operation. A ready
input pin is provided to extend a bus cycle beyond
the minimum four states (clocks).

The bus controller also generates two control sig­nals (DEN

and DT/R) when interfacing to external
transceiver chips. This capability allows the addition
of transceivers for simple buffering of the multi­plexed address/data bus.

Clock Generator

The 80C186EC provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide­by-two counter and three low-power operating
modes.

The oscillator circuit is designed to be used with ei­ther a parallel resonant fundamental or third-over­tone mode crystal network. Alternatively, the oscilla­tor circuit may be driven from an external clock
source. Figure 2 shows the various operating modes
of the oscillator circuit.

The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter. This counter is
used to drive all internal phase clocks and the exter­nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys­tem components. All AC timings are referenced to
CLKOUT.

The following parameters are recommended when
choosing a crystal:

Temperature Range: Application Specific

ESR (Equivalent Series Res.): 40X max

C0 (Shunt Capacitance of Crystal): 7.0 pF max

C

L

(Load Capacitance): 20 pFg2pF

Drive Level: 1 mW (max)

4

80C186EC/188EC, 80L186EC/188EC

272434–2

NOTE:

1. The LC network is only required when using a third overtone crystal.

Figure 2. 80C186EC Clock Connections

80C186EC PERIPHERAL
ARCHITECTURE

The 80C186EC integrates several common system
peripherals with a CPU core to create a compact, yet
powerful system. The integrated peripherals are de­signed to be flexbile and provide logical interconnec­tions between supporting units (e.g., the DMA unit
can accept requests from the Serial Communica­tions Unit).

The list of integrated peripherals includes:

Ð Two cascaded, 8259A compatible, Programma-

ble Interrupt Controllers

Ð 3-Channel Timer/Counter Unit

Ð 2-Channel Serial Communications Unit

Ð 4-Channel DMA Unit

Ð 10-Output Chip-Select Unit

Ð 32-bit Watchdog Timer Unit

Ð I/O Port Unit

Ð Refresh Control Unit

Ð Power Management Unit

The registers associated with each integrated pe­ripheral are contained within a 128 x 16-bit register
file called the Peripheral Control Block (PCB). The
base address of the PCB is programmable and can
be located on any 256 byte address boundary in ei­ther memory or I/O space.

Figure 3 provides a list of the registers associated
with the PCB. The Register Bit Summary individually
lists all of the registers and identifies each of their
programming attributes.

5

80C186EC/188EC, 80L186EC/188EC

PCB

Function

Offset

00H Master PIC Port 0

02H Master PIC Port 1

04H Slave PIC Port 0

06H Slave PIC Port 1

08H Reserved

0AH SCU Int. Req. Ltch.

0CH DMA Int. Req. Ltch.

0EH TCU Int. Req. Ltch.

10H Reserved

12H Reserved

14H Reserved

16H Reserved

18H Reserved

1AH Reserved

1CH Reserved

1EH Reserved

20H WDT Reload High

22H WDT Reload Low

24H WDT Count High

26H WDT Count Low

28H WDT Clear

2AH WDT Disable

2CH Reserved

2EH Reserved

30H T0 Count

32H T0 Compare A

34H T0 Compare B

46H T0 Control

38H T1 Count

3AH T1 Compare A

3CH T1 Compare B

3EH T1 Control

PCB

Function

Offset

40H T2 Count

42H T2 Compare

44H Reserved

46H T2 Control

48H Port 3 Direction

4AH Port 3 Pin State

4CH Port 3 Mux Control

4EH Port 3 Data Latch

50H Port 1 Direction

52H Port 1 Pin State

54H Port 1 Mux Control

56H Port 1 Data Latch

58H Port 2 Direction

5AH Port 2 Pin State

5CH Port 2 Mux Control

5EH Port 2 Data Latch

60H SCU 0 Baud

62H SCU 0 Count

64H SCU 0 Control

66H SCU 0 Status

68H SCU 0 RBUF

6AH SCU 0 TBUF

6CH Reserved

6EH Reserved

70H SCU 1 Baud

72H SCU 1 Count

74H SCU 1 Control

76H SCU 1 Status

78H SCU 1 RBUF

7AH SCU 1 TBUF

7CH Reserved

7EH Reserved

PCB

Function

Offset

80H GCS0 Start

82H GCS0 Stop

84H GCS1 Start

86H GCS1 Stop

88H GCS2 Start

8AH GCS2 Stop

8CH GCS3 Start

8EH GCS3 Stop

90H GCS4 Start

92H GCS4 Stop

94H GCS5 Start

96H GCS5 Stop

98H GCS6 Start

9AH GCS6 Stop

9CH GCS7 Start

9EH GCS7 Stop

A0H LCS Start

A2H LCS Stop

A4H UCS Start

A6H UCS Stop

A8H Relocation Register

AAH Reserved

ACH Reserved

AEH Reserved

B0H Refresh Base Addr.

B2H Refresh Time

B4H Refresh Control

B6H Refresh Address

B8H Power Control

BAH Reserved

BCH Step ID

BEH Powersave

PCB

Function

Offset

C0H DMA 0 Source Low

C2H DMA 0 Source High

C4H DMA 0 Dest. Low

C6H DMA 0 Dest. High

C8H DMA 0 Count

CAH DMA 0 Control

CCH DMA Module Pri.

CEH DMA Halt

D0H DMA 1 Source Low

D2H DMA 1 Source High

D4H DMA 1 Dest. Low

D6H DMA 1 Dest. High

D8H DMA 1 Count

DAH DMA 1 Control

DCH Reserved

DEH Reserved

E0H DMA 2 Source Low

E2H DMA 2 Source High

E4H DMA 2 Dest. Low

E6H DMA 2 Dest. High

E8H DMA 2 Count

EAH DMA 2 Control

ECH Reserved

EEH Reserved

F0H DMA 3 Source Low

F2H DMA 3 Source High

F4H DMA 3 Dest. Low

F6H DMA 3 Dest. High

F8H DMA 3 Count

FAH DMA 3 Control

FCH Reserved

FEH Reserved

Figure 3. Peripheral Control Block Registers

6

80C186EC/188EC, 80L186EC/188EC

Programmable Interrupt Controllers

The 80C186EC utilizes two 8259A compatible Pro­grammable Interrupt Controllers (PIC) to manage
both internal and external interrupts. The 8259A
modules are configured in a master/slave arrange­ment.

Seven of the external interrupt pins, INT0 through
INT6, are connected to the master 8259A module.
The eighth external interrupt pin, INT7, is connected
to the slave 8259A module.

There are a total of 11 internal interrupt sources
from the integrated peripherals: 4 Serial, 4 DMA and
3 Timer/Counter.

Timer/Counter Unit

The 80C186EC Timer/Counter Unit (TCU) provides
three 16-bit programmable timers. Two of these are
highly flexible and are connected to external pins for
external control or clocking. The third timer is not
connected to any external pins and can only be
clocked internally. However, it can be used to clock
the other two timer channels. The TCU can be used
to count external events, time external events, gen­erate non-repetitive waveforms or generate timed in­terrupts.

Serial Communications Unit

The 80C186EC Serial Communications Unit (SCU)
contains two independent channels. Each channel is
identical in operation except that only channel 0 is
directly supported by the integrated interrupt control­ler (the channel 1 interrupts are routed to external
interrupt pins). Each channel has its own baud rate
generator and can be internally or externally clocked
up to one half the processor operating frequency.
Both serial channels can request service from the
DMA unit thus providing block reception and trans­mission without CPU intervention.

Independent baud rate generators are provided for
each of the serial channels. For the asynchronous
modes, the generator supplies an 8x baud clock to
both the receive and transmit shifting register logic.
A 1x baud clock is provided in the synchronous
mode.

DMA Unit

The four channel Direct Memory Access (DMA) Unit
is comprised of two modules with two channels
each. All four channels are identical in operation.
DMA transfers can take place from memory to mem­ory, I/O to memory, memory to I/O or I/O to I/O.

DMA requests can be external (on the DRQ pins),
internal (from Timer 2 or a serial channel) or soft­ware initiated.

The DMA Unit transfers data as bytes only. Each
data transfer requires at least two bus cycles, one to
fetch data and one to deposit. The minimum clock
count for each transfer is 8, but this will vary depend­ing on synchronization and wait states.

Chip-Select Unit

The 80C186EC Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip­selects to access both memories and peripherals. In
addition, each chip-select can be programmed to
automatically insert additional clocks (wait states)
into the current bus cycle, and/or automatically ter­minate a bus cycle independent of the condition of
the READY input pin.

I/O Port Unit

The I/O Port Unit on the 80C186EC supports two
8-bit channels and one 6-bit channel of input, output
or input/output operation. Port 1 is multiplexed with
the chip select pins and is output only. Port 2 is mul­tiplexed with the pins for serial channels 1 and 2. All
Port 2 pins are input/output. Port 3 has a total of 6
pins: four that are multiplexed with DMA and serial
port interrupts and two that are non-multiplexed,
open drain I/O.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen­erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed. A 9-bit
counter controls the number of clocks between re­fresh requests.

A 12-bit address generator is maintained by the RCU
and is presented on the A12:1 address lines during
the refresh bus cycle. Address bits A19:13 are pro­grammable to allow the refresh address block to be
located on any 8 Kbyte boundary.

Watchdog Timer Unit

The Watchdog Timer Unit (WDT) allows for graceful
recovery from unexpected hardware and software
upsets. The WDT consists of a 32-bit counter that
decrements every clock cycle. If the counter reach­es zero before being reset, the WDTOUT

pin is

7

80C186EC/188EC, 80L186EC/188EC

pulled low for four clock cycles. Logically ANDing
the WDTOUT

pin with the power-on reset signal al­lows the WDT to reset the device in the event of a
WDT timeout. If a less drastic method of recovery is
desired, WDTOUT

can be connected directly to NMI
or one of the INT input pins. The WDT may also be
used as a general purpose timer.

Power Management Unit

The 80C186EC Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides four power management
modes: Active, Powersave, Idle and Powerdown.

Active Mode indicates that all units on the
80C186EC are operating at (/2 the CLKIN frequency.

Idle Mode freezes the clocks of the Execution and
Bus units at a logic zero state (all peripherals contin­ue to operate normally).

The Powerdown Mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.

In Powersave Mode, all internal clock signals are di­vided by a programmable prescalar (up to (/64 the
normal frequency). Powersave Mode can be used
with Idle Mode as well as during normal (Active
Mode) operation.

80C187 Interface (80C186EC only)

The 80C186EC supports the direct connection of
the 80C187 Numerics Processor Extension. The
80C187 can dramatically improve the performance
of calculation intensive applications.

ONCE Test Mode

To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EC has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’.
The ONCE mode is selected by forcing the
A19/S6/ONCE

pin low during a processor reset
(this pin is weakly held high during reset to prevent
inadvertant entrance into ONCE Mode).

PACKAGE INFORMATION

This section describes the pin functions, pinout and
thermal characteristics for the 80C186EC in the
Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ
Quad Flat Pack (QFP) and the Shrink Quad Flat
Pack (SQFP). For complete package specifications

and information, see the Intel Packaging Outlines
and Dimensions Guide (Order Number: 231369).

Prefix Identification

Table 1 lists the prefix identifications.

Table 1. Prefix Identification

Prefix Note

Package Temperature

Type Range

TS QFP (EIAJ) Extended

KU 1 PQFP Extended/Commercial

SB 1 SQFP Extended/Commercial

S 1 QFP (EIAJ) Commercial

NOTE:

1. The 5V 25 MHz version is only available in commercial
temperature range corresponding to 0

§

Ctoa70§C am-

bient.

Pin Descriptions

Each pin or logical set of pins is described in Table

2. There are four columns for each entry in the Pin

Description Table. The following sections describe
each column.

Column 1: Pin Name

In this column is a mnemonic that de­scribes the pin function. Negation of the
signal name (i.e. RESIN

) implies that the

signal is active low.

Column 2: Pin Type

A pin may be either power (P), ground
(G), input only (I), output only (O) or in­put/output (I/O). Please note that some
pins have more than 1 function.
A19/S6/ONCE

, for example, is normally
an output but functions as an input dur­ing reset. For this reason
A19/S6/ONCE

is classified as an input/

output pin.

Column 3: Input Type (for I and I/O types only)

There are two different types of input
pins on the 80C186EC: asynchronous
and synchronous. Asynchronous pins
require that setup and hold times be met
only to

guarantee recognition

. Synchro-
nous input pins require that the setup
and hold times be met to

guarantee

proper operation

. Stated simply, missing
a setup or hold on an asynchronous pin
will result in something minor (i.e. a timer
count will be missed) whereas missing a
setup or hold on a synchronous pin will
result in system failure (the system will
‘‘lock up’’).

An input pin may also be edge or level
sensitive.

8

80C186EC/188EC, 80L186EC/188EC

Column 4: Output States (for O and I/O types

only)

The state of an output or I/O pin is de­pendent on the operating mode of the
device. There are four modes of opera­tion that are different from normal active
mode: Bus Hold, Reset, Idle Mode, Pow­erdown Mode. This column describes
the output pin state in each of these
modes.

The legend for interpreting the information in the Pin
Descriptions is shown in Table 1.

As an example, please refer to the table entry for
AD12:0. The ‘‘I/O’’ signifies that the pins are bidirec­tional (i.e. have both an input and output function).
The ‘‘S’’ indicates that, as an input the signal must
be synchronized to CLKOUT for proper operation.
The ‘‘H(Z)’’ indicates that these pins will float while

the processor is in the Hold Acknowledge state.
R(Z) indicates that these pins will float while RESIN
is low. P(0) and I(0) indicate that these pins will drive
0 when the device is in either Powerdown or Idle
Mode.

Some pins, the I/O Ports for example, can be pro­grammed to perform more than one function. Multi­function pins have a ‘‘/’’ in their signal name be­tween the different functions (i.e. P3.0/RXI1). If the
input pin type or output pin state differ between func­tions, then that will be indicated by separating the
state (or type) with a ‘‘/’’ (i.e. H(X)/H(Q)). In this
example when the pin is configured as P3.0 then its
hold output state is H(X); when configured as RXI1
its output state is H(Q).

All pins float while the processor is in the ONCE
Mode (with the exception of OSCOUT).

Table 1. Pin Description Nomenclature

Symbol Description

P Power Pin (applyaVCCvoltage)
G Ground (connect to V

SS

)
I Input only pin
O Output only pin
I/O Input/Output pin

S(E) Synchronous, edge sensitive
S(L) Synchronous, level sensitive
A(E) Asynchronous, edge sensitive
A(L) Asynchronous, level sensitive

H(1) Output driven to VCCduring bus hold
H(0) Output driven to V

SS

during bus hold
H(Z) Output floats during bus hold
H(Q) Output remains active during bus hold
H(X) Output retains current state during bus hold

R(WH) Output weakly held at VCCduring reset
R(1) Output driven to V

CC

during reset

R(0) Output driven to V

SS

during reset
R(Z) Output floats during reset
R(Q) Output remains active during reset
R(X) Output retains current state during reset

I(1) Output driven to VCCduring Idle Mode
I(0) Output driven to V

SS

during Idle Mode
I(Z) Output floats during Idle Mode
I(Q) Output remains active during Idle Mode
I(X) Output retains current state during Idle Mode

P(1) Output driven to VCCduring Powerdown Mode
P(0) Output driven to V

SS

during Powerdown Mode
P(Z) Output floats during Powerdown Mode
P(Q) Output remains active during Powerdown Mode
P(X) Output retains current state during Powerdown Mode

9

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions

Pin Name

Pin Input Output

Pin Description

Type Type States

V

CC

PÐ ÐPOWERa5Vg10% power supply connection

V

SS

GÐ ÐGROUND

CLKIN I A(E) Ð CLocK INput is the external clock input. An external

oscillator operating at two times the required processor
operating frequency can be connected to CLKIN. For
crystal operation, CLKIN (along with OSCOUT) are the
crystal connections to an internal Pierce oscillator.

OSCOUT O Ð H(Q) OSCillator OUTput is only used when using a crystal to

generate the internal clock. OSCOUT (along with CLKIN)

R(Q)

are the crystal connections to an internal Pierce oscillator.

I(Q)

This pin can not be used as 2X clock output for non-

P(X)

crystal applications (i.e. this pin is not connected for non­crystal applications).

CLKOUT O Ð H(Q) CLocK OUTput provides a timing reference for inputs and

outputs of the processor, and is one-half the input clock

R(Q)

(CLKIN) frequency. CLKOUT has a 50% duty cycle and

I(Q)

transitions every falling edge of CLKIN.

P(X)

RESIN I A(L) Ð RESet IN causes the processor to immediately terminate

any bus cycle in progress and assume an initialized state.
All pins will be driven to a known state, and RESOUT will
also be driven active. The rising edge (low-to-high)
transition synchronizes CLKOUT with CLKIN before the
processor begins fetching opcodes at memory location
0FFFF0H.

RESOUT O Ð H(0) RESet OUTput that indicates the processor is currently in

the reset state. RESOUT will remain active as long as

R(1)

RESIN

remains active.

I(0)

P(0)

PDTMR I/O A(L) H(WH) Power-Down TiMeR pin (normally connected to an

external capacitor) that determines the amount of time the

R(Z)

processors waits after an exit from Powerdown before

P(WH)

resuming normal operation. The duration of time required

I(WH)

will depend on the startup characteristics of the crystal
oscillator.

NMI I A(E) Ð Non-Maskable Interrupt input causes a TYPE-2 interrupt

to be serviced by the CPU. NMI is latched internally.

TEST/BUSY I A(E) Ð TEST is used during the execution of the WAIT instruction

to suspend CPU operation until the pin is sampled active

(TEST)

(LOW). TEST

is alternately known as BUSY when
interfacing with an 80C187 numerics coprocessor
(80C186EC only).

A19/S6/ONCE I/O A(L) H(Z) This pin drives address bit 19 during the address phase of

the bus cycle. During T2 and T3 this pin functions as

R(WH)

status bit 6. S6 is low to indicate CPU bus cycles and high

I(0)

to indicate DMA or refresh bus cycles. During a processor

P(0)

reset (RESIN

active) this pin becomes the ONCE input
pin. Holding this pin low during reset will force the part into
ONCE Mode.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

10

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name

Pin Input Output

Pin Description

Type Type States

A18/S5 I/O A(L) H(Z) These pins drive address information during the address

phase of the bus cycle. During T2 and T3 these pins drive

A17/S4 R(WH)

status information (which is always 0 on the 80C186EC).

A16/S3 I(0)

These pins are used as inputs during factory test; driving

(A15:8) P(0)

these pins low during reset will cause unspecified operation.
On the 80C188EC, A15:8 provide valid address information
for the entire bus cycle.

AD15/CAS2 I/O S(L) H(Z) These pins are part of the multiplexed ADDRESS and DATA

bus. During the address phase of the bus cycle, address bits

AD14/CAS1 R(Z)

15 through 13 are presented on these pins and can be

AD13/CAS0 I(0)

latched using ALE. Data information is transferred during the

P(0)

data phase of the bus cycle. Pins AD15:13/CAS2:0 drive the
82C59 slave address information during interrupt
acknowledge cycles.

AD12:0 I/O S(L) H(Z) These pins provide a multiplexed ADDRESS and DATA bus.

During the address phase of the bus cycle, address bits 0

(AD7:0) R(Z)

through 12 (0 through 7 on the 80C188EC) are presented on

I(0)

the bus and can be latched using ALE. Data information is

P(0)

transferred during the data phase of the bus cycle.

S2:0 O Ð H(Z) Bus cycle Status are encoded on these pins to provide bus

transaction information. S2:0

are encoded as follows:

R(1)

I(1)

P(1)

S2

S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Processor HALT
1 0 0 Instruction Queue Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (No bus activity)

ALE O Ð H(0) Address Latch Enable output is used to strobe address

information into a transparent type latch during the address

R(0)

phase of the bus cycle.

I(0)

P(0)

BHE O Ð H(Z) Byte High Enable output to indicate that the bus cycle in

progress is transferring data over the upper half of the data

(RFSH

) R(Z)

bus. BHE and A0 have the following logical encoding:

I(1)

P(1)

A0 BHE

Encoding (for 80C186EC/

80L186EC only)

0 0 Word transfer
0 1 Even Byte transfer
1 0 Odd Byte transfer
1 1 Refresh operation

On the 80C188EC/80L188EC, RFSH is asserted low to
indicate a refresh bus cycle.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

11

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name

Pin Input Output

Pin Description

Type Type States

RD O Ð H(Z) ReaD output signals that the accessed memory or I/O

device should drive data information onto the data bus.

R(Z)

I(1)

P(1)

WR O Ð H(Z) WRite output signals that data available on the data bus are

to be written into the accessed memory or I/O device.

R(Z)

I(1)

P(1)

READY I A(L) Ð READY input to signal the completion of a bus cycle. READY

must be active to terminate any 80C186EC bus cycle, unless

S(L)

it is ignored by correctly programming the Chip-Select unit.

(Note 1)

DEN O Ð H(Z) Data ENable output to control the enable of bi-directional

transceivers in a buffered system. DEN

is active only when

R(Z)

data is to be transferred on the bus.

I(1)

P(1)

DT/R O Ð H(Z) Data Transmit/Receive output controls the direction of a bi-

directional buffer in a buffered system.

R(Z)

I(X)

P(X)

LOCK I/O A(L) H(Z) LOCK output indicates that the bus cycle in progress is not

interruptable. The processor will not service other bus

R(Z)

requests (such as HOLD) while LOCK

is active. This pin is

I(X)

configured as a weakly held high input while RESIN

is active

P(X)

and must not be driven low.

HOLD I A(L) Ð HOLD request input to signal that an external bus master

wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed.

HLDA O Ð H(1) HoLD Acknowledge output to indicate that the processor

has relinquished control of the local bus. When HLDA is

R(0)

asserted, the processor will (or has) floated its data bus and

I(0)

control signals allowing another bus master to drive the

P(0)

signals directly.

NCS O Ð H(1) Numerics Coprocessor Select output is generated when

acessing a numerics coprocessor. This signal does not exist

R(1)

on the 80C188EC/80L188EC.

I(1)

P(1)

ERROR I A(L) Ð ERROR input that indicates the last numerics processor

extension operation resulted in an exception condition. An
interrupt TYPE 16 is generated if ERROR

is sampled active
at the beginning of a numerics operation. Systems not using
an 80C187 must tie ERROR

to VCC. This signal does not

exist on the 80C188EC/80L188EC.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

12

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name

Pin Input Output

Pin Description

Type Type States

PEREQ I A(L) Ð Processor Extension REQuest signals that a data

transfer between an 80C187 Numerics Processor
Extension and Memory is pending. Systems not using an
80C187 must tie this pin to V

SS

. This signal does not exist

on the 80C188EC/80L188EC.

UCS O Ð H(1) Upper Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

R(1)

programmed by the user. After reset, UCS

is configured to

I(1)

be active for memory accesses between 0FFC00H and

P(1)

0FFFFFH.

LCS O Ð H(1) Lower Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

R(1)

programmed by the user. LCS

is inactive after a reset.

I(1)

P(1)

P1.0/GCS0 O Ð H(X)/H(1) These pins provide a multiplexed function. If enabled,

each pin can provide a General purpose Chip Select

P1.1/GCS1

R(1)

output which will go active whenever the address of a

P1.2/GCS2

I(X)/I(1)

memory or I/O bus cycle is within the address limitations

P1.3/GCS3

P(X)/P(1)

programmed by the user. When not programmed as a

P1.4/GCS4

Chip-Select, each pin may be used as a general purpose

P1.5/GCS5

output port.

P1.6/GCS6
P1.7/GCS7

T0OUT O Ð H(Q) Timer OUTput pins can be programmed to provide single

clock or continuous waveform generation, depending on

T1OUT R(1)

the timer mode selected.

I(Q)

P(X)

T0IN I A(L) Ð Timer INput is used either as clock or control signals,

depending on the timer mode selected. This pin may be

T1IN A(E)

either level or edge sensitive depending on the
programming mode.

INT7:0 I A(L) Ð Maskable INTerrupt input will cause a vector to a specific

Type interrupt routine. The INT6:0 pins can be used as

A(E)

cascade inputs from slave 8259A devices. The INT pins
can be configured as level or edge sensitive.

INTA O Ð H(1) INTerrupt Acknowledge output is a handshaking signal

used by external 82C59A Programmable Interrupt

R(1)

Controllers.

I(1)

P(1)

P3.5 I/O A(L) H(X) Bidirectional, open-drain port pins.
P3.4 R(Z)

I(X)

H(X)

P3.3/DMAI1 O Ð H(X) DMA Interrupt output goes active to indicate that the

channel has completed a transfer. DMAI1 and DMAI0 are

P3.2/DMAI0 R(0)

multiplexed with output only port functions.

I(Q)

P(X)

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

13

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name

Pin Input Output

Pin Description

Type Type States

P3.1/TXI1 O Ð H(X)/H(Q) Transmit Interrupt output goes active to indicate that

serial channel 1 has completed a transfer. TXI1 is

R(0)

multiplexed with an output only Port function.

I(Q)

P(X)

P3.0/RXI1 O Ð H(X)/H(Q) Receive Interrupt output goes active to indicate that

serial channel 1 has completed a reception. RXI1 is

R(0)

multiplexed with an output only port function.

I(Q)

P(X)

WDTOUT O Ð H(Q) WatchDog Timer OUTput is driven low for four clock

cycles when the watchdog timer reaches zero. WDTOUT

R(1)

may be ANDed with the power-on reset signal to reset the

I(Q)

processor when the watchdog timer is not properly reset.

P(X)

P2.7/CTS1 I/O A(L) H(X) Clear-To-Send input is used to prevent the transmission

of serial data on the TXD signal pin. CTS1

and CTS0 are

P2.3/CTS0

R(Z)

multiplexed with an I/O Port function.

I(X)

P(X)

P2.6/BCLK1 I/O A(L)/ H(X) Baud CLocK input can be used as an alternate clock

source for each of the integrated serial channels. The

P2.2/BCLK0 A(E) R(Z)

BCLK inputs are multiplexed with I/O Port functions. The

I(X)

BCLK input frequency cannot exceed (/2 the operating

P(X)

frequency of the processor .

P2.5/TXD1 I/O A(L) H(Q) Transmit Data output provides serial data information.

The TXD outputs are multiplexed with I/O Port functions.

P2.1/TXD0 R(Z)

During synchronous serial communications, TXD will

I(X)/I(Q)

function as a clock output.

P(X)

P2.4/RXD1 I/O A(L) H(X)/H(Q) Receive Data input accepts serial data information. The

RXD pins are multiplexed with I/O Port functions. During

P2.0/RXD0 R(Z)

synchronous serial communications, RXD is bi-directional

I(X)/I(Q)

and will become an output for transmission of data (TXD

P(X)

becomes the clock).

DRQ3:0 I A(L) Ð DMA ReQuest input pins are used to request a DMA

transfer. The timing of the request is dependent on the
programmed synchronization mode.

NOTES:

1. READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.

2. Pin names in parentheses apply to the 80C188EC/80L188EC.

14

80C186EC/188EC, 80L186EC/188EC

Pinout

Tables 3 and 4 list the pin names with package loca­tion for the 100-pin Plastic Quad Flat Pack (PQFP)
component. Figure 4 depicts the PQFP package as
viewed from the top side of the component (i.e. con­tacts facing down).

Tables 5 and 6 list the pin names with package loca­tion for the 100-pin EIAJ Quad Flat Pack (QFP) com­ponent. Figure 5 depicts the QFP package as viewed

from the top side of the component (i.e. contacts
facing down).

Tables 7 and 8 list the pin names with package loca­tion for the 100-pin Shrink Quad Flat Pack (SQFP)
component. Figure 6 depicts the SQFP package as
viewed from the top side of the component (i.e., con­tacts facing down).

Table 3. PQFP Pin Functions with Location

AD Bus

Name Pin

AD0 73
AD1 72
AD2 71
AD3 70
AD4 66
AD5 65
AD6 64
AD7 63
AD8 (A8) 60
AD9 (A9) 59
AD10 (A10) 58
AD11 (A11) 57
AD12 (A12) 56
AD13/CAS0 55
(A13/CAS0)
AD14/CAS1 54
(A14/CAS1)
AD15/CAS2 53
(A15/CAS2)
A16/S3 77
A17/S4 76
A18/S5 75
A19/S6/ONCE 74

Bus Control

Name Pin

ALE 52
BHE

(RFSH)51

S0

78

S1

79
S2 80
RD 50
WR

49
READY 85
DEN 47
DT/R

46
LOCK

48
HOLD 44
HLDA 45
INTA

34

Power and Ground

Name Pin

V

CC

13

V

CC

14

V

CC

38

V

CC

62

V

CC

67

V

CC

69

V

CC

86

V

SS

12

V

SS

15

V

SS

37

V

SS

39

V

SS

61

V

SS

68

V

SS

87

Processor Control

Name Pin

RESIN 8
RESOUT 7
CLKIN 10
OSCOUT 11
CLKOUT 6
TEST/BUSY 83
(TEST

)

PEREQ (V

SS

)81

NCS

(N.C.) 35

ERROR

(VCC)84
PDTMR 9
NMI 82
INT0 30
INT1 31
INT2 32
INT3 33
INT4 40
INT5 41
INT6 42
INT7 43

I/O

Name Pin

UCS 88
LCS

89

P1.7/GCS7 90
P1.6/GCS6 91
P1.5/GCS5 92
P1.4/GCS4

93

P1.3/GCS3

94

P1.2/GCS2

95

P1.1/GCS1

96

P1.0/GCS0

97

P2.7/CTS1 23
P2.6/BCLK1 22
P2.5/TXD1 21
P2.4/RXD1 20
P2.3/CTS0 19
P2.2/BCLK0 18
P2.1/TXD0 17
P2.0/RXD0 16

P3.5 29
P3.4 28
P3.3/DMAI1 27
P3.2/DMAI0 26
P3.1/TXI1 25
P3.0/RXI1 24

T0IN 3
T0OUT 2
T1IN 5
T1OUT 4

DRQ0 98
DRQ1 99
DRQ2 100
DRQ3 1

WDTOUT 36

15

80C186EC/188EC, 80L186EC/188EC

Table 4. PQFP Pin Locations with Pin Name

Pin Name

1 DRQ3
2 T0OUT
3 T0IN
4 T1OUT
5 T1IN
6 CLKOUT
7 RESOUT
8 RESIN

9 PDTMR
10 CLKIN
11 OSCOUT
12 V

SS

13 V

CC

14 V

CC

15 V

SS

16 P2.0/RXD0
17 P2.1/TXD0
18 P2.2/BCLK0
19 P2.3/CTS0
20 P2.4/RXD1
21 P2.5/TXD1
22 P2.6/BCLK1
23 P2.7/CTS1
24 P3.0/RXI1
25 P3.1/TXI1

Pin Name

26 DMAI0/P3.2
27 DMAI1/P3.3
28 P3.4
29 P3.5
30 INT0
31 INT1
32 INT2
33 INT3
34 INTA
35 NCS (N.C.)
36 WDTOUT
37 V

SS

38 V

CC

39 V

SS

40 INT4
41 INT5
42 INT6
43 INT7
44 HOLD
45 HLDA
46 DT/R
47 DEN
48 LOCK
49 WR
50 RD

Pin Name

51 BHE (RFSH)
52 ALE
53 AD15 (A15)
54 AD14 (A14)
55 AD13 (A13)
56 AD12 (A12)
57 AD11 (A11)
58 AD10 (A10)
59 AD9 (A9)
60 AD8 (A8)
61 V

SS

62 V

CC

63 AD7
64 AD6
65 AD5
66 AD4
67 V

CC

68 V

SS

69 V

CC

70 AD3
71 AD2
72 AD1
73 AD0
74 A19/S6/ONCE
75 A18/S5

Pin Name

76 A17/S4
77 A16/S3
78 S0
79 S1
80 S2
81 PEREQ (VSS)
82 NMI
83 TEST
84 ERROR (VCC)
85 READY
86 V

CC

87 V

SS

88 UCS
89 LCS
90 P1.7/GCS7
91 P1.6/GCS6
92 P1.5/GCS5
93 P1.4/GCS4
94 P1.3/GCS3
95 P1.2/GCS2
96 P1.1/GCS1
97 P1.0/GCS0
98 DRQ0
99 DRQ1

100 DRQ2

16

80C186EC/188EC, 80L186EC/188EC

272434–3

NOTE:

This is the FPO number location (indicated by X’s).

Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)

17

80C186EC/188EC, 80L186EC/188EC

Table 5. QFP Pin Names with Package Location

AD Bus

Name Pin

AD0 76
AD1 75
AD2 74
AD3 73
AD4 69
AD5 68
AD6 67
AD7 66
AD8 (A8) 63
AD9 (A9) 62
AD10 (A10) 61
AD11 (A11) 60
AD12 (A12) 59
AD13/CAS0 58
(A13/CAS0)
AD14/CAS1 57
(A14/CAS1)
AD15/CAS2 56
(A15/CAS2)
A16/S3 80
A17/S4 79
A18/S5 78
A19/S6/ONCE

77

Bus Control

Name Pin

ALE 55
BHE

(RFSH)54

S0

81

S1

82
S2 83
RD 53
WR

52
READY 88
DEN

50
DT/R

49
LOCK

51
HOLD 47
HLDA 48
INTA

37

Power and Ground

Name Pin

V

CC

16

V

CC

17

V

CC

41

V

CC

65

V

CC

70

V

CC

72

V

CC

89

V

SS

15

V

SS

18

V

SS

40

V

SS

42

V

SS

64

V

SS

71

V

SS

90

Processor Control

Name Pin

RESIN 11
RESOUT 10
CLKIN 13
OSCOUT 14
CLKOUT 9
TEST/BUSY 86
(TEST

)

PEREQ (V

SS

)84

NCS

(N.C.) 38

ERROR

(VCC)87
PDTMR 12
NMI 85
INT0 33
INT1 34
INT2 35
INT3 36
INT4 43
INT5 44
INT6 45
INT7 46

I/O

Name Pin

UCS 91
LCS

92

P1.7/GCS7

93
P1.6/GCS6 94
P1.5/GCS5 95
P1.4/GCS4

96
P1.3/GCS3

97
P1.2/GCS2

98
P1.1/GCS1

99
P1.0/GCS0

100

P2.7/CTS1 26
P2.6/BCLK1 25
P2.5/TXD1 24
P2.4/RXD1 23
P2.3/CTS0

22
P2.2/BCLK0 21
P2.1/TXD0 20
P2.0/RXD0 19

P3.5 32
P3.4 31
P3.3/DMAI1 30
P3.2/DMAI0 29
P3.1/TXI1 28
P3.0/RXI1 27

T0IN 6
T0OUT 5
T1IN 8
T1OUT 7

DRQ0 1
DRQ1 2
DRQ2 3
DRQ3 4

WDTOUT

39

18

80C186EC/188EC, 80L186EC/188EC

Table 6. QFP Package Location with Pin Names

Pin Name

1 DRQ0
2 DRQ1
3 DRQ2
4 DRQ3
5 T0OUT
6 T0IN
7 T1OUT
8 T1IN

9 CLKOUT
10 RESOUT
11 RESIN
12 PDTMR
13 CLKIN
14 OSCOUT
15 V

SS

16 V

CC

17 V

CC

18 V

SS

19 P2.0/RXD0
20 P2.1/TXD0
21 P2.2/BCLK0
22 P2.3/CTS0
23 P2.4/RXD1
24 P2.5/TXD1
25 P2.6/BCLK1

Pin Name

26 P2.7/CTS1
27 P3.0/RXI1
28 P3.1/TXI1
29 DMAI0/P3.2
30 DMAI1/P3.3
31 P3.4
32 P3.5
33 INT0
34 INT1
35 INT2
36 INT3
37 INTA
38 NCS (N.C.)
39 WDTOUT
40 V

SS

41 V

CC

42 V

SS

43 INT4
44 INT5
45 INT6
46 INT7
47 HOLD
48 HLDA
49 DT/R
50 DEN

Pin Name

51 LOCK
52 WR
53 RD
54 BHE (RFSH)
55 ALE
56 AD15 (A15)
57 AD14 (A14)
58 AD13 (A13)
59 AD12 (A12)
60 AD11 (A11)
61 AD10 (A10)
62 AD9 (A9)
63 AD8 (A8)
64 V

SS

65 V

CC

66 AD7
67 AD6
68 AD5
69 AD4
70 V

CC

71 V

SS

72 V

CC

73 AD3
74 AD2
75 AD1

Pin Name

76 AD0
77 A19/S6/ONCE
78 A18/S5
79 A17/S4
80 A16/S3
81 S0
82 S1
83 S2
84 PEREQ (VSS)
85 NMI
86 TEST
87 ERROR (VCC)
88 READY
89 V

CC

90 V

SS

91 UCS
92 LCS
93 P1.7/GCS7
94 P1.6/GCS6
95 P1.5/GCS5
96 P1.4/GCS4
97 P1.3/GCS3
98 P1.2/GCS2
99 P1.1/GCS1

100 P1.0/GCS0

19

80C186EC/188EC, 80L186EC/188EC

272434–4

NOTE:

This is the FPO number location (indicated by X’s).

Figure 5. Quad Flat Pack (EIAJ) Pinout Diagram

20

80C186EC/188EC, 80L186EC/188EC

Table 7. SQFP Pin Functions with Location

AD Bus

AD0 73
AD1 72
AD2 71
AD3 70
AD4 66
AD5 65
AD6 64
AD7 63
AD8 (A8) 60
AD9 (A9) 59
AD10 (A10) 58
AD11 (A11) 57
AD12 (A12) 56
AD13 (A13) 55
AD14 (A14) 54
AD15 (A15) 53
A16 77
A17 76
A18 75
A19/ONCE 74

Bus Control

ALE 52
BHE

(RFSH)51

S0

78

S1

79

S2

80
RD 50
WR

49
READY 85
DT/R

46
DEN

47
LOCK

48
HOLD 44
HLDA 45

Processor Control

RESIN 8
RESOUT 7
CLKIN 10
OSCOUT 11
CLKOUT 6
TEST/BUSY 83
NMI 82
INT0 30
INT1 31
INT2 32
INT3 33
INT4 40
INT5 41
INT6 42
INT7 43
INTA

34

PEREQ (V

SS

)81

ERROR

(VCC)84

NCS

(N.C.) 35

PDTMR 9

Power and Ground

V

CC

13

V

CC

14

V

CC

38

V

CC

62

V

CC

67

V

CC

69

V

CC

86

V

SS

12

V

SS

15

V

SS

37

V

SS

39

V

SS

61

V

SS

68

V

SS

87

I/O

UCS 88
LCS

89

P1.0/GCS0 97
P1.1/GCS1

96
P1.2/GCS2 95
P1.3/GCS3

94
P1.4/GCS4 93
P1.5/GCS5

92
P1.6/GCS6

91
P1.7/GCS7

90

P2.0/RXD0 16
P2.1/TXD0 17
P2.2/BCLK0 18
P2.3/CTS0

19
P2.4/RXD1 20
P2.5/TXD1 21
P2.6/BCLK1 22
P2.7/CTS1 23

P3.0/RXI1 24
P3.1/TXI1 25
P3.2/DMAI0 26
P3.3/DMAI1 27
P3.4 28
P3.5 29

DRQ0 98
DRQ1 99
DRQ2 100
DRQ3 1

T0IN 3
T0OUT 2
T1IN 5
T1OUT 4
WDTOUT

36

21

80C186EC/188EC, 80L186EC/188EC

Table 8. SQFP Pin Locations with Pin Names

Pin Name

1 DRQ3
2 T0OUT
3 T0IN
4 T1OUT
5 T1IN
6 CLKOUT
7 RESOUT
8 RESIN

9 PDTMR
10 CLKIN
11 OSCOUT
12 V

SS

13 V

CC

14 V

CC

15 V

SS

16 P2.0/RXD0
17 P2.1/TXD0
18 P2.2/BCLK0
19 P2.3/CTS0
20 P2.4/RXD1
21 P2.5/TXD1
22 P2.6/BCLK1
23 P2.7/CTS1
24 P3.0/RXI1
25 P3.1/TXI1

Pin Name

26 P3.2/DMAI0
27 P3.3/DMAI1
28 P3.4
29 P3.5
30 INT0
31 INT1
32 INT2
33 INT3
34 INTA
35 NSC (N.C.)
36 WDTOUT
37 V

SS

38 V

CC

39 V

SS

40 INT4
41 INT5
42 INT6
43 INT7
44 HOLD
45 HLDA
46 DT/R
47 DEN
48 LOCK
49 WR
50 RD

Pin Name

51 BHE (RFSH)
52 ALE
53 AD15 (A15)
54 AD14 (A14)
55 AD13 (A13)
56 AD12 (A12)
57 AD11 (A11)
58 AD10 (A10)
59 AD9 (A9)
60 AD8 (A8)
61 V

SS

62 V

CC

63 AD7 (A7)
64 AD6 (A6)
65 AD5
66 AD4
67 V

CC

68 V

SS

69 V

CC

70 AD3
71 AD2
72 AD1
73 AD0
74 A19/ONCE
75 AD18

Pin Name

76 A17
77 A16
78 S0
79 S1
80 S2
81 PEREQ (VSS)
82 MNI
83 TEST/BUSY

(TEST

)

84 ERROR

(VCC)
85 READY
86 V

CC

87 V

SS

88 UCS
89 LCS
90 P1.7/GCS7
91 P1.6/GS6
92 P1.5/GCS5
93 P1.4/GCS4
94 P1.3/GCS3
95 P1.2/GCS2
96 P1.1/GCS1
97 P1.0/GCS0
98 DRQ0
99 DRQ1

100 DRQ2

22

80C186EC/188EC, 80L186EC/188EC

272434–5

NOTE:

This is the FPO number location (indicated by X’s)

Figure 6. 100-Pin Shrink Quad Flat Pack Package (SQFP)

23

80C186EC/188EC, 80L186EC/188EC

Package Thermal Specifications

The 80C186EC/80L186EC is specified for operation
when T

C

(the case temperature) is within the range

of

b

40§Ctoa100§C. TCmay be measured in any
environment to determine whether the processor is
within the specified operating range. The case tem­perature must be measured at the center of the top
surface.

T

A

(the ambient temperature) can be calculated

from i

CA

(thermal resistance from the case to ambi-

ent) with the following equation:

T

A

e

T

C

b

P * i

CA

Typical values for iCAat various airflows are given
in Table 9. P (the maximum power consumptionÐ
specified in Watts) is calculated by using the maxi­mum I

CC

and VCCof 5.5V.

Table 9. Thermal Resistance (i

CA

) at Various Airflows (in§C/Watt)

Airflow in ft/min (m/sec)

0 200 400 600 800 1000

(0) (1.01) (2.03) (3.04) (4.06) (5.07)

iCA(PQFP) 27.0 22.0 18.0 15.0 14.0 13.5

iCA(QFP) 64.5 55.5 51.0 TBD TBD TBD

iCA(SQFP) 62.0 TBD TBD TBD TBD TBD

24

80C186EC/188EC, 80L186EC/188EC

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Storage Temperature ААААААААААb65§Ctoa150§C

Case Temperature Under BiasÀÀÀb65§Ctoa100§C

Supply Voltage

with Respect to V

SS

АААААААААААb0.5V toa6.5V

Voltage on Other Pins

with Respect to V

SS

ААААААb0.5V to V

CC

a

0.5V

NOTICE: This data sheet contains preliminary infor­mation on new products in production. The specifica­tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

Recommended Connections

Power and ground connections must be made to
multiple V

CC

and VSSpins. Every 80C186EC-based

circuit board should include separate power (V

CC

)

and ground (V

SS

) planes. Every VCCpin must be

connected to the power plane, and every V

SS

pin
must be connected to the ground plane. Liberal de­coupling capacitance should be placed near the
processor. The processor can cause transient pow­er surges when its output buffers transition, particu­larly when connected to large capacitive loads.

Low inductance capacitors and interconnects are
recommended for best high frequency electrical per­formance. Inductance is reduced by placing the de­coupling capacitors as close as possible to the proc­essor V

CC

and VSSpackage pins.

Always connect any unused input to an appropriate
signal level. In particular, unused interrupt inputs
(NMI, INT0:7) should be connected to V

SS

through a
pull-down resistor. Leave any unused output pin un­connected.

25

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80C186EC/80C188EC)

Symbol Parameter Min Max Units Notes

V

CC

Supply Voltage 4.5 5.5 V

V

IL

Input Low Voltage

b

0.5 0.3 V

CC

V

V

IH

Input High Voltage 0.7 V

CC

V

CC

a

0.5 V

V

OL

Output Low Voltage 0.45 V I

OL

e

3 mA (Min)

V

OH

Output High Voltage V

CC

b

0.5 V I

OH

eb

2 mA (Min)

V

HYR

Input Hysteresis on RESIN 0.5 V

I

LI

Input Leakage Current for Pins:

g

15 mA0

s

V

IN

s

V

CC

AD15:0 (AD7:0, A15:8), READY,
HOLD, RESIN

,

CLKIN, TEST

/BUSY, NMI, INT7:0,
T0IN, T1IN, P2.7 –P2.0, P3.5 –P3.0,
DRQ3:0, PEREQ, ERROR

I

LIU

Input Leakage for Pins with Pullups

b

0.275

b

5mAV

IN

e

0.7 V

CC

Active During Reset: (Note 1)
A19:16, LOCK

I

LO

Output Leakage for Floated Output

g

15 mA 0.45sV

OUT

s

V

CC

Pins (Note 2)

I

CC

Supply Current Cold (in RESET)

80C186EC25 125 mA (Notes 3, 7)
80C186EC20 100 mA (Note 3)
80C186EC13 70 mA (Note 3)

I

ID

Supply Current in Idle Mode

80C186EC25 92 mA (Notes 4, 7)
80C186EC20 76 mA (Note 4)
80C186EC13 50 mA (Note 4)

I

PD

Supply Current in Powerdown Mode

80C186EC25 100 mA (Notes 5, 7)
80C186EC20 100 mA (Note 5)
80C186EC13 100 mA (Note 5)

C

IN

Input Pin Capacitance 0 15 pF T

F

e

1 MHz

C

OUT

Output Pin Capacitance 0 15 pF T

F

e

1 MHz (Note 6)

NOTES:

1. These pins have an internal pull-up device that is active while RESIN

is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V

CC

, and temperature with ALL outputs loaded as

specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V

CC

, and temperature with ALL

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V

CC

, and temperature with

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

6. Output Capacitance is the capacitive load of a floating output pin.

7. Operating conditions for 25 MHz is 0

§

Ctoa70§C, V

CC

e

5.0g10%.

26

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80L186EC13/80L188EC13)

Symbol Parameter Min Max Units Notes

V

CC

Supply Voltage 2.7 5.5 V

V

IL

Input Low Voltage

b

0.5 0.3 V

CC

V

V

IH

Input High Voltage 0.7 V

CC

V

CC

a

0.5 V

V

OL

Output Low Voltage 0.45 V I

OL

e

3 mA (Min)

V

OH

Output High Voltage V

CC

b

0.5 V I

OH

eb

2 mA (Min)

V

HYR

Input Hysteresis on RESIN 0.5 V

I

LI

Input Leakage Current for Pins:

g

15 mA0

s

V

IN

s

V

CC

AD15:0 (AD7:0, A15:8), READY,
HOLD, RESIN

, CLKIN,

TEST

/BUSY, NMI, INT7:0,
T0IN, T1IN, P2.7 –P2.0, P3.5 –P3.0,
DRQ3:0, PEREQ, ERROR

I

LIU

Input Leakage for Pins with Pullups

b

0.275

b

5mAV

IN

e

0.7 V

CC

Active During Reset: (Note 1)
A19:16, LOCK

I

LO

Output Leakage for Floated Output

g

15 mA 0.45sV

OUT

s

V

CC

Pins (Note 2)

I

CC

Supply Current Cold (in RESET) (Note 3)

80L186EC-13 36 mA

I

ID

Supply Current in Idle Mode (Note 4)

80L186EC-13 24 mA

I

PD

Supply Current in Powerdown Mode (Note 5)

80L186EC-13 30 mA

C

IN

Input Pin Capacitance 0 15 pF T

F

e

1 MHz

C

OUT

Output Pin Capacitance 0 15 pF T

F

e

1 MHz (Note 6)

NOTES:

1. These pins have an internal pull-up device that is active while RESIN

is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V

CC

, and temperature with ALL outputs loaded as

specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V

CC

, and temperature with ALL

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V

CC

, and temperature with

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

6. Output Capacitance is the capacitive load of a floating output pin.

27

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80L186EC16/80L188EC16) (Operating Temperature 0

§

Cto70§C)

Symbol Parameter Min Max Units Notes

V

CC

Supply Voltage 3.0 5.5 V

V

IL

Input Low Voltage

b

0.5 0.3 V

CC

V

V

IH

Input High Voltage 0.7 V

CC

V

CC

a

0.5 V

V

OL

Output Low Voltage 0.45 V I

OL

e

3 mA (Min)

V

OH

Output High Voltage V

CC

b

0.5 V I

OH

eb

2 mA (Min)

V

HYR

Input Hysteresis on RESIN 0.5 V

I

LI

Input Leakage Current for Pins:

g

15 mA0

s

V

IN

s

V

CC

AD15:0 (AD7:0, A15:8), READY,
HOLD, RESIN

, CLKIN,

TEST

/BUSY, NMI, INT7:0,
T0IN, T1IN, P2.7 –P2.0, P3.5 –P3.0,
DRQ3:0, PEREQ, ERROR

I

LIU

Input Leakage for Pins with Pullups

b

0.275

b

5mAV

IN

e

0.7 V

CC

Active During Reset: (Note 1)
A19:16, LOCK

I

LO

Output Leakage for Floated Output

g

15 mA 0.45sV

OUT

s

V

CC

Pins (Note 2)

I

CC

Supply Current Cold (in RESET) (Note 3)

80L186EC-16 45 mA

I

ID

Supply Current in Idle Mode (Note 4)

80L186EC-16 35 mA

I

PD

Supply Current in Powerdown Mode (Note 5)

80L186EC-16 50 mA

C

IN

Input Pin Capacitance 0 15 pF T

F

e

1 MHz

C

OUT

Output Pin Capacitance 0 15 pF T

F

e

1 MHz (Note 6)

NOTES:

1. These pins have an internal pull-up device that is active while RESIN

is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V

CC

, and temperature with ALL outputs loaded as

specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V

CC

, and temperature with ALL

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V

CC

, and temperature with

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

6. Output Capacitance is the capacitive load of a floating output pin.

28

80C186EC/188EC, 80L186EC/188EC

ICCversus Frequency and Voltage

The ICCconsumed by the processor is composed of
two components:

1. I

PD

ÐThe quiescent current that represents inter­nal device leakage. Measured with all inputs at
either V

CC

or ground and no clock applied.

2. I

CCS

ÐThe switching current used to charge and
discharge internal parasitic capacitance when
changing logic levels. I

CCS

is related to both the
frequency of operation and the device supply
voltage (V

CC

). I

CCS

is given by the formula:

PowereV * IeV2* C

DEV

* f

... I

CCS

e

V * C

DEV

* f

Where:

VeSupply Voltage (VCC)

C

DEV

e

Device Capacitance

feOperating Frequency

Measuring C

PD

on a device like the 80C186EC

would be difficult. Instead, C

PD

is calculated using

the above formula with I

CC

values measured at

known V

CC

and frequency. Using the CPDvalue, the

user can calculate I

CC

at any voltage and frequency

within the specified operating range.

Example. Calculate typical I

CC

at 14 MHz, 5.2V VCC.

I

CC

e

I

PD

a

I

CCS

e

0.1 mAa5.2V * 0.77 * 14 MHz

e

56.2 mA

PDTMR Pin Delay Calculation

The PDTMR pin provides a delay between the as­sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode. A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize.

NOTE:

The PDTMR pin function does not apply when
RESIN

is asserted (i.e. a device reset while in Pow-

erdown is similar to a cold reset and RESIN

must

remain active until after the oscillator has stabilized.

To calculate the value of capacitor to use to provide
a desired delay, use the equation:

440cteCPD(5V, 25§C)

Where:

t

e

desired delay in seconds

C

PD

e

capacitive load on PDTMR in microfarads

Example. For a delay of 300 ms, a capacitor value of

C

PD

e

440c(300c10

b

6

e

0.132 mF is required.

Round up to a standard (available) capacitor value.

NOTE:

The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci­tance needed to achieve the desired delay. A delay
variance of

a

50% tob25% can occur due to
temperature, voltage, and device process ex­tremes. In general, higher V

CC

and/or lower tem-

peratures will decrease delay time, while lower V

CC

and/or higher temperature will increase delay time.

Parameter Typical Max Units Notes

CPD 0.77 1.37 mA/V*MHz 1, 2

CPD (Idle Mode) 0.55 0.96 mA/V*MHz 1, 2

NOTES:

1. Maximum C

PD

is measured atb40§C with all outputs loaded as specified in the AC test conditions and the device in reset

(or Idle Mode). Due to tester limitations, CLKOUT and OSCOUT also have 50 pF loads that increase I

CC

by V*C*F.

2. Typical C

PD

is calculated at 25§C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode).

29

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC25

Symbol Parameter

25 MHz

Units Notes

Min Max

INPUT CLOCK

T

F

CLKIN Frequency 0 50 MHz 1

T

C

CLKIN Period 20

%

ns 1

T

CH

CLKIN High Time 8

%

ns 1, 2

T

CL

CLKIN Low Time 8

%

ns 1, 2

T

CR

CLKIN Rise Time 1 10 ns 1, 3

T

CF

CLKIN Fall Time 1 10 ns 1, 3

OUTPUT CLOCK

T

CD

CLKIN to CLKOUT Delay 0 17 ns 1, 4

T CLKOUT Period 2*T

C

ns 1

T

PH

CLKOUT High Time (T/2)b5 (T/2)a5ns 1

T

PL

CLKOUT Low Time (T/2)b5 (T/2)a5ns 1

T

PR

CLKOUT Rise Time 1 6 ns 1, 5

T

PF

CLKOUT Fall Time 1 6 ns 1, 5

OUTPUT DELAYS

T

CHOV1

ALE, S2:0, DEN, DT/R, 3 17 ns 1, 4, 6, 7
BHE (RFSH), LOCK, A19:16

T

CHOV2

GCS0:7, LCS, UCS, NCS,RD,WR 3 20 ns 1,4,6,8

T

CLOV1

BHE (RFSH), DEN, LOCK, RESOUT, 3 17 ns 1, 4, 6
HLDA, T0OUT, T1OUT, A19:16

T

CLOV2

RD,WR, GCS7:0, LCS, UCS, AD15:0 3 20 ns 1, 4, 6
(AD7:0, A15:8), NCS

, INTA1:0, S2:0

T

CHOF

RD,WR, BHE (RFSH), DT/R, 0 20 ns 1
LOCK

, S2:0, A19:16

T

CLOF

DEN, AD15:0 (AD7:0, A15:8) 0 20 ns 1

30

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC25

(Continued)

Symbol Parameter

25 MHz

Units Notes

Min Max

SYNCHRONOUS INPUTS

T

CHIS

TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0,10 ns1,9
P2.6, P2.7

T

CHIH

TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0 3ns1,9

T

CLIS

AD15:0 (AD7:0), READY 10 ns 1, 10

T

CLIH

READY, AD15:0 (AD7:0) 3 ns 1, 10

T

CLIS

HOLD, PEREQ, ERROR 10 ns 1, 9

T

CLIH

HOLD, PEREQ, ERROR 3ns1,9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V

IH

for high time, VILfor low time.

3. Only required to guarantee I

CC

. Maximum limits are bounded by TC,TCHand TCL.

4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6. See Figure 14 for rise and fall times.

7. T

CHOV1

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8. T

CHOV2

applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

31

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC-20/80C186EC-13

Symbol Parameter Min Max Min Max Unit Notes

INPUT CLOCK 20 MHz 13 MHz

TF CLKIN Frequency 0 40 0 26 MHz 1
TC CLKIN Period 25

%

38.5

%

ns 1

TCH CLKIN High Time 10

%

12

%

ns 1, 2

TCL CLKIN Low Time 10

%

12

%

ns 1, 2
TCR CLKIN Rise Time 1 10 1 10 ns 1, 3
TCF CLKIN Fall Time 1 10 1 10 ns 1, 3

OUTPUT CLOCK

T

CD

CLKIN to CLKOUT Delay 0 17 0 23 ns 1, 4
T CLKOUT Period 2 * TC 2 * TC ns 1
T

PH

CLKOUT High Time (T/2)b5 (T/2)a5 (T/2)b5 (T/2)a5ns 1
T

PL

CLKOUT Low Time (T/2)b5 (T/2)a5 (T/2)b5 (T/2)a5ns 1
T

PR

CLKOUT Rise Time 1616ns1,5
TPFCLKOUT Fall Time 1616ns1,5

OUTPUT DELAYS

T

CHOV1

ALE, S2:0, DEN, DT/R, 3 20 3 25 ns 1,4,6,7

BHE

(RFSH), LOCK, A19:16

T

CHOV2

GCS7:0, LCS, UCS, 3 23 3 30 ns 1,4,6,8

RD

,WR, NCS, WDTOUT

T

CLOV1

BHE (RFSH), DEN, LOCK, RESOUT, 3 20 3 25 ns 1, 4, 6

HLDA, T0OUT, T1OUT

T

CLOV2

RD,WR, GSC7:0, LCS, UCS, AD15:0 3 23 3 30 ns 1, 4, 6

(AD7:0, A15:8), NCS

, INTA, S2:0, A19:16

T

CHOF

RD,WR, BHE (RFSH), DT/R, LOCK, 025030ns1

S2:0

, A19:16

T

CLOF

DEN, AD15:0 (AD7:0, A15:8) 0 25 0 30 ns 1

INPUT REQUIREMENTS

T

CHIS

TEST, NMI, T1IN, T0IN, READY, 10 10 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CHIH

TEST, NMI, T1IN, T0IN, READY, 3 3 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CLIS

AD15:0 (AD7:0), READY 10 10 ns 1, 10

T

CLIH

AD15:0 (AD7:0), READY 3 3 ns 1, 10

T

CLIS

HOLD, RESIN, PEREQ, ERROR, DRQ3:0 10 10 ns 1, 9

T

CLIH

HOLD, RESIN, REREQ, ERROR, DRQ3:0 3 3 ns 1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V

IH

for high time, VILfor low time.

3. Only required to guarantee I

CC

. Maximum limits are bounded by TC,TCHand TCL.

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

6. See Figure 15 for rise and fall times.

7. T

CHOV1

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8. T

CHOV2

applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

32

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC13

Symbol Parameter Min Max Unit Notes

INPUT CLOCK 13 MHz

T

F

CLKIN Frequency 0 26 MHz 1

T

C

CLKIN Period 38.5

%

ns 1

T

CH

CLKIN High Time 15

%

ns 1, 2

T

CL

CLKIN Low Time 15

%

ns 1, 2

T

CR

CLKIN Rise Time 1 10 ns 1, 3

T

CF

CLKIN Fall Time 1 10 ns 1, 3

OUTPUT CLOCK

T

CD

CLKIN to CLKOUT Delay 0 20 ns 1, 4
T CLKOUT Period 2 * TC ns 1
T

PH

CLKOUT High Time (T/2)b5 (T/2)a5ns 1
T

PL

CLKOUT Low Time (T/2)b5 (T/2)a5ns 1
T

PR

CLKOUT Rise Time 1 10 ns 1, 5
T

PF

CLKOUT Fall Time 1 10 ns 1, 5

OUTPUT DELAYS

T

CHOV1

S2:0, DT/R, BHE, LOCK 3 28 ns 1,4,6,7

T

CHOV2

LCS, UCS, DEN, A19:16, RD,WR, NCS, 3 32 ns 1, 4, 6, 8

WDTOUT, ALE

T

CHOV3

GCS7:0 3 34 ns 1,4,6

T

CLOV1

LOCK, RESOUT, HLDA, T0OUT, T1OUT 3 28 ns 1, 4, 6

T

CLOV2

RD

,WR, AD15:0 (AD7:0, A15:8), BHE

3 32 ns 1,4,6

(RFSH

), NCS, INTA, DEN

T

CLOV3

GSC7:0, LCS, UCS 3 34 ns 1,4,6

T

CLOV4

S2:0, A19:16 3 37 ns 1, 4, 6

T

CHOF

RD,WR, BHE (RFSH), DT/R, LOCK, 0 30 ns 1

S2:0

, A19:16

T

CLOF

DEN, AD15:0 (AD7:0, A15:8) 0 35 ns 1

INPUT REQUIREMENTS

T

CHIS

TEST, NMI, T1IN, T0IN, READY, 20 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CHIH

TEST, NMI, T1IN, T0IN, READY, 3 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CLIS

AD15:0 (AD7:0), READY 20 ns 1, 10

T

CLIH

AD15:0 (AD7:0), READY 3 ns 1, 10

T

CLIS

HOLD, RESIN, PEREQ, ERROR, DRQ3:0 20 ns 1, 9

T

CLIH

HOLD, RESIN, REREQ, ERROR, DRQ3:0 3 ns 1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V

IH

for high time, VILfor low time.

3. Only required to guarantee I

CC

. Maximum limits are bounded by TC,TCHand TCL.

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

33

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC13 (Continued)

NOTES:

6. See Figure 15 for rise and fall times.

7. T

CHOV1

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8. T

CHOV2

applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

AC CharacteristicsÐ80L186EC16 (Operating Temperature 0

§

Cto70§C)

Symbol Parameter Min Max Unit Notes

INPUT CLOCK 16 MHz

T

F

CLKIN Frequency 0 32 MHz 1
T

C

CLKIN Period 31.25

%

ns 1

T

CH

CLKIN High Time 13

%

ns 1, 2

T

CL

CLKIN Low Time 13

%

ns 1, 2

T

CR

CLKIN Rise Time 1 10 ns 1, 3
T

CF

CLKIN Fall Time 1 10 ns 1, 3

OUTPUT CLOCK

T

CD

CLKIN to CLKOUT Delay 0 20 ns 1, 4
T CLKOUT Period 2 * TC ns 1
T

PH

CLKOUT High Time (T/2)b5 (T/2)a5ns 1
T

PL

CLKOUT Low Time (T/2)b5 (T/2)a5ns 1
T

PR

CLKOUT Rise Time 1 9 ns 1, 5
T

PF

CLKOUT Fall Time 1 9 ns 1, 5

OUTPUT DELAYS

T

CHOV1

S2:0, DT/R, BHE, LOCK 3 25 ns 1,4,6,7

T

CHOV2

LCS, UCS, DEN, A19:16, RD,WR, NCS, 3 30 ns 1, 4, 6, 8

WDTOUT, ALE

T

CHOV3

GCS7:0 3 32 ns 1,4,6

T

CLOV1

LOCK, RESOUT, HLDA, T0OUT, T1OUT 3 25 ns 1, 4, 6

T

CLOV2

RD,WR, AD15:0 (AD7:0, A15:8), BHE 3 30 ns 1,4,6

(RFSH

), NCS, INTA, DEN

T

CLOV3

GSC7:0, LCS, UCS 3 32 ns 1,4,6

T

CLOV4

S2:0, A19:16 3 34 ns 1, 4, 6

T

CHOF

RD,WR, BHE (RFSH), DT/R, LOCK, 0 28 ns 1

S2:0

, A19:16

T

CLOF

DEN, AD15:0 (AD7:0, A15:8) 0 32 ns 1

INPUT REQUIREMENTS

T

CHIS

TEST, NMI, T1IN, T0IN, READY, 15 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CHIH

TEST, NMI, T1IN, T0IN, READY, 3 ns 1, 9

CTS1:0

, BCLK1:0, P3.4, P3.5

T

CLIS

AD15:0 (AD7:0), READY 15 ns 1, 10

T

CLIH

AD15:0 (AD7:0), READY 3 ns 1, 10

T

CLIS

HOLD, RESIN, PEREQ, ERROR, DRQ3:0 15 ns 1, 9

T

CLIH

HOLD, RESIN, PEREQ, ERROR, DRQ3:0 3 ns 1, 9

34

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC16 (Continued)

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V

IH

for high time, VILfor low time.

3. Only required to guarantee I

CC

. Maximum limits are bounded by TC,TCHand TCL.

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

6. See Figure 15 for rise and fall times.

7. T

CHOV1

applies to BHE (RFSH

), LOCK and A19:16 only after a HOLD release.

8. T

CHOV2

applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)

Symbol Parameter Min Max Unit Notes

RELATIVE TIMINGS

T

LHLL

ALE Active Pulse Width Tb15 ns

T

AVLL

AD Valid Setup before ALE Falls (/2Tb10 ns

T

PLLL

Chip Select Valid before ALE Falls (/2Tb10 ns 1

T

LLAX

AD Hold after ALE Falls (/2Tb10 ns

T

LLWL

ALE Falling to WR Falling (/2Tb15 ns 1

T

LLRL

ALE Falling to RD Falling (/2Tb15 ns 1

T

WHLH

WR Rising to Next ALE Rising (/2Tb10 ns 1

T

AFRL

AD Float to RD Falling 0 ns

T

RLRH

RD Active Pulse Width 2Tb5ns2

T

WLWH

WR Active Pulse Width 2Tb5ns2

T

RHAX

RD Rising to Next Address Active Tb15 ns

T

WHDX

Output Data Hold after WR Rising Tb15 ns

T

WHPH

WR Rise to Chip Select Rise (/2Tb10 ns 1

T

RHPH

RD Rise to Chip Select Rise (/2Tb10 ns 1

T

PHPL

Chip Select Inactive to Next Chip (/2Tb10 ns 1
Select Active

T

OVRH

ONCE Active Setup to RESIN Rising T ns

T

RHOX

ONCE Hold after RESIN Rise T ns

T

IHIL

INTA High to Next INTA Low 4Tb5ns4
during INTA Cycle

T

ILIH

INTA Active Pulse Width 2Tb5ns2,4

T

CVIL

CAS2:0 Setup before 2nd INTA 8T ns 2, 4
Pulse Low

T

ILCX

CAS2:0 Hold after 2nd INTA Pulse Low 4T ns 2, 4

T

IRES

Interrupt Resolution Time 150 ns 3

T

IRLH

IR Low Time to Reset Edge Detector 50 ns

T

IRHIF

IR Hold Time after 1st INTA Falling 25 ns 4, 5

35

80C186EC/188EC, 80L186EC/188EC

Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)

NOTES:

1. Assumes equal loading on both pins.

2. Can be extended using wait states.

3. Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active. This is not directly measureable by the user. For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the T

IRES

value since the signal must pass through two 8259A

modules.

4. See INTA Cycle Waveforms for definition.

5. To guarantee interrupt is not spurious.

Serial Port Mode 0 Timings (80C186EC-25/20/13, 80L186EC-16/13)

Symbol Parameter Min Max Unit Notes

RELATIVE TIMINGS

T

XLXL

TXD Clock Period T (na1) ns 1, 2

T

XLXH

TXD Clock Low to Clock High (Nl1) 2Tb35 2Ta35 ns 1

T

XLXH

TXD Clock Low to Clock High (Ne1) Tb35 Ta35 ns 1

T

XHXL

TXD Clock High to Clock Low (Nl1) (nb1) Tb35 (nb1) Ta35 ns 1, 2

T

XHXL

TXD Clock High to Clock Low (Ne1) Tb35 Ta35 ns 1

T

QVXH

RXD Output Data Setup to TXD (nb1)Tb35 ns 1, 2
Clock High (N

l

1)

T

QVXH

RXD Output Data Setup to TXD Tb35 ns 1
Clock High (N

e

1)

T

XHQX

RXD Output Data Hold after TXD 2Tb35 ns 1
Clock High (N

l

1)

T

XHQX

RXD Output Data Hold after TXD Tb35 ns 1
Clock High (N

e

1)

T

XHQZ

RXD Output Data Float after Last Ta20 ns 1
TXD Clock High

T

DVXH

RXD Input Data Setup to TXD Ta20 ns 1
Clock High

T

XHDX

RXD Input Data Setup after TXD 0 ns 1
Clock High

NOTES:

1. See Figure 13 for Waveforms.

2. n is the value in the BxCMP register ignoring the ICLK bit.

36

80C186EC/188EC, 80L186EC/188EC

AC TEST CONDITIONS

The AC specifications are tested with the 50 pF load
shown in Figure 7. See the Derating Curves section
to see how timings vary with load capacitance.

Specifications are measured at the V

CC

/2 crossing
point, unless otherwise specified. See AC Timing
Waveforms for AC specification definitions, test pins
and illustrations.

272434–6

C

L

e

50 pF for all signals

Figure 7. AC Test Load

AC TIMING WAVEFORMS

272434–7

Figure 8. Input and Output Clock Waveforms

37

80C186EC/188EC, 80L186EC/188EC

272434–8

Figure 9. Output Delay and Float Waveforms

272434–9

Figure 10. Input Setup and Hold

272434–10

Figure 11. Relative Interrupt Signal Timings

38

80C186EC/188EC, 80L186EC/188EC

272434–11

Figure 12. Relative Signal Waveform

272434–12

Figure 13. Serial Port Mode 0 Waveform

39

80C186EC/188EC, 80L186EC/188EC

DERATING CURVES

272434–13

Figure 14. Typical Output Delay Variations versus Load Capacitance

272434–14

Figure 15. Typical Rise and Fall Variations versus Load Capacitance

RESET

The processor will perform a reset operation any
time the RESIN

pin is active. The RESIN pin is syn­chronized before it is presented internally, which
means that the clock must be operating before a
reset can take effect. From a power-on state, RESIN
must be held active (low) in order to guarantee cor­rect initialization of the processor. Failure to pro-

vide RESIN

while the device is powering up will

result in unspecified operation of the device.

Figure 16 shows the correct reset sequence when
first applying power to the processor. An external
clock connected to CLKIN must not exceed the V

CC

threshold being applied to the processor. This is nor­mally not a problem if the clock driver is supplied
with the same V

CC

that supplies the processor.

When attaching a crystal to the device, RESIN

must

remain active until both V

CC

and CLKOUT are stable
(the length of time is application specific and de­pends on the startup characteristics of the crystal
circuit). The RESIN

pin is designed to operate cor-

rectly using a RC reset circuit, but the designer must
ensure that the ramp time for V

CC

is not so long that

RESIN

is never sampled at a logic low level when

V

CC

reaches minimum operating conditions.

Figure 17 shows the timing sequence when RESIN
is applied after VCCis stable and the device has
been operating. Note that a reset will terminate all
activity and return the processor to a known operat­ing state. Any bus operation that is in progress at the
time RESIN is asserted will terminate immediately
(note that most control signals will be driven to their
inactive state first before floating).

While RESIN

is active, bus signals LOCK,

A19/S16/ONCE

and A18:16 are configured as in­puts and weakly held high by internal pullup transis­tors. Only A19/ONCE

can be overdriven to a low
and is used to enable the ONCE Mode. Forcing
LOCK

or A18:16 low at any time while RESIN is low
is prohibited and will cause unspecified device oper­ation.

40

80C186EC/188EC, 80L186EC/188EC

Figure 16. Cold RESET Waveforms

272434–15

NOTE:

CLKOUT synchronization occurs on the rising edge of RESIN

. If RESIN is sampled high while CLKOUT is high (solid line), then CLKOUT will remain low for two CLKIN

periods. If RESIN

is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.

Pin names in parentheses apply to 80C188EC/80L188EC.

41

80C186EC/188EC, 80L186EC/188EC

Figure 17. Warm RESET Waveforms

272434–16

NOTE:

CLKOUT synchronization occurs on the rising edge of RESIN

. If RESIN is sampled high while CLKOUT is high (solid line), then CLKOUT will remain low for two CLKIN

periods. If RESIN

is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.

Pin names in parentheses apply to 80C188EC/80L188EC.

42

80C186EC/188EC, 80L186EC/188EC

BUS CYCLE WAVEFORMS

Figures 18 through 24 present the various bus cy­cles that are generated by the processor. What is
shown in the figure is the relationship of the various

bus signals to CLKOUT. These figures along with
the information present in AC Specifications allow
the user to determine all the critical timing analysis
needed for a given application.

272434–17

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 18. Memory Read, I/O Read, Instruction Fetch and Refresh Waveforms

43

80C186EC/188EC, 80L186EC/188EC

272434–18

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 19. Memory Write and I/O Write Cycle Waveforms

44

80C186EC/188EC, 80L186EC/188EC

272434–19

NOTES:

1. Address information is invalid. If previous bus cycle was a read, then the AD15:0 (AD7:0) lines will float during T1.
Otherwise, the AD15:0 (AD7:0) lines will continue to drive during T1 (data is invalid). All other control lines are in their
inactive state.

2. All address lines drive zeros while in Powerdown or Idle Mode.

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 20. Halt Cycle Waveforms

45

80C186EC/188EC, 80L186EC/188EC

272434–20

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 21. Interrupt Acknowledge Cycle Waveforms

46

80C186EC/188EC, 80L186EC/188EC

272434–21

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 22. HOLD/HLDA Cycle Waveforms

47

80C186EC/188EC, 80L186EC/188EC

272434–22

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 23. Refresh during HLDA Waveforms

48

80C186EC/188EC, 80L186EC/188EC

272434–23

NOTES:

1. READY must be low by either edge to cause a wait state.

2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 24. READY Cycle Waveforms

49

80C186EC/188EC, 80L186EC/188EC

80C186EC/80C188EC EXECUTION
TIMINGS

A determination of program execution timing must
consider the bus cycles necessary to prefetch in­structions as well as the number of execution unit
cycles necessary to execute instructions. The fol­lowing instruction timings represent the minimum
execution time in clock cycles for each instruction.
The timings given are based on the following as­sumptions:

#

The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.

#

No wait states or bus HOLDs occur.

#

All word-data is located on even-address bound­aries (80C186EC only).

All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.

All instructions which involve memory accesses can
require one or two additional clocks above the mini­mum timings shown due to the asynchronous hand­shake between the bus interface unit (BIU) and exe­cution unit.

With a 16-bit BIU, the 80C186EC has sufficient bus
performance to ensure that an adequate number of
prefetched bytes will reside in the queue (6 bytes)
most of the time. Therefore, actual program execu­tion time will not be substantially greater than that
derived from adding the instruction timings shown.

The 80C188EC 8-bit BIU is limited in its performance
relative to the execution unit. A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time. Therefore, actual
program execution time will be substantially greater
than that derived from adding the instruction timings
shown.

50

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY

Function Format

80C186EC 80C188EC

Comments

Clock Clock

Cycles Cycles

DATA TRANSFER
MOV

e

Move:

Register to Register/Memory 1000100w modreg r/m 2/12 2/12*

Register/memory to register 1000101w modreg r/m 2/9 2/9*

Immediate to register/memory 1100011w mod000 r/m data data if we1 12/13 12/13 8/16-bit

Immediate to register 1011w reg data data if we1 3/4 3/4 8/16-bit

Memory to accumulator 1010000w addr-low addr-high 8 8*

Accumulator to memory 1010001w addr-low addr-high 9 9*

Register/memory to segment register 10001110 mod0reg r/m 2/9 2/13

Segment register to register/memory 10001100 mod0reg r/m 2/11 2/15

PUSHePush:

Memory 11111111 mod110 r/m 16 20

Register 01010 reg 10 14

Segment register 000reg110 9 13

Immediate 011010s0 data data if se01014

PUSHAePush All 01100000 36 68

POPePop:

Memory 10001111 mod000 r/m 20 24

Register 01011 reg 10 14

Segment register 000reg111 (regi01) 8 12

POPAePopAll 01100001 51 83

XCHGeExchange:

Register/memory with register 1000011w modreg r/m 4/17 4/17*

Register with accumulator 10010 reg 3 3

INeInput from:

Fixed port 1110010w port 10 10*

Variable port 1110110w 8 8*

OUTeOutput to:

Fixed port 1110011w port 9 9*

Variable port 1110111w 7 7*

XLATeTranslate byte to AL 11010111 11 15

LEAeLoad EA to register 10001101 modreg r/m 6 6

LDSeLoad pointer to DS 11000101 modreg r/m (modi11) 18 26

LESeLoad pointer to ES 11000100 modreg r/m (modi11) 18 26

LAHFeLoad AH with flags 10011111 2 2

SAHFeStore AH into flags 10011110 3 3

PUSHFePush flags 10011100 9 13

POPFePop flags 10011101 8 12

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

51

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

Function Format

80C186EC 80C188EC

Comments

Clock Clock

Cycles Cycles

DATA TRANSFER (Continued)
SEGMENT

e

Segment Override:

CS 00101110 2 2

SS 00110110 2 2

DS 00111110 2 2

ES 00100110 2 2

ARITHMETIC
ADD

e

Add:

Reg/memory with register to either 000000dw modreg r/m 3/10 3/10*

Immediate to register/memory 100000sw mod000 r/m data data if s we01 4/16 4/16*

Immediate to accumulator 0000010w data data if we1 3/4 3/4 8/16-bit

ADCeAdd with carry:

Reg/memory with register to either 000100dw modreg r/m 3/10 3/10*

Immediate to register/memory 100000sw mod010 r/m data data if s we01 4/16 4/16*

Immediate to accumulator 0001010w data data if we1 3/4 3/4 8/16-bit

INCeIncrement:

Register/memory 1111111w mod000 r/m 3/15 3/15*

Register 01000 reg 3 3

SUBeSubtract:

Reg/memory and register to either 001010dw modreg r/m 3/10 3/10*

Immediate from register/memory 100000sw mod101 r/m data data if s we01 4/16 4/16*

Immediate from accumulator 0010110w data data if we1 3/4 3/4* 8/16-bit

SBBeSubtract with borrow:

Reg/memory and register to either 000110dw modreg r/m 3/10 3/10*

Immediate from register/memory 100000sw mod011 r/m data data if s we01 4/16 4/16*

Immediate from accumulator 0001110w data data if we1 3/4 3/4* 8/16-bit

DECeDecrement

Register/memory 1111111w mod001 r/m 3/15 3/15*

Register 01001 reg 3 3

CMPeCompare:

Register/memory with register 0011101w modreg r/m 3/10 3/10*

Register with register/memory 0011100w modreg r/m 3/10 3/10*

Immediate with register/memory 100000sw mod111 r/m data data if s we01 3/10 3/10*

Immediate with accumulator 0011110w data data if we1 3/4 3/4 8/16-bit

NEGeChange sign register/memory 1111011w mod011 r/m 3/10 3/10*

AAAeASCII adjust for add 00110111 8 8

DAAeDecimal adjust for add 00100111 4 4

AASeASCII adjust for subtract 00111111 7 7

DASeDecimal adjust for subtract 00101111 4 4

MULeMultiply (unsigned): 1111011w mod100 r/m

Register-Byte 26–28 26–28
Register-Word 35–37 35–37
Memory-Byte 32–34 32–34
Memory-Word 41–43 41–43*

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

52

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

Function Format

80C186EC 80C188EC

Comments

Clock Clock

Cycles Cycles

ARITHMETIC (Continued)

IMULeInteger multiply (signed): 1111011w mod101 r/m

Register-Byte 25–28 25–28
Register-Word 34–37 34–37
Memory-Byte 31–34 32–34
Memory-Word 40–43 40–43*

IMULeInteger Immediate multiply 011010s1 modreg r/m data data if se0 22 – 25/ 22–25/

(signed)

29–32 29–32

DIVeDivide (unsigned): 1111011w mod110 r/m

Register-Byte 29 29
Register-Word 38 38
Memory-Byte 35 35
Memory-Word 44 44*

IDIVeInteger divide (signed): 1111011w mod111 r/m

Register-Byte 44–52 44–52
Register-Word 53–61 53–61
Memory-Byte 50–58 50–58
Memory-Word 59–67 59–67*

AAMeASCII adjust for multiply 11010100 00001010 19 19

AADeASCII adjust for divide 11010101 00001010 15 15

CBWeConvert byte to word 10011000 2 2

CWDeConvert word to double word 10011001 4 4

LOGIC
Shift/Rotate Instructions:

Register/Memory by 1 1101000w modTTTr/m 2/15 2/15

Register/Memory by CL 1101001w modTTTr/m 5an/17an5an/17an

Register/Memory by Count 1100000w modTTTr/m count

5an/17an5an/17an

TTT Instruction

000 ROL
001 ROR
010 RCL
011 RCR
1 0 0 SHL/SAL
101 SHR
111 SAR

AND

e

And:

Reg/memory and register to either 001000dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod100 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0010010w data data if we1 3/4 3/4* 8/16-bit

TESTeAnd function to flags, no result:

Register/memory and register 1000010w modreg r/m 3/10 3/10

Immediate data and register/memory 1111011w mod000 r/m data data if we1 4/10 4/10*

Immediate data and accumulator 1010100w data data if we1 3/4 3/4 8/16-bit

OReOr:

Reg/memory and register to either 000010dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod001 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0000110w data data if we1 3/4 3/4* 8/16-bit

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

53

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

Function Format

80C186EC 80C188EC

Comments

Clock Clock

Cycles Cycles

LOGIC (Continued)
XOR

e

Exclusive or:

Reg/memory and register to either 001100dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod110 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0011010w data data if we1 3/4 3/4 8/16-bit

NOTeInvert register/memory 1111011w mod010 r/m 3/10 3/10*

STRING MANIPULATION

MOVSeMove byte/word 1010010w 14 14*

CMPSeCompare byte/word 1010011w 22 22*

SCASeScan byte/word 1010111w 15 15*

LODSeLoad byte/wd to AL/AX 1010110w 12 12*

STOSeStore byte/wd from AL/AX 1010101w 10 10*

INSeInput byte/wd from DX port 0110110w 14 14

OUTSeOutput byte/wd to DX port 0110111w 14 14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

MOVSeMove string 11110010 1010010w 8a8n 8a8n*

CMPSeCompare string 1111001z 1010011w 5a22n 5a22n*

SCASeScan string 1111001z 1010111w 5a15n 5a15n*

LODSeLoad string 11110010 1010110w 6a11n 6a11n*

STOSeStore string 11110010 1010101w 6a9n 6a9n*

INSeInput string 11110010 0110110w 8a8n 8a8n*

OUTSeOutput string 11110010 0110111w 8a8n 8a8n*

CONTROL TRANSFER

CALL

e

Call:

Direct within segment 11101000 disp-low disp-high 15 19

Register/memory 11111111 mod010 r/m 13/19 17/27
indirect within segment

Direct intersegment 10011010 segment offset 23 31

segment selector

Indirect intersegment 11111111 mod011 r/m (modi11) 38 54

JMPeUnconditional jump:

Short/long 11101011 disp-low 14 14

Direct within segment 11101001 disp-low disp-high 14 14

Register/memory 11111111 mod100 r/m 11/17 11/21
indirect within segment

Direct intersegment 11101010 segment offset 14 14

segment selector

Indirect intersegment 11111111 mod101 r/m (modi11) 26 34

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

54

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

Function Format

80C186EC 80C188EC

Comments

Clock Clock

Cycles Cycles

CONTROL TRANSFER (Continued)
RET

e

Return from CALL:

Within segment 11000011 16 20

Within seg adding immed to SP 11000010 data-low data-high 18 22

Intersegment 11001011 22 30

Intersegment adding immediate to SP 11001010 data-low data-high 25 33

JE/JZeJump on equal/zero 01110100 disp 4/13 4/13 JMP not

JL/JNGEeJump on less/not greater or equal 01111100 disp 4/13 4/13

taken/JMP

JLE/JNGeJump on less or equal/not greater 01111110 disp 4/13 4/13

taken

JB/JNAEeJump on below/not above or equal 01110010 disp 4/13 4/13

JBE/JNAeJump on below or equal/not above 01110110 disp 4/13 4/13

JP/JPEeJump on parity/parity even 01111010 disp 4/13 4/13

JOeJump on overflow 01110 000 disp 4/13 4/13

JSeJump on sign 01111000 disp 4/13 4/13

JNE/JNZeJump on not equal/not zero 01110101 disp 4/13 4/13

JNL/JGEeJump on not less/greater or equal 01111101 disp 4/13 4/13

JNLE/JGeJump on not less or equal/greater 01111111 disp 4/13 4/13

JNB/JAEeJump on not below/above or equal 01110011 disp 4/13 4/13

JNBE/JAeJump on not below or equal/above 01110111 disp 4/13 4/13

JNP/JPOeJump on not par/par odd 01111011 disp 4/13 4/13

JNOeJump on not overflow 01110001 disp 4/13 4/13

JNSeJump on not sign 01111001 disp 4/13 4/13

JCXZeJump on CX zero 11100011 disp 5/15 5/15

LOOPeLoop CX times 11100010 disp 6/16 6/16 LOOP not

LOOPZ/LOOPEeLoop while zero/equal 11100001 disp 6/16 6/16

taken/LOOP

LOOPNZ/LOOPNEeLoop while not zero/equal 11100000 disp 6/16 6/16

taken

ENTEReEnter Procedure 11001000 data-low data-high L

Le0 15 19
L

e

1 25 29

L

l

1

22a16(nb1) 26a20(nb1)

LEAVEeLeave Procedure 11001001 8 8

INTeInterrupt:

Type specified 11001101 type 47 47

Type 3 11001100 45 45

if INT. taken/

INTOeInterrupt on overflow 11001110 48/4 48/4

if INT. not

taken

IRETeInterrupt return 11001111 28 28

BOUNDeDetect value out of range 01100010 modreg r/m 33–35 33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

55

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC 80C188EC

Function Format Clock Clock Comments

Cycles Cycles

PROCESSOR CONTROL

CLCeClear carry 11111000 2 2

CMCeComplement carry 11110101 2 2

STCeSet carry 11111001 2 2

CLDeClear direction 11111100 2 2

STDeSet direction 11111101 2 2

CLIeClear interrupt 11111010 2 2

STIeSet interrupt 11111011 2 2

HLTeHalt 11110100 2 2

WAITeWait 10011011 6 6 ifTESTe0

LOCKeBus lock prefix 11110000 2 2

NOPeNo Operation 10010000 3 3

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:

if mod

e

11 then r/m is treated as a REG field

if mod

e

00 then DISPe0*, disp-low and disp­high are absent

if mod

e

01 then DISPedisp-low sign-extended
to 16-bits, disp-high is absent

if mod

e

10 then DISPedisp-high: disp-low

if r/m

e

000 then EAe(BX)a(SI)aDISP

if r/m

e

001 then EAe(BX)a(DI)aDISP

if r/m

e

010 then EAe(BP)a(SI)aDISP

if r/m

e

011 then EAe(BP)a(DI)aDISP

if r/m

e

100 then EAe(SI)aDISP

if r/m

e

101 then EAe(DI)aDISP

if r/m

e

110 then EAe(BP)aDISP*

if r/m

e

111 then EAe(BX)aDISP

DISP follows 2nd byte of instruction (before data if
required)

*except if mod

e

00 and r/me110 then EA

e

disp-high: disp-low.

EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenev­er appropriate.

Segment Override Prefix

0 0 1 reg 1 1 0

reg is assigned according to the following:

Segment

reg Register

00 ES
01 CS
10 SS
11 DS

REG is assigned according to the following table:

16-Bit (w

e

1) 8-Bit (we0)

000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed
by the BP register are computed using the SS seg­ment register. The physical addresses of the desti­nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.

56

80C186EC/188EC, 80L186EC/188EC

ERRATA

An 80C186EC/80L186EC with a STEPID value of
0002H has no known errata. A device with a STEPID
of 0002H can be visually identified by noting the
presence of an ‘‘A’’ or ‘‘B’’ alpha character next to
the FPO number or the absence of any alpha char­acter. The FPO number location is shown in Figures
4, 5 and 6.

REVISION HISTORY

This data sheet replaces the following data sheets:

272072-003 80C186EC

272076-003 80C188EC

272332-001 80L186EC

272333-001 80L188EC

272373-001 SB80C188EC/SB80L188EC

272372-001 SB80C186EC/SB80L186EC

57