Datasheet TSA5521T-C3, TSA5521T-C3-M1, TSA5521M-C4, TSA5521M-C3-R1, TSA5521M-C3 Datasheet (Philips)

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Page 1
DATA SH EET
Product specification Supersedes data of 1995 Mar 16 File under Integrated Circuits, IC02
1996 Oct 10
INTEGRATED CIRCUITS
TSA5520; TSA5521
1.3 GHz universal bus-controlled TV synthesizer
Page 2
1996 Oct 10 2
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
FEATURES
Complete 1.3 GHz single chip system
Four PNP band switch buffers (40 mA)
33 V output tuning voltage
In-lock detector
15-bit programmable divider
Programmable reference divider ratio
(512, 640 or 1024)
Programmable charge-pump current (60 or 280 µA)
Varicap drive disable
Universal bus protocol I
2
C-bus or 3-wire bus (the TSA5520/TSA5521 I2C-bus mode only includes the write mode; if both read and write modes are required the TSA5526/TSA5527 devices should be selected):
– bus protocol for 18 or 19 bits transmission
(3-wire bus)
– extra protocol for 27 bits for test and features
(3-wire bus) – address plus 4 data bytes transmission (I2C-bus) – three independent I2C-bus addresses
Low power and low radiation.
APPLICATIONS
TV tuners and front ends
VCR tuners.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TSA5520M SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5520T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSA5521M SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5521T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Page 3
1996 Oct 10 3
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
QUICK REFERENCE DATA
Notes
1. One band switch buffer ON with 40 mA.
2. One buffer ON, I
o
= 40 mA; two buffers ON, maximum sum of Io= 50 mA.
3. The power dissipation is calculated as follows:
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CC1
supply voltage (+5 V) 4.5 5.5 V
V
CC2
band switch supply voltage (12 V) V
CC1
12 13.5 V
I
CC1
supply current 20 25 mA
I
CC2
band switch supply current note 1 50 55 mA
f
RF
RF input frequency 64 1300 MHz
V
i(RF)
RF input voltage 80 to 150 MHz 25 +3 dBm
150 MHz to 1 GHz 28 +3 dBm 1 to 1.3 GHz 15 +3 dBm
f
xtal
crystal oscillator input frequency 3.2 4.0 4.48 MHz
I
o(PNP)
PNP band switch buffers output current note 2 4 50 mA
P
tot
total power dissipation note 3 250 400 mW
T
stg
IC storage temperature 40 +150 °C
T
amb
operating ambient temperature 20 +85 °C
P
D
V
CC1ICC1VCC2ICC2Io
()I
o
V
CE satPNP()
V33 2()
2
27 k+×+×+×=
Page 4
1996 Oct 10 4
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Table 1 Differences between TSA5520 and TSA5521
Notes
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
TYPE NUMBER DATA WORD REFERENCE DIVIDER FREQUENCY STEP (kHz)
TSA5520 18-bit 512
(1)
62.5
TSA5520 19-bit 1024
(1)
31.25
TSA5521 18-bit or 19-bit 640
(2)
50
The device has three independent I2C-bus addresses which can be selected by applying a specific voltage on the CE input (see Table 5). The general address C2 is always valid. When the I2C-bus format is fully used, TSA5520 and TSA5521 are equal.
3-wire bus format (SW = V
CC1
or open-circuit)
Data is transmitted to the device during a HIGH level on the CE input (enable line pin 15). The device is compatible with 18-bit and 19-bit data formats. The first four bits are used to program the PNP band switch buffers and the remaining bits are used to control the programmable divider. A 27-bit data format may also be used to set the charge-pump current, the reference divider ratio and for test purposes. The difference between TSA5520 and TSA5521 are given in Table 1.
When the 27-bit format is used, the TSA5520 and TSA5521 are equal and the reference divider is controlled by the RSA and RSB bits (see Table 7). More details are given in Chapter “Functional description” Section “3-wire bus mode (SW = open-circuit or V
CC1
); see
Figs 3, 4 and 5”.
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output. Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal. The lock detector output is LOW when the PLL loop is
locked. In the test mode, this output is used as a test output for f
ref
and 1/2f
div
(see Table 6). The device can be controlled in accordance with the I2C-bus format or the 3-wire bus format depending on the voltage applied to the SW input (see Table 2).
I
2
C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four PNP band switch buffers, set the charge-pump current and the reference divider ratio.
Page 5
1996 Oct 10 5
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MKA965
8
BS17BS26BS35BS4
4-BIT BAND SWITCH
REGISTER
GATE
7-BIT CONTROL
REGISTER
15-BIT FREQUENCY
REGISTER
IN-LOCK
DETECTOR
LOCK
DIGITAL
PHASE
COMPARATOR
RSA,RSB
T2,T1,T0
11
15
14
13
SCL
SDA
CE
I C/3-WIRE BUS
RECEIVER
2
T2,T1,T0
AMP
CHARGE
PUMP
9
10
LOGIC
V
CC1
V
EE
3
2
12
LOCK
4
V
CC2
SW
POWER-ON
RESET
XTAL
OSCILLATOR
DIVIDER
512/640/1024
RSA
AMP
RSB
XTAL
16
OS
CP
CP
PRESCALER
DIVIDE-BY-8
1
RF
15-BIT
PROGRAMMABLE
DIVIDER
f
div
f
ref
TSA5520 TSA5521
V
tune
Page 6
1996 Oct 10 6
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
PINNING
SYMBOL PIN DESCRIPTION
RF 1 RF signal input V
EE
2 ground
V
CC1
3 supply voltage (+5 V)
V
CC2
4 band switch supply voltage (+12 V) BS4 5 PNP band switch buffer output 4 BS3 6 PNP band switch buffer output 3 BS2 7 PNP band switch buffer output 2 BS1 8 PNP band switch buffer output 1 CP 9 charge-pump output V
tune
10 tuning voltage output
SW 11 bus format selection input, I
2
C-bus or
3-wire LOCK 12 lock detector output SCL 13 serial clock input SDA 14 serial data input/output CE 15 chip enable/address selection input XTAL 16 crystal oscillator input
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are Chip Enable (CE), serial data input (SDA) and serial clock input (SCL). A LOW level on the SW input enables the I2C-bus inputs which are CE [Address Selection (AS) input], serial data input/output (SDA) and serial clock input (SCL). The bus format selection is given in Table 2.
I
2
C-bus mode (SW = LOW); see Table 3
Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus receiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes).
The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3.
The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and band switch data (first bit = 1) will follow. Until an I
2
C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB).
I
2
C-bus address selection
The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input.
The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 5.
Page 7
1996 Oct 10 7
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Table 2 Bus format selection
Table 3 I
2
C-bus data format
Table 4 Description of Table 3
PIN NAME 3-WIRE BUS MODE I
2
C BUS MODE
11 SW open or HIGH LOW 13 SCL clock input SCL input 14 SDA data input SDA input/output 15 CE chip enable input address selection input
BYTE MSB DATA BYTE LSB SLAVE ANSWER
Address Byte (ADB) 1 1 0 0 0 MA1 MA0 0 A Divider Byte 1 (DB1) 0 N14 N13 N12 N11 N10 N9 N8 A Divider Byte 2 (DB2) N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte (CB) 1 CP T2 T1 T0 RSA RSB OS A Band switch Byte (BB) XXXXBS4BS3BS2BS1 A
SYMBOL DESCRIPTION
A acknowledge MA1 and MA0 programmable address bits (see Table 5) N14 to N0 programmable divider bits; N = N14 × 2
14
+ N13 × 213+ ... + N1 × 2+N0 CP charge-pump current; CP = 0 = 60 µA; CP = 1 = 280 µA T2 to T0 test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 RSA and RSB reference divider ratio select bits (see Table 7) OS tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON;
when OS = 1 tuning voltage is OFF (high impedance)
BS4 to BS1 PNP band switch buffers control bits; when BS
n
= 0 buffer n is OFF;
when BSn= 1 buffer n is ON
X don’t care
Table 5 I2C-bus address selection
VOLTAGE APPLIED TO THE
CE INPUT (SW = LOW)
MA1 MA0
0 to 0.1V
CC1
00
Always valid 0 1
0.4V
CC1
to 0.6V
CC1
10
0.9V
CC1
to V
CC1
11
Page 8
1996 Oct 10 8
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
3-wire bus mode (SW = open-circuit or V
CC1
);
see Figs 3, 4 and 5 During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the clock pulse. The first four bits control the band switch buffers and are loaded into the internal band switch register on the 5th rising edge of the clock pulse. The frequency bits are loaded into the frequency register at the HIGH-to-LOW transition of the chip enable line when an 18-bit or 19-bit data word is transmitted.
At power-on the charge-pump current is set to 280 µA, the tuning voltage output is disabled (V
tune
= 33 V in application; see Fig.12), the test bits T2, T1 and T0 are set to the normal mode and RSB is set to 1 (TSA5520) or 0 (TSA5521). When an 18-bit data word is transmitted, the most significant bit of the divider N14 is internally set to 0 and bit RSA is set to 1. When a 19-bit data word is transmitted, bit RSA is set to 0.
When a 27-bit word is transmitted, the frequency bits are loaded into the frequency register on the 20th rising edge of the clock pulse and the control bits at the HIGH-to-LOW transition of the chip enable line. In this mode, the reference divider is given by the RSA and RSB bits (see Table 7). The test bits T2, T1 and T0, the charge-pump bit CP, the ratio select bit RSB and the OS bit can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or a 19-bit transmission
occurs. Only RSA is controlled by the transmission length when the 18-bit or 19-bit format is used.
A data word of less than 18 bits will not affect the frequency register of the device. The definition of the bits is unchanged compared to the I2C bus mode.
The power-on detection threshold voltage V
POR
is fixed to
V
CC1
= 2 V at room temperature. Below this threshold, the
device is reset to the power-on state described above.
Table 6 Test bits
Table 7 Ratio select bits
T2 T1 T0 DEVICE OPERATION
0 0 1 normal mode 0 1 X charge-pump is OFF 1 1 0 charge-pump is sinking current 1 1 1 charge-pump is sourcing current 100f
ref
is available at LOCK output
101
1
⁄2f
div
is available at LOCK output
RSA RSB REFERENCE DIVIDER
X 0 640 0 1 1024 1 1 512
Fig.3 Normal mode; 18-bit data format (RSA = 1).
For TSA5520 bit RSB =1 at power-on; the reference divider is 512 or 1024. For TSA5521 bit RSB = 0 at power-on; the reference divider is 640. For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Page 9
1996 Oct 10 9
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Fig.4 Normal mode; 19-bit data format (RSA = 0).
For TSA5520 bit RSB = 1 at power-on; the reference divider is 512 or 1024. For TSA5521 bit RSB = 0 at power-on; the reference divider is 640. For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Fig.5 Test and features mode; 27-bit data format.
For TSA5520 bit RSB = 1 at power-on; the reference divider is 512 or 1024. For TSA5521 bit RSB = 0 at power-on; the reference divider is 640. For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Page 10
1996 Oct 10 10
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Short-circuit between V
CC1
and V
CC2
is allowed provided the voltage applied to V
CC2
is less than the 6 V maximum
rating at V
CC1
.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in accordance with
“MIL-STD-883C category B”
(2000 V). Every pin withstands the ESD test in accordance with Philips
Semiconductors Machine Model 0 , 200 pF (200 V).
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC1
supply voltage; +5 V (pin 3) 0.3 +6.0 V
V
CC2
band switch supply voltage; +12 V (pin 4) 0.3 +16 V
V
i(RF)
prescaler input voltage 0.3 V
CC1
V
V
o(BSn)
band switch buffers output voltage (pins 5 to 8)
0.3 V
CC2
V
I
o(BSn)
band switch buffers output current 1 +50 mA
V
o(CP)
charge-pump output voltage (pin 9) 0.3 V
CC1
V
V
o(tune)
output tuning voltage (pin 10) 0.3 +35 V
V
i(SW)
input switching voltage (pin 11) 0.3 V
CC1
V
V
o(LOCK)
lock output voltage (pin 12) 0.3 V
CC1
V
V
i(SCL)
serial clock input voltage (pin 13) 0.3 +6.0 V
V
i/o(SDA)
serial data input/output voltage (pin 14) 0.3 +6.0 V
I
o(SDA)
serial data output current 1 +10 mA
V
i(CE)
chip enable input voltage (pin 15) 0.3 +6.0 V
V
i(xtal)
crystal oscillator input voltage (pin 16) 0.3 V
CC1
V
T
stg
IC storage temperature 40 +150 °C
T
j
maximum junction temperature +150 °C
t
sc
short-circuit time; every pin except pin 4 to pin 3 and every pin to pin 2
note 1 10 s
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air
SO16 110 K/W SSOP16 142 K/W
Page 11
1996 Oct 10 11
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
CHARACTERISTICS
V
CC1
= 4.5 to 5.5 V; V
CC2=VCC1
to 13.2 V; T
amb
= 20 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
CC1
supply voltage 4.5 5.5 V
V
CC2
band switch buffers supply voltage
V
CC1
12 13.5 V
I
CC1
supply current at power-on 20 25 mA
I
CC2
band switch buffers supply current at power-on 0.5 1 mA
one band switch buffer is ON; I
source
=40mA
50 55 mA
two band switch buffers are ON; I
source
=40mA+5mA
(any combination)
56 62 mA
V
POR
supply voltage below which POR is active
1.5 2.0 V
f
RF
RF input frequency 64 1300 MHz
DR divider ratio 15-bit frequency word 256 32767
14-bit frequency word 256 16383
f
xtal
crystal oscillator input frequency R
xtal
= 25 to 200 3.2 4.0 4.48 MHz
Z
xtal
crystal oscillator input impedance (absolute value)
fi= 4 MHz 600 1200 −Ω
Prescaler (see Figs 8 and 9) V
i(RF)
RF input level fi= 80 to 150 MHz 25 3 dBm
f
i
= 150 to 1000 MHz 28 3 dBm
f
i
= 1000 to 1300 MHz 15 3 dBm
Z
i(RF)
input impedance see Fig.8
PNP band switch buffers outputs (pins 5 to 8)
I
LO
output leakage current V
CC2
= 13.5 V;
Vo=0V
10 −− µA
V
o(sat)
output saturation voltage I
source
= 40 mA;
V
o(sat)=VCC2
V
o
0.2 0.4 V
LOCK output (PNP collector output)
I
o(ool)
output current when out-of-lock V
CC1
= 5.5 V; Vo= 5.5 V −−100 µA
V
osat(ool)
output saturation voltage when out-of-lock
I
source
= 200 µA;
V
o(sat)=VCC1
V
o
0.4 0.8 V
V
o(LOCK)
LOCK output voltage 0.01 0.4 V
SW input (bus format input)
V
IL
LOW level input voltage 0 1.5 V
V
IH
HIGH level input voltage 3 V
CC1
V
I
IH
HIGH level input current VSW=V
CC1
−−10 µA
I
IL
LOW level input current VSW=0V −100 −− µA
Page 12
1996 Oct 10 12
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
CE input (chip enable/address selection)
V
IL
LOW level input voltage 0 1.5 V
V
IH
HIGH level input voltage 3 5.5 V
I
IH
HIGH level input current VCE= 5.5 V −−10 µA
I
IL
LOW level input current VCE=0V −10 −− µA
SCL and SDA inputs
V
IL
LOW level input voltage 0 1.5 V
V
IH
HIGH level input voltage 3.0 5.5 V
I
IH
HIGH level input current V
BUS
= 5.5 V; V
CC1
=0V −−10 µA
V
BUS
= 5.5 V; V
CC1
= 5.5 V −−10 µA
I
IL
LOW level input current V
BUS
= 1.5 V; V
CC1
=0V −−10 µA
V
BUS
=0V; V
CC1
= 5.5 V 10 −− µA
f
clk
clock frequency 100 400 kHz
SDA outputs (I
2
C-bus mode)
I
LO
output leakage current V
SDA
= 5.5 V −−10 µA
V
o
output voltage I
sink
=3mA −−0.4 V
Charge-pump output CP
|I
ICPH
| HIGH charge-pump current CP = 1 280 −µA
|I
ICPL
| LOW charge-pump current CP = 0 60 −µA
V
CP
output voltage in-lock; T
amb
=25°C 1.95 V
I
LI(off)
off-state leakage current T2 = 0; T1 = 1 15 0.5 +15 nA
Tuning voltage output V
tune
I
LO(off)
leakage current when switched-off
OS = 1; V
tune
=33V −−10 µA
V
o
output voltage when the loop is closed
OS = 0; T2 = 0; T1 = 0; T0 = 1; RL=27kΩ; V
tune
=33V
0.2 32.7 V
3-wire bus timing (see Figs 6 and 7) t
HIGH
clock high time 2 −− µs
t
SU;DAT
data set-up time 2 −− µs
t
HD;DAT
data hold time 2 −− µs
t
SU;ENSCL
enable to clock set-up time 10 −− µs
t
HD;ENDAT
enable to data hold time 2 −− µs
t
EN
enable between two transmissions
10 −− µs
t
HD;ENSCL
enable to clock active edge hold time
6 −− µs
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Page 13
1996 Oct 10 13
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Fig.6 Timing diagram for 3-wire bus; SDA, SCL and CE.
Fig.7 Timing diagram for 3-wire bus; CE and SCL.
Page 14
1996 Oct 10 14
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Fig.8 Prescaler Smith chart of typical input impedance at pin 1.
BBBBBBBBBBBBBBBBBBBBBBBBBB
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBB
B
BBBBBBBBBBBBBBBBBBBBBBBBBB
Fig.9 Prescaler typical input sensitivity curve.
Page 15
1996 Oct 10 15
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
INTERNAL PIN CONFIGURATION
handbook, full pagewidth
MLC886 - 1
V
CC1
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
1
RF
internal
reference
voltage
V
ref
2
3
V
CC1
V
EE
4
V
CC2
V
CC2
5
BS4
V
CC2
6
BS3
V
CC2
7
BS2
V
CC2
8
BS1
V
CC1
16
XTAL
V
CC1
15
CE
to address
selection
V
CC1
14
SDA
ACK
(I C BUS)
2
V
CC1
13
SCL
V
CC1
12
LOCK
command
V
CC1
11
SW
V
CC1
10
V
tune
down
up
9
CP
TSA5520 TSA5521
Fig.10 Internal pin configuration.
Page 16
1996 Oct 10 16
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
APPLICATION INFORMATION Tuning amplifier
The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 27 k which is connected to the tuning voltage supply rail. Figures 11 and 12 show a possible loop filter. The component values depend on the oscillator characteristics and the selected reference frequency.
Crystal oscillator
The crystal oscillator uses a 4 MHz crystal connected in series with an 18 pF capacitor thereby operating in the series resonance mode. Connecting the oscillator to the supply voltage is preferred but it can, however, also be connected to ground.
Examples of I
2
C-bus sequences (SW = LOW)
Tables 8 to 12 show the various sequences where f
osc
= 100 MHz, BS4 = ON, ICP= 280 µA, N = 512, f
xtal
= 4 MHz,
S = START, A = acknowledge and P = STOP. The sequence is as follows: START + address byte + divider byte 1 + divider byte 2 + control byte + band switch byte + STOP.
For the complete sequence see Table 8 (sequence 1) or Table 9 (sequence 2).
Table 8 Complete sequence 1
Table 9 Complete sequence 2
Table 10 Divider bytes only sequence
Table 11 Control and band switch bytes only sequence
Table 12 Control byte only sequence
Other I
2
C-bus sequences are not allowed. Other I2C-bus addresses may be selected by applying an appropriate voltage
to the CE input.
Examples of 3-wire bus sequences (TSA5520; SW = OPEN) Table 13 18-bit sequence (f
osc
= 800 MHz, BS4 = ON)
Table 14 19-bit sequence (f
osc
= 650 MHz, BS3 = ON)
The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence.
SC2A06A40ACEA08A P
SC2ACEA08A06A40A P
SC2A06A40A P
SC2ACEA08AP
SC2ACEA P
100011001000000000
0100101000101000000
Page 17
1996 Oct 10 17
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Table 15 27-bit sequence (f
osc
= 750 MHz, BS1 = ON, N = 640, Icp=60µA, no test function)
The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence. This sequence sets RSA = RSB = 0; CP = 0.
Table 16 19-bit sequence
This sequence will program f
osc
to 600 MHz in 50 kHz steps. ICP remains at 60 µA.
Table 17 18-bit sequence
This sequence will program f
osc
to 600 MHz in 50 kHz steps. ICP remains at 60 µA.
Table 18 27-bit sequence (f
osc
= 650 MHz, BS1 = ON)
This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence I
CP
= 280 µA, N = 1024 (19-bit transmission)
and N = 512 (18-bit transmission), RSB = 1.
Example of 3-wire bus sequence (TSA5521; SW = OPEN) Table 19 19-bit sequence (f
osc
= 700 MHz, BS3 = ON)
N = 640 unless RSB has been programmed to 0 during a 27-bit sequence.
000101110101001100010001000
0001010111011100000
000110111011100000
000110100010100000011001010
0100011011010110000
Page 18
1996 Oct 10 18
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
Fig.11 Typical I2C-bus application.
handbook, full pagewidth
MLC887
CP SWITCH
33 V
MID
HIGH
12 V
LOW
5 V
RF
V
SW LOCK SCL SDA CE XTAL
2.2 nF 100 nF
22 k
27 k
22 k
33 nF
tune
V
tune
BS1 BS2 BS3 BS4LOCK
SCL
SDA
AS
V V
V
EE RF
TSA552X
CC2 CC1
1 nF
(1)
(2)
10 nF
18 pF4 MHz
(1) Connection to ground is also allowed. (2) Capacitor prevents parasitic oscillation on the V
CC2
line.
Fig.12 Typical 3-wire bus application.
handbook, full pagewidth
MLC888
CP SWITCH
33 V
MID
HIGH
12 V
LOW
5 V
RF
V
SW LOCK SCL SDA CE XTAL
2.2 nF 100 nF
22 k
27
k
tune
BS1 BS2 BS3 BS4LOCK
CLOCK
DATA
ENABLE
V V
RF
TSA552X
CC2 CC1
1 nF
(1)
(2)
10 nF
18 pF4 MHz
V
EE
22 k
33 nF
V
tune
(1) Connection to ground is also allowed. (2) Capacitor prevents parasitic oscillation on the V
CC2
line.
Page 19
1996 Oct 10 19
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
PACKAGE OUTLINES
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A1A2A
3
b
p
cD
(1)E(1) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8 0
o o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT109-1
91-08-13 95-01-23
076E07S MS-012AC
0.069
0.0098
0.0039
0.057
0.049
0.01
0.019
0.014
0.0098
0.0075
0.39
0.38
0.16
0.15
0.050
1.05
0.041
0.24
0.23
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Page 20
1996 Oct 10 20
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
UNIT A
1
A2A
3
b
p
cD
(1)E(1)
(1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
0.65
6.6
6.2
0.65
0.45
0.48
0.18
10
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
1.0
SOT369-1
94-04-20 95-02-04
w M
θ
A
A
1
A
2
b
p
D
y
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
X
(A )
3
A
0.25
18
16
9
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
A
max.
1.5
Page 21
1996 Oct 10 21
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
SOLDERING SO or SSOP Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
(order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SO and SSOP packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Wave soldering
SO Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
The longitudinal axis of the package footprint must be parallel to the solder flow.
The package footprint must incorporate solder thieves at the downstream end.
SSOP Wave soldering isnot recommended for SSOP packages.
This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following conditions must be observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering technique should be used.
The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate solder thieves at the downstream end.
Even with these conditions, only consider wave soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
M
ETHOD (SO OR SSOP)
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 °C.
Page 22
1996 Oct 10 22
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
Page 23
1996 Oct 10 23
Philips Semiconductors Product specification
1.3 GHz universal bus-controlled TV synthesizer
TSA5520; TSA5521
NOTES
Page 24
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands 537021/50/02/pp24 Date of release: 1996 Oct 10 Document order number: 9397 750 01353
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