Datasheet TSA5059 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TSA5059

2.7 GHz I

2

C-bus controlled
low phase noise frequency
synthesizer

Preliminary specification
File under Integrated Circuits, IC02

1999 Oct 05

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

FEATURES

• Complete 2.7 GHz single chip system

• Optimized for low phase noise

• Selectable divide-by-two prescaler

• Operation up to2.7 GHz with and without divide-by-two

prescaler

• Selectable reference divider ratio

• Compatible with UK-DTT (Digital Terrestrial Television)

offset requirements

• Selectable crystal/comparison frequency output

• Four selectable charge pump currents

• Four selectable I2C-bus addresses

• Standard and fast mode I2C-bus

• I2C-bus compatible with 3.3 and 5 V microcontrollers

• 5-level Analog-to-Digital Converter (ADC)

• Low power consumption

• 33 V tuning voltage drive

• Three I/O ports and one output port.

APPLICATIONS

• SAT, TV, VCR and cable tuning systems

• Digital set-top boxes.

GENERAL DESCRIPTION

The TSA5059 is a single chip PLL frequency synthesizer
designed for satellite and terrestrial tuning systems up to

2.7 GHz.
TheRFpreamplifierdrivesthe 17-bit main divider enabling

astep size equal tothe comparison frequency, for aninput
frequency up to 2.7 GHz. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider to give a software compatibility with

TSA5059

existing ICs. In this case, the step size is twice the
comparison frequency.

The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.

Bothdividedandcomparisonfrequencyarecomparedinto
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, including the
high-voltage transistor to drive directly the 33 V tuning
voltage, without the need of an external transistor.

ControldataisenteredviatheI2C-bus;fiveserialbytesare
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports,set the charge pump current, selectthe prescaler by
two, select the signal to switch to the XT/COMP output pin
and/or select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC can be read out of the TSA5059 on the SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.

1999 Oct 05 2

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

QUICK REFERENCE DATA

VCC= 4.5 to 5.5 V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

f

i(RF)

V

i(RF)(rms)

f

xtal

T

amb

T

stg

supply voltage 4.5 5.0 5.5 V
supply current T
RF input frequency 64 − 2700 MHz
RF input voltage (RMS value) f

crystal frequency 4 − 16 MHz
ambient temperature −20 − +85 °C
storage temperature −40 − +150 °C

Note

1. Asymmetrical drive on pin RFA or RFB; see Fig.3.

= −20 to +85 °C; unless otherwise specified.

amb

=25°C 303745mA

amb

from 64 to 150 MHz;

i(RF)

note 1
f

from 150 to 2200 MHz;

i(RF)

note 1
f

from 2.2 to 2.7 GHz;

i(RF)

note 1

12.6 − 300 mV

−25 − +2.5 dBm

7.1 − 300 mV

−30 − +2.5 dBm

22.4 − 300 mV

−20 − +2.5 dBm

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TSA5059T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
TSA5059TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1999 Oct 05 3

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

BLOCK DIAGRAM

handbook, full pagewidth

XTAL

RFA

RFB

2

13
14

OSCILLATOR

PRE
AMP

XTAL

DIVIDER

1/2

REFERENCE

DIVIDER

4-BIT LATCH

17-BIT

DIVIDER

LOCK

DETECT

DIGITAL PHASE

COMPARATOR

CHARGE PUMP

3

TSA5059

XT/COMP

AS

SCL

SDA

ADC

4
6
5

11

TRANSCEIVER

3-BIT

ADC

POWER-ON

RESET

1-BIT

LATCH

I2C-BUS

3-BIT

INPUT

PORTS

17-BIT LATCH
DIVIDE RATIO

4-BIT LATCH

AND

OUTPUT PORTS

P3 P2 P1 P0

1

2-BIT

LATCH

CONTROL

MODE
LOGIC

33 V
AMP

CP

16

VT

12

V

CC

15

GND

TSA5059

10987

FCE120

Fig.1 Block diagram.

1999 Oct 05 4

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

PINNING

SYMBOL PIN DESCRIPTION

CP 1 charge pump output
XTAL 2 crystal oscillator input
XT/COMP 3 f
AS 4 I
SDA 5 I
SCL 6 I
P3 7 general purpose output Port 3
P2 8 general purpose input/output Port 2
P1 9 general purpose input/output Port 1
P0 10 general purpose input/output Port 0
ADC 11 analog-to-digital converter input
V

CC

12 supply voltage
RFA 13 RF signal input A
RFB 14 RF signal input B
GND 15 ground supply
VT 16 tuning voltage output

or f

xtal
2

C-bus address selection input

2

C-bus serial data input/output

2

C-bus serial clock input

signal output

comp

handbook, halfpage

XT/COMP

CP

1

XTAL

2
3

AS

4

SDA

SCL

P3
P2

TSA5059

5
6
7
8

FCE121

Fig.2 Pin configuration.

16

VT

15

GND

14

RFB

13

RFA
V

12

CC

ADC

11
10

P0
P1

9

TSA5059

FUNCTIONAL DESCRIPTION

The TSA5059 contains all the necessary elements but a
referencesourceandaloopfilterto control a varicap tuned
local oscillator forming a phase locked loop frequency
synthesized source. The IC is designed in a high speed
process with a fast phase detector to allow a high
comparison frequency to reach a low phase noise level on
the oscillator.

The block diagram is shown in Fig.1. The RF signal is
applied at pins RFA and RFB. Thanks to the input
preamplifier a good sensitivity is provided. The output of
the preamplifier is fed to the 17-bit programmable divider
either through a divide-by-two prescaler or directly.
Becauseof the internal high speed process, theRF divider
is working for a frequency up to 2.7 GHz, without the need
for the divide-by-two prescaler to be used. This prescaler
is present on chip for compatibility reasons with existing
circuits.

The output of the 17-bit programmable divider f

DIV

is fed
into the phase comparator, where it is compared in both
phaseandfrequency with the comparison frequency f

comp

This frequency is derived from the signal present at
pin XTAL, f

, divided down in the reference divider. It is

xtal

possible either to connect a quartz crystal topin XTAL and
then using the on-chip crystal oscillator, or to feed this pin

with a reference signal from an external source.
The reference divider can have a dividing ratio selected
from 16 different values between 2 and 320, including the
ratio 24 to cope with the offset requirement of the UK-DTT
system, see Table 8.

The output of the phase comparator drives the
charge pump and the loop amplifier section. This amplifier
has an on-chip high voltage drive transistor which avoids
the use of an additional external component. Pin CP is the
output of the charge pump, and pin VT is the pin to drive
the tuning voltage to the varicap diode of the Voltage
Controlled Oscillator (VCO). The loop filter has to be
connected between pins CP and VT.

In addition, it is possible to drive another PLL synthesizer,
or the clock input of a digital demodulation IC, from the
pin XT/COMP. It is possible to select by software either
f

, the crystal oscillator frequency or f

xtal

, the frequency

comp

present after the reference divider at this pin. It is also
possible to switch off this output, in case it is not used.

For test and alignment purposes, it is possible to release

.

the tuning voltage output to be able to apply an external
voltage on it, to select one of the three charge pump test
modes, and to monitor half the f

at Port P0. See

DIV

Table 10 for all possible modes.

1999 Oct 05 5

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

Four open-collector output ports are provided on the IC for
general purpose; three of these can also be used as input
ports. A 3-bit ADC is also available.

The TSA5059 is controlled via the two-wire I2C-bus.
For programming, there is one 7-bit module address and
the R/W bit for selecting READ or WRITE mode. To be
able to have more than one synthesizer in an I2C-bus
system, one of four possible addresses is selected
depending on the voltage applied at pin AS (see Table 3).

The TSA5059 fulfils the fast mode I2C-bus, according to
the Philips I2C-bus specification. The I2C-bus interface is
designed in such a way that pins SCL and SDA can be
connected either to 5 or to 3.3 V pulled-up I2C-bus lines,
allowing the PLL synthesizer to be connected directly to
the bus lines of a 3.3 V microcontroller.

WRITE mode: R/W=0

After the address transmission (first byte), data bytes can
be sent to the device (see Table 1). Four data bytes are
neededtofullyprogramtheTSA5059. The bus transceiver
hasan auto-increment facility that permitsprogramming of
the TSA5059 within one single transmission
(address + 4 data bytes).

TSA5059

The TSA5059 can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or byte 4. The meaning of the bits in the data bytes
is given in Table 1. The first bit of the first data byte
transmitted indicates whether byte 2 (first bit is logic 0) or
byte 4 (first bit is logic 1) will follow. Until an I2C-bus STOP
condition is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
To allow a smooth frequency sweep for fine tuning, and
while the data of the dividing ratio of the main divider is in
data bytes 2, 3 and 4, it is necessary for changing the
frequency to send the data bytes 2 to 5 in a repeated
sending, or to finish an incomplete transmission by a
STOP condition. Repeated sending of data bytes 2 and 3
without ending the transmission does not change the
dividing ratio. To illustrate, the following data sequences
will change the dividing ratio:

• Bytes 2, 3, 4 and 5

• Bytes 4, 5, 2 and 3

• Bytes 2, 3, 4 and STOP

• Bytes 4, 5, 2 and STOP

• Bytes 2, 3 and STOP

• Bytes 2 and STOP

• Bytes 4 and STOP.

Table 1 Write data format

BYTE DESCRIPTION MSB

1 address 1 1 0 0 0 MA1 MA0 0 A
2 programmable divider 0 N14 N13 N12 N11 N10 N9 N8 A
3 programmable divider N7 N6 N5 N4 N3 N2 N1 N0 A
4 control data 1 N16 N15 PE R3 R2 R1 R0 A
5 control data C1 C0 XCE XCS P3 P2/T2 P1/T1 P0/T0 A

Note

1. MSB is transmitted first.

(1)

LSB CONTROL BIT

1999 Oct 05 6

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

Table 2 Explanation of Table 1

BIT DESCRIPTION

MA1 and MA0 programmable address bits; see Table 3
A acknowledge bit
N16 to N0 programmable main divider ratio control bits; N = N16 × 216+ N15 × 215+ ... + N1 × 21+N0
PE prescaler enable (prescaler by 2 is active when bit PE = 1)
R3 to R0 programmable reference divider ratio control bits; see Table 8
C1 and C0 charge pump current select bits; see Table 9
XCE XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10
XCS XT/COMP select; signal select when bit XCE = 1, test mode enable when bit XCE = 0; see Table 10
T2, T1 and T0 test mode select when bit XCE = 0 and bit XCS = 1; see Table 10
P3, P2 and P1 Port P3, P2 and P1 output states
P0 Port P0 output state, except in test mode; see Table 10

Address selection (see Table 3)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having

up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given in
Table 3.

Table 3 Address selection

MA1 MA0 VOLTAGE APPLIED TO PIN AS

0 0 0 to 0.1V

CC

0 1 open-circuit
1 0 0.4V
1 1 0.9V

to 0.6VCC; note 1

CC

to V

CC

CC

Note

1. This address is selected by connecting a 15 kΩ resistor between pin AS and pin V

CC

.

Status at Power-On Reset (POR)

At power-on or when the supply voltage drops below approximately 2.75 V, internal registers are set according to
Table 4.

Table 4 Status at Power-on reset; note 1

BYTE DESCRIPTION MSB LSB CONTROL BIT

1 address 11000MA1MA00 A
2 programmable divider 0 XXXXXXX A
3 programmable divider XXXXXXXX A
4 control data 1 XXXXXXX A
5 control data 0001X

(2)

(2)

1

(2)

X

(2)

X

A

Notes

1. X = don’t care.

2. At Power-on reset, all output ports are in high-impedance state.

1999 Oct 05 7

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

READ mode: R/W=1

Data can be read out of the TSA5059 by setting the
bit R/W to logic 1 (see Table 5). After the slave address
has been recognized, the TSA5059 generates an
acknowledge pulse and the first data byte (status word) is
transferredontheSDA line(MSBfirst). Data is valid on the
SDA line during a HIGH-level of the SCL clock signal.

A second data byte can be read out of the TSA5059 if the
controller generates an acknowledge on the SDA line.
End of transmission will occur if no acknowledge from the
controller occurs.The TSA5059 will then release the data
line to allow the controller to generate a STOP condition.
When ports P0 to P2 are used as inputs, they must be
programmed in their high-impedance state.

The POR flag is set to logic 1 when VCC drops below
approximately 2.75 V and at power-on.

Table 5 Read data format

BYTE DESCRIPTION MSB

(1)

1 address 1 1000MA1MA01 A
2 status byte POR FL I2 I1 I0 A2 A1 A0 −

It is reset to logic 0 when an end of data is detected by the
TSA5059 (end of a READ sequence).

Control of the loop is made possible with the in-lock flag
which indicates (bit FL = 1) whenthe loop is phase-locked.

The bits I2, I1 and I0 represent the status of the I/O ports
P2, P1 and P0 respectively. A logic 0 indicates a
LOW-level and a logic 1 indicates a HIGH-level.

A built-in 5-level ADC is available at pin ADC. This
converter can be used to feed AFC information to the
microcontroller through the I2C-bus. The relationship
between bits A2, A1, A0 and the input voltage at pin ADC
is given in Table 7.

LSB CONTROL BIT

Note

1. MSB is transmitted first.

Table 6 Explanation of Table 5

BIT DESCRIPTION

A acknowledge bit
MA1 and MA0 programmable address bits; see Table 3
POR Power-on reset flag (bit POR = 1 on power-on)
FL in-lock flag (bit FL = 1 when the loop is phase-locked)
I2, I1 and I0 digital information for I/O ports P2, P1 and P0 respectively
A2, A1 and A0 digital outputs of the 5-level ADC; see Table 7

Table 7 ADC levels

A2 A1 A0 VOLTAGE APPLIED TO PIN ADC

1 0 0 0.6VCCto V
0 1 1 0.45VCCto 0.6V
0 1 0 0.3VCCto 0.45V
0 0 1 0.15VCCto 0.3V
0 0 0 0 to 0.15V

CC

CC
CC
CC

CC

Note

1. Accuracy is ±0.03V

CC

.

(1)

1999 Oct 05 8

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

Reference divider ratio

The reference divider ratio is set by 4 bits in the WRITE
mode, giving 16 different ratios which allow to adjust the
comparison frequency to different values, depending on
the compromise which has to be found between step size
and phase noise.

Table 8 Reference dividing ratios

R3 R2 R1 R0 RATIO

0000 2 2MHz 2MHz 4MHz
0001 4 1MHz 1MHz 2MHz
0010 8 500kHz 500kHz 1MHz
001116 250kHz 250kHz 500kHz
010032 125kHz 125kHz 250kHz
010164 62.5 kHz 62.5 kHz 125 kHz
0110128 31.25 kHz 31.25 kHz 62.5 kHz
0111256 15.625 kHz 15.625 kHz 31.25 kHz
100024 166.67 kHz 166.67 kHz 333.33 kHz
1001 5 800kHz 800kHz 1.6MHz
101010 400kHz 400kHz 800kHz
101120 200kHz 200kHz 400kHz
110040 100kHz 100kHz 200kHz
110180 50kHz 50kHz 100kHz
1110160 25kHz 25kHz 50kHz
1111320 12.5 kHz 12.5kHz 25 kHz

COMPARISON

FREQUENCY

Table 8 shows the different dividing ratios and the
corresponding comparison frequencies and step size,
assuming the device is provided with a 4 MHz signal at
pin XTAL.

The dividing ratio of24 is implemented to fulfil the UK-DTT
recommendation regarding offset frequency of1⁄6MHz.

STEP

(1)

BIT PE = 0

(1)

BIT PE = 1

(1)

Note

1. Only valid when the IC is used with a 4 MHz crystal.

Charge pump current

The charge pump current can be chosen from 4 different values depending on the value of bits C1 and C0 in the I2C-bus
byte 4, according to Table 9.

Table 9 Charge pump current

I

(µA) (absolute value)

C1 C0

MIN. TYP. MAX.

0 0 100 135 170
0 1 210 280 350
1 0 450 600 750
1 1 920 1230 1560

1999 Oct 05 9

cp

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

XT/COMP frequency output

It is possible to output either the crystal or the comparison
frequency at this pin to be used in the application, for
example to drive a second PLL synthesizer, saving a
quartz crystal in the bill of material. To output f
necessary to set bit XCE to logic 1 and bit XCS to logic 0,
or bit XCE to logic 0 and bit XCS to logic 1 during a test
mode, while to output f

, it is necessary to set both

comp

bits XCE and XCS to logic 1.
If the output signal at this pin is not used, it is

recommendedto disable it, setting both bits XCE and XCS
to logic 0. Table 10 shows how this pin is programmed.
At power-on, the XT/COMP output is set, with the f
signal selected.

Prescaler enable

Even if the TSA5059 is able to work with the relation
f

= step size for an input frequency up to 2.7 GHz, this

comp

ICisdesigned to be backward compatible with existing ICs

xtal

, it is

xtal

TSA5059

for which this relation is only valid for an RF frequency up
to 2.0 GHz and in which it is necessary to select a fixed
divide-by-two prescaler for frequencies between 2.0 and

2.7 GHz.
The prescaler is selected by setting bit PE to logic 1 and

it is not in use if bit PE is set to logic 0.
For new designs, and especially if it is important to reach

a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0, and not to use the
prescaler, allowing the comparison frequency to be equal
to the step size, whatever the RF frequency is between
64 and 2700 MHz.

Test modes

It is possible to access the test modes setting bit XCE to
logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0, as described in
Table 10.

Table 10 XT/COMP and test mode selection; note 1

XCE XCS T2 T1 T0 XT/COMP OUTPUT TEST MODE

0 0 X X X disabled normal operation
10XXXf
11XXXf
01000f

xtal
comp
xtal

normal operation
normal operation
test operation: charge pump sink;

status byte: bit FL = 1

01001f

xtal

test operation: charge pump source;
status byte: bit FL = 0

01010f

xtal

test operation: charge pump disabled;

status byte: bit FL = 0
01011f
011XXf

xtal
xtal

test operation:1⁄2f

DIV

test operation: tuning voltage (pin VT) is

off (high-impedance); note 2

Notes

1. X = don’t care.

2. Status at Power-on reset.

switched to Port P0

1999 Oct 05 10

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); note 1.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

(n)

I

O(SDA)

I

O(Px)

I

O(ΣPx)

T

amb

T

stg

T

j(max)

t

sc

supply voltage −0.3 +6.0 V
voltage on pins

CP, XTAL, XT/COMP, AS, P0, P1,

−0.3 V

+ 0.3 V

CC

P2, P3, ADC, RFA and RFB
SCL and SDA −0.3 +6.0 V

VT −0.3 +35 V
serial data output current −1.0 +10.0 mA
P0, P1, P2 and P3 output current port switched on −1.0 +20.0 mA
sum of currents in P0, P1, P2 and P3 − 50.0 mA
ambient temperature −20 +85 °C
storage temperature −40 +150 °C
maximum junction temperature − 150 °C
short-circuit time each pin to VCCor GND − 10 s

Note

1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings cannot be accumulated.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

TSA5059T (SOT109-1; SO16) 115 K/W
TSA5059TS (SOT369-1; SSOP16) 144 K/W

1999 Oct 05 11

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

CHARACTERISTICS

VCC= 4.5 to 5.5 V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin V

V

CC

I

CC

V

CC(POR)

CC

supply voltage 4.5 5.0 5.5 V
supply current T
supply voltage below which POR is active T

RF inputs (pins RFA and RFB)

f

i(RF)

V

i(RF)(rms)

Z

i(RF)

C

i(RF)

RF input frequency 64 − 2700 MHz
RF input voltage (RMS value) f

RF input impedance see Fig.7 −−− Ω
RF input capacitance see Fig.7 −−− pF

MDR main divider ratio prescaler disabled 64 − 131071

Crystal oscillator (pin XTAL)

f

xtal

Z

XTAL

Z

XTAL

P

XTAL

f

i(ext)

V

i(ext)(p-p)

crystal frequency 4 − 16 MHz

 crystal oscillator negative impedance 4 MHz crystal 400 680 −Ω

recommended crystal series resistance 4 MHz crystal −−200 Ω
crystal drive level 4 MHz crystal; note 2 − 40 −µW
external reference input frequency note 3 2 − 20 MHz
external reference input voltage

(peak-to-peak value)

Phase comparator and charge pump

f

comp

N

comp

comparison frequency −−2 MHz
equivalent phase noise at the phase

detector input

I

 charge pump current C1 = 0; C0 = 0 100 135 170 µA

cp

I

cpl

charge pump leakage current −10 0 +10 nA

= −20 to +85 °C; f

amb

)

= 4 MHz; measured according to Fig.4; unless otherwise specified.

xtal

=25°C303745mA

amb

=25°C − 2.75 − V

amb

between 64 and

i(RF)

150 MHz; note 1
f

between 150 and

i(RF)

2200 MHz; note 1
f

between 2.2 and

i(RF)

2.7 GHz; note 1

12.6 − 300 mV

−25 − +2.5 dBm

7.1 − 300 mV

−30 − +2.5 dBm

22.4 − 300 mV

−20 − +2.5 dBm

prescaler enabled 128 − 262142

note 3 200 − 500 mV

f

comp

= 250 kHz;

−−157 − dBc/Hz
C1=C0=1;
in the loop bandwidth

C1 = 0; C0 = 1 210 280 350 µA
C1 = 1; C0 = 0 450 600 750 µA
C1 = 1; C0 = 1 920 1230 1540 µA

1999 Oct 05 12

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Tuning voltage output (pin VT)

I

lO(off)

leakage current when switched off XCE = 0; XCS = 1;

T2 = 1; VVT=33V

V

O

output voltage when the loop is

locked; normal mode;
VVT= 33 V; pull-up
resistor of 27 kΩ

XT/COMP output (pin XT/COMP)

V

O(p-p)

AC output voltage (peak-to-peak value) XCE = 1 − 400 − mV

Input/output and output ports (pins P0, P1, P2 and P3)

I

lO

V
V
V

O(sat)
IL
IH

port leakage current port off; VO=V
output port saturation voltage port on; I

CC

=10mA − 0.2 0.4 V

sink

LOW-level input voltage −−1.5 V
HIGH-level input voltage 3.0 −− V

ADC input (pin ADC)

I
I

LIH
LIL

HIGH-level input leakage current V
LOW-level input leakage current V

ADC=VCC

=0V −10 −− µA

ADC

Address selection (pin AS)

I

LIH

I

LIL

HIGH-level input leakage current VAS=V

CC

LOW-level input leakage current VAS=0V −0.5 −− mA

SCL and SDA inputs (pins SCL and SDA)

V

IL

V

IH

I

LIH

I

LIL

f

SCL

LOW-level input voltage −−1.5 V
HIGH-level input voltage 2.3 −− V
HIGH-level input leakage current VIH= 5.5 V

V

= 5.5 V −−10 µA

CC

=0V −−10 µA

V

CC

LOW-level input leakage current VIL=0V; VCC= 5.5 V −10 −− µA
SCL clock frequency −−400 kHz

SDA output (pin SDA)

V

O(ack)

output voltage during acknowledge I

=3mA −−0.4 V

sink

=6mA −−0.6 V

I

sink

Notes

1. Asymmetrical drive on pin RFA or RFB; see Fig.3.

2. The drive level is expected with the crystal at series resonance with a series resistance of 50 Ω. The value will be
different with another crystal.

3. To drive pin XTAL from the pin XT/COMP of another TSA5059, couple the signal through a capacitor of 1 nF
(to remove the DC level), in series with an 1.2 kΩ resistor, see Fig.5.

−−−10 µA

0.25 − 32.7 V

−−10 µA

−−10 µA

−−1mA

1999 Oct 05 13

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

handbook, full pagewidth

V

i(RF)

(dBm)

−12

−18

−24

−30

−36

−42

−48

−54

−60

+6

0

−6

500 1000 1500 2000 2500 30000

TSA5059

FCE416

guaranteed area

f (MHz)

Fig.3 Sensitivity curve.

1999 Oct 05 14

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

APPLICATION INFORMATION

An example of a typical application is givenin Fig.4. In this application the VCO centrefrequency is 1.5 GHz, with a slope
of 100 MHz/V; the expected loop bandwidth is 10 kHz with a charge pump current of 555 µA and f
componentsneedto be adapted to each application depending ontheVCOcharacteristics and the required performance
of the loop.

3.9 kΩ

2.2 nF

TSA5059

33 V

5 V

27 kΩ

16
15
14
13
12
11
10

9

VT

GND
RFB
RFA

V

CC

2.7 kΩ

1 nF
1 nF
10 nF

1 nF

VCO

output

tuning

voltage

VCO

handbook, full pagewidth

4 MHz

SDA

SCL

MICRO-

CONTROLLER

18 pF

XT/COMP

47 nF

CP

XTAL

AS

1
2
3
4
5
6
7

8

of 250 kHz. Filter

comp

P3 P2 P1 P0 ADC

Fig.4 Typical application.

Loop bandwidth

Most of the applications the TSA5059 are dedicated for
require a large loopbandwidth, in the order of a few kHz to
a few tens of kHz. The calculation of the loop filter
elements has to be done for each application, while it
dependsontheVCOslopeandphasenoise,aswellasthe
reference frequency and charge pump current.
A simulation of the loop can easily be done by using the
SIMPATA software from Philips.

Reference source

The TSA5059 is well suited to be used with a 4 MHz
crystal connected to pin XTAL. Philips crystal ordering
code 4322 143 04093 is recommended in this case.

FCE123

It is however possible to use a crystal with an higher
frequency (up to 16 MHz) to improve the noise
performance. When choosing a crystal, one should take
notice to select a crystalable to withstand the drive level of
the TSA5059 without suffering from accelerated ageing.

It is also possible to feed pin XTAL with an external signal
between2 and 20 MHz,comingfrom an external oscillator
orfromthepin XT/COMPofanotherTSA5059,whenmore
than one synthesizer is present in the same application.
Then the application given in Fig.5 should be used.

If the signal at pin XT/COMP is not used in an application,
the output should be switched off (XCE = 0, XCS = 0).
This pin should then be open.

1999 Oct 05 15

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

handbook, full pagewidth

4 MHz

18 pF

1
2

3
4

TSA5059

5
6
7
8

16
15

14
13
12
11
10

9

1.0 nF

1.2 kΩ

1
2

3
4

TSA5059

5
6
7
8

TSA5059

16
15

14
13
12
11
10

9

FCE124

Fig.5 Application for using one crystal with two TSA5059s.

I2C-bus crosstalk and loop amplifier

The TSA5059 includes a loop amplifier between pin CP
and pin VT. While this amplifier shares the same ground
pin as the I2C-bus, there may be some I2C-bus crosstalk.

The best way to avoid any I2C-bus crosstalk, both in the
PLL IC and in the application (i.e. parasitic coupling
between the I2C-bus lines and the VCO coil), is to avoid
the I2C-bus signal to come in the RF part by using an
I2C-bus gate that allows only the messages for the PLL to
go to the PLL, and to avoid unnecessary repeated
sending. Such a gate is integrated in most of the Philips
digital demodulators.

2

If I

C-bus crosstalk is still a problem, it is possible not to
use the internal amplifier, and to replace it with a NMOS
transistor in the application as given in Fig.6. In this case
the pin VT is left open, and it is possible to implement on
the PCB the foot print for a jumper between the tuning
voltage line and pin VT to be able to choose either the
internal amplifier (mounting the jumper and not the NMOS
transistor) or the external amplifier (mounting the NMOS
transistor and not the jumper). It is recommended to use a
BSH111 or BSH121 N-channel MOS transistor. The
threshold voltage of the transistor has to be lower than

2.0 V.

1999 Oct 05 16

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

handbook, full pagewidth

CP

33 V

27 kΩ

3.9 kΩ

2.2 nF47 nF

BSH111

or BSH121

1

16

VT

2.7 kΩ

2.7
pF

1 nF

jumper

(optional)

TSA5059

tuning
voltage

VCO

FCE417

RF input impedance

handbook, full pagewidth

Fig.6 Application for using an external loop amplifier.

1

0.5

0.2

+ j

0

− j

0.2

0.5

0.5 10.2 1052

2

2.7GHz

2

5

10

64MHz

10

5

Fig.7 RF input impedance.

1999 Oct 05 17

1

FCE418

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

PACKAGE OUTLINES

SO16: plastic small outline package; 16 leads; body width 3.9 mm

D

c

y

Z

16

9

TSA5059

SOT109-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 2.5 5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.010

0.057

0.004

0.049

0.25

0.01

b

3

p

0.49

0.25

0.36

0.19

0.0100

0.019

0.0075

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

10.0

9.8

0.39

0.38

8

b

p

scale

eHELLpQZywv θ

4.0

1.27

3.8

0.16

0.050

0.15

w M

6.2

5.8

0.244

0.228

A

2

1.05

0.041

Q

A

1

detail X

1.0

0.7

0.4

0.6

0.028

0.039

0.020

0.016

(A )

L

p

L

0.25 0.1

0.25

0.01

0.01 0.004

A

3

θ

0.7

0.3

0.028

0.012

o

8

o

0

OUTLINE
VERSION

SOT109-1

IEC JEDEC EIAJ

076E07S MS-012AC

REFERENCES

1999 Oct 05 18

EUROPEAN

PROJECTION

ISSUE DATE

95-01-23
97-05-22

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

16

D

c

y

Z

9

E

H

E

TSA5059

SOT369-1

A

X

v M

A

pin 1 index

18

w M

b

b

0.32

0.20

p

p

cD

0.25

5.30

0.13

5.10

0 2.5 5 mm

scale

(1)E(1)

eHELLpQZywv θ

4.5

0.65

4.3

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

1.5

0.15

0.00

1.4

1.2

A

2

3

0.25

UNIT A1A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

Q

A

2

6.6

6.2

L

0.65

0.45

(A )

L

p

A

1

detail X

0.75

1.0

0.45

3

A

θ

0.130.2 0.1

0.48

0.18

(1)

o

10

o

0

OUTLINE

VERSION

SOT369-1

IEC JEDEC EIAJ

REFERENCES

1999 Oct 05 19

EUROPEAN

PROJECTION

ISSUE DATE

94-04-20
95-02-04

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TSA5059

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust

be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Oct 05 20

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

1999 Oct 05 21

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase

TSA5059

noise frequency synthesizer

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1999 Oct 05 22

Philips Semiconductors Preliminary specification

2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer

NOTES

TSA5059

1999 Oct 05 23

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS,ViaCasati, 23 - 20052 MONZA (MI),
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TOKYO 108-8507, Tel. [phone], Fax. [phone]

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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
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Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

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Slovenia: see Italy
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/01/pp24 Date of release: 1999 Oct 05 Document order number: 9397 750 05435