Datasheet TSA1001IF Datasheet (SGS Thomson Microelectronics)

TSA1001

10-BIT, 25MSPS, 35mW A/D CONVERTER

■ 10-bit A/D converter in deep submicron

CMOS technology

■ Ultra low power consumption: 35mW @

25Msps (10mW @ 5Msps)

■ Single supply voltage: 2.5V

■ Input range: 2Vpp differential

■ 25Msps sampling frequency

■ ENOB=9.7 @ Nyquist

■ SFDR typically up to 72dB @ Nyquist

■ Built-in reference voltage with external bias

capability

■ STMicroelectronics 8, 10, 12 and 14-bits ADC

pinout compatibility

DESCRIPTION

The TSA1001 is a 10-bit, 25Msps sampling fre­quency Analog to Digital converter using a CMOS
technology combining high performances and
very low power consumption.

The TSA1001 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and go beyond 9.8 effective bits at
Fs=25Msps, and Fin=10MHz .

Especially designed f or portable applications, the
TSA1001 only dissipates 35mW at 25Msps. When
running at lower sampling frequencies, even lower
consumption can be achieved.

A voltage reference is int egrated in the circuit to
simplify the de sign and minimize external c om po­nents. It is nevertheless possible to use the circuit
with an external reference.

The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for synchro­nization purposes.

The TSA1001 is available in commercial (0 to

+70°C) and extended (-40 t o +85°C) temperat ure
range, in a small 48 pins TQFP package.

ORDER CODE

Part Number

TSA1001CF 0°C to +70°C TQFP48 Tray SA1001C
TSA1001CFT 0°C to +70°C TQFP48 Tape & Reel SA1001C
TSA1001IF -40°C to +85°C TQFP48 Tray SA1001I
TSA1001IFT -40°C to +85°C TQFP48 Tape & Reel SA1001I
EVAL1001/AA Evaluation board

Temperature

Range

Package Conditioning Marking

PIN CONNECTIONS (top view)

AGND

index

corner

IPOL

VREFP

VREFM

AGND

VIN

AGND

VINB
AGND
INCM

AGND
AVCC
AVCC

AVCC

AVCC

DFSB

4748 44 43 42 41 40 39 38

46 45

1
2

3
4
5
6

7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

DVCC

DVCC

TSA1001

CLK

DGND

DGND

OEB

VCCB

GNDB

NC

DGND

VCCB

NC

GNDB

GNDB

VCCBNCOR

DR

23 24

NC

37

NC

36

NC

35

NC

34
33

D0 (LSB)

32

D1

31

D2

30

D3
D4

29

D5

28

D6

27
26

D7

25

D8

D9 (MSB)

PACKAGE

7 × 7 mm TQFP48

APPLICATIONS

■ Portable instrumentation

■ Video processing

■ Medical imaging and ultrasound

■ High resolution fax and scanners

■ Digital communications

October 2000

1/19

TSA1001

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Values Unit

AVCC
DVCC
VCCB

Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage

IDout Digital output current -100 to 100 mA

Tstg Storage temperature +150 °C

ESD Electrical Static Discharge:

- HBM

- CDM-JEDEC Standard

1). All voltages values, except di f ferential v ol tage, are with respe ct t o network ground te rm i nal. The m agnitude of i nput and out pu t volt ages
must neve r exceed -0.3V or VCC+0V

OPERATING CONDITIONS

Symbol Parameter Test conditions Min Typ Max Unit

AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCB Digital buffer Supply voltage 2.25 2.5 2.7 V

VREFP Forced top voltage reference 1.16 - AVCC V

VREFM Forced bottom reference voltage 0 0 0.5 V

1)

1)

1)

0 to 3.3 V
0 to 3.3 V
0 to 3.3 V

KV

2

1.5

BLOCK DIAGRAM

VIN

INCM

VINB

CLK

+2.5V

stage stage
1 2

Timing

GND

stage
n

Sequencer-pha s e shifting

Digital data correction

Reference

Buffers

VREFP

circuit

GNDA

IPOL

VREFM

DFSB
OEB

DR
DO

TO

D9

OR

2/19

PIN CONNECTIONS (top view)

index

corner

1

IPOL

VREFP

2

AGND

VIN

AGND

VINB
AGND
INCM

AGND
AVCC

3
4

5
6

7
8

9
10
11
12

VREFM

AGND

AVCC

AVCC

DFSB

OEB

4748 44 43 42 41 40 39 38

46 45

NC

NC

VCCB

GNDB

TSA1001

13 14 15 16 17 18 19 20 21 22

DVCC

DVCC

DGND

CLK

DGND

DGND

GNDB

GNDB

VCCB

23 24

VCCBNCOR

DR

TSA1001

NC

37

NC

36

NC

35

NC

34
33

D0 (LSB)

32

D1

31

D2

30

D3
D4

29

D5

28

D6

27
26

D7

25

D8AVCC

D9 (MSB)

PIN DESCRIPTION

Pin No Name Description Observation Pin No Name Description Observation

1 IPOL Analog bias current input 25 D8 Digi tal output CMOS output (2.5V)
2 VREFP Top voltage reference 1V 26 D7 Digital output CMOS output (2.5V)
3 VREFM Bottom voltage reference 0V 27 D6 Digital output CMOS outpu t (2.5V)
4 AGND Analog ground 0V 28 D5 Digital output CMOS output (2.5V)
5 VIN Analog input 1Vpp 29 D4 Digital output CMOS output (2.5V)
6 AGND Analog ground 0V 30 D3 Digital output CMOS output (2.5V)
7 VINB Inverted analog input 1Vpp 31 D2 Digital output CMOS output (2.5V)
8 AGND Analog ground 0V 32 D1 Digital output CMOS output (2.5V)

9 INCM Input common mode 0.5V 33 D0(LSB) Least Significant Bit output CMOS output (2.5V)
10 AGND Analog ground 0V 34 NC Non connected
1 1 AVCC Analog p ower supply 2.5V 35 NC Non connected
12 AVCC Analog power supply 2.5V 36 NC Non conn ected
13 DVCC Digital power s upply 2. 5V 37 NC Non connected
14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS out pu t (2.5V)
15 DGND Digital ground 0V 39 VCCB Digital Buffer power supply 2.5V
16 CLK Clock input 2.5V compatible CMOS input 40 GNDB Digital Buffer ground 0V
17 DGND Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V
18 NC Non connected 42 NC Non connected
19 DGN D Digita l ground 0V 43 NC Non connected
20 GND B Digital buffer ground 0V 44 OEB Output Enable i nput 2.5V compatible CMOS input
21 GNDB Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V compatible CMOS input
22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V
23 OR Out Of Range output CMOS output (2.5V) 47 AVCC Analog power supply 2.5V
24 D9(MSB) Most Significant Bit output CMOS output (2.5V) 48 AGND Analog ground 0V

3/19

TSA1001

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

FS Sampling Frequency 0.5 25 MHz

DC Clock Duty Cycle 45 50 55 %
TC1 Clock pulse width (high) 18 20 ns
TC2 Clock pulse width (low) 18 20 ns

Tod

Data Output Delay (Fall of Clock
to Data Valid)

Tpd Data Pipeline delay 6.5 cycles

Ton

Toff

Falling edge of OEB to digital
output valid data

Rising edge of OEB to digital
output tri-state

10pF load capacitance

5ns

1ns

1ns

TIMING DIAGRAM

N-1

CLK

OEB

Tod

DATA

OUT

DR

N-8

N+4

N+3

N+2

N-7

N+1

N-6

N-5

6.5 clk cycles

N-4

N

Toff

N+5

N-2N-3

N+6

N+7

N+8

Ton

N

N+1

HZ state

4/19

TSA1001

CONDITIONS:

AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

Symbol Parameter Test conditions Min Typ Max Unit

VIN-VINB Full scale refere nce voltag e 2.0 Vpp

Cin Input capacitance 7. pF

BW Analog Input Bandwitdh Vin@Full Scale, FS=25Msps 100 MHz

ERB

1). See parameters defini t i o n for more information

Effective Resolution Bandwidth

REFERENCE VOLTAGE

Symbol Parameter Test conditions Min Typ Max Unit

1)

60 MHz

VREFP Top internal reference voltage

Tmin= -40°C to Tmax= 85°C

1)

0.90 1.16 V

1.20 1.27 1.35 V

0.91 1.03 1.15 V

Vpol Analog bias voltage

Tmin= -40°C to Tmax= 85°C

1)

1.19 1.36 V

Ipol Analog bias current Normal operating mode 25 50 70 µA
Ipol Analog bias current Shutdown mode 0 µA

0.48 0.57 0.65 V

VINCM Input common mode voltage

Tmin= -40°C to Tmax= 85°C

1). Not fully tes ted over the te m perature range. Guaranted by sampling.

1)

0.48 0.66 V

5/19

TSA1001

CONDITIONS:

AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

Symbol Parameter Test conditions Min Typ Max Unit

1)

ICCA Analog Supply current

Tmin= -40°C to Tmax= 85°C

1)

ICCD Digital Supply Current

Tmin= -40°C to Tmax= 85°C

1)

ICCB Digital Buffer Supply Current

Tmin= -40°C to Tmax= 85°C

ICCBZ

PdZ

Rthja

Rthjc

1).Rpol= 25KΩ. E quiva l en t l oad: Rloa d= 470Ω and Cload= 6pF

2). Not fully tes ted over the te m perature range. Guaranted by sampling.

Digital Buffer Supply Current in
High Impedance Mode

Power consumption in normal

Pd

operation mode

Power consumption in High
Impedance mode

Junction-ambient thermal resis­tor (TQFP48)

Junction-case thermal resistor
(TQFP48)

1)

1)

Tmin= -40°C to Tmax= 85°C

1)

DIGITAL INPUTS AND OUTPUTS

1 1.8 14 mA

2)

14 mA

12mA

2)

2mA

1.4 5 mA

2)

5mA

40 100 µA

35 47 mW

2)

47 mW

32 37 mW

80 °C/W

18 °C/W

Symbol Parameter Test conditions Min Typ Max Unit

Digital inputs

VIL Logic "0" voltage 0.8 V
VIH Logic "1" voltage 2.0 V

Digital Outputs

VOL Logic "0" voltage Iol=10µA 0.4 V
VOH Logic "1" voltage Ioh=10µA 2.4 V
IOZ High Impedance leakage current OEB set to VIH -1.5 1.5 µA

C

Output Load Capacitance 15 pF

L

ACCURACY

Symbol Parameter Test conditions Min Typ Max Unit

OE Offset Error -5 ±0.1 +5 %

DNL Differential Non Linearity -0.7 ±0.3 +0.7 LSB

INL Integral Non Linear ity -0.8 ±0.3 +0.8 LSB

Monotonicity and no missing

6/19

­codes

Guaranted

TSA1001

CONDITIONS:

AVCC = DVCC = 2.5V, Fs= 25Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

Fin= 5MHz

1)

Fin= 10MHz

SFDR Spurious Free Dynamic Range

Fin= 5MHz

2)

Fin= 10MHz

1)

2)

SNR Signal to Noise Ratio

Fin= 5MHz
Fin= 10MHz

Fin= 5MHz
Fin= 10MHz

1)

2)

THD Total Harmonic Distortion

Fin= 5MHz
Fin= 10MHz

Fin= 5MHz
Fin= 10MHz

1)

2)

SINAD

Signal to Noise and Distortion­Ratio

Fin= 5MHz
Fin= 10MHz

Fin= 5MHz
Fin= 10MHz

1)

2)

ENOB Effective Number of Bits

Fin= 5MHz
Fin= 10MHz

Fin= 5MHz
Fin= 10MHz

1). Rpol= 25KΩ. Equivalent load: Rload= 470Ω and Clo ad= 6pF

2).Tmin= -40°C to Tmax= 85°C. Not fully tested over th e temperatur e range. Guara nt ed by sampling .

66
66

66
66

58
58

58
58

63
63

62
62

58
58

58
58

9.5

9.5

9.5

9.5

80.5
76

59.3

59.3

79.5
75

59.0

59.0

9.70

9.70

dBc

dBc

dB

dB

dB

dB

dB

dB

bits

bits

7/19

TSA1001

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 25Msps, which is high enou gh to fully
characterize the test frequ ency response. The in­put level is +1dBFS to saturate the signal.

Differential Non Linearity (DNL)

The average deviation of any output code width
from the ideal code width of 1LSB.

Integral Non linearity (INL)

An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.

DYNAMIC PARAMETERS

Dynamic measurements are performed by
spectral analysis, appli ed to an inp ut sinewave of
various frequencies and sampled at 25Msps.

Spurious Free Dynami c R ange (SFDR)

The ratio between the amp litude of fundament al
tone (signal power) and the power of the worst
spurious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dBc.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the f irst five harm oni c
distortion components to the rms value of the
fundamental line. It is expressed in dB.

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (f
DC, fundamental and the first five harmonics.

/2) excluding

s

SNR is reported in dB.

Signal to Noise and Distorsion Ratio (SINAD)

Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A
becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A

amplitude, the SINAD expression

0

/FS)

0

The ENOB is expressed in bits.

Analog Input Bandwidth

The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.

Pipeline delay

Delay between time when the analog input is
initially sampled and time when the corresponding
digital data output is valid on the output bus. Also
called data latency. It is expressed as a number of
clock cycles.

8/19

EQUIVALENT CIRCUITS

TSA1001

Figure 1 : Analog Input Circuit

AVCC=2.5V

VIN

(or V IN B )

PAD
CAPACITANCE

7 pF

AGND=0V

Figure 2 : Input clock circuit

DVCC=2.5V

CLK

common mode

Figure 3 : Input buffers

VCC buf=2.5V

Ω278.5 Ω208.2Ω355.5

DFS

7 pF

PAD
CAPACITANCE

GND buff=0V

Figure 4 : Tri-state output buffers

VCC buf=2.5V

OE

PAD
CAPACITANCE

7 pF

DGND=0V

DATA

GN D bu ff=0V

GND buff =0V

VCC b u f =2 .5V

OUT

2 mA
OUTPUT
BUFFER

PAD CAPAC ITANCE
7pF

9/19

TSA1001

Static parameter: Integral Non Linearity

Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072pts

0.4

0.3

0.2

0.1

0

-0.1

INL (LSBs)

-0.2

-0.3

-0.4

-0.5
0 200 400 600 800 1000

Output C ode

Static parameter: Differential Non Linearity

Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072 pts

0.3

0.2

0.1

0

DNL (LSBs)

-0.1

-0.2

-0.3
0 200 400 600 800 1000

Linearity vs. AVcc

Fs=25MSPS; Icca=1 1mA; Fin=1MHz

61

60.5

60

59.5

59

58.5

Dynamic parameters (dB)

58

2.25 2.35 2.45 2.55 2.65

SNR

SINAD

ENOB

AVCC (V)

10

9.95

9.9

9.85

9.8

9.75

9.7

9.65

9.6

Output Code

ENOB (bits)

Distortion vs. AVcc

Fs=25MSPS; Icca=1 1mA; Fin=1MHz

-67

-69

-71

-73

-75

-77

-79

-81

-83

Dynamic Parameters (dB)

-85

2.25 2.35 2.45 2.55 2.65

THD

SFDR

AVCC (V)

10/19

TSA1001

Linearity vs. DVcc

Fs=25MSPS; Icca=11mA; Fin=1MHz

61

60.5

60

59.5

59

58.5

SNR

SINAD

ENOB

Dynamic parameters (dB)

58

2.25 2.35 2.45 2.55 2.65

DVCC (V)

Linearity vs. VccB
Fs=25MSPS; Icca=11mA; Fin=1MHz

61

60.5

60

59.5

59

58.5

Dynamic parameters (dB)

58

2.25 2.35 2.45 2.55 2.65

SNR

SINAD

ENOB

VCCB (V)

10

9.95

9.9

9.85

9.8

9.75

9.7

10

9.95

9.9

9.85

9.8

9.75

9.7

9.65

9.6

Distortion vs. DVcc

Fs=25MSPS; Icca=11mA; Fin=1MHz

-70

-71

-72

-73

-74

-75

ENOB (bits)

-76

-77

-78

-79

Dynamic Parameters (dB)

-80

2.25 2.35 2.45 2.55 2.65

THD

SFDR

DVCC (V)

Distortion vs. VccB
Fs=25MSPS; Icca=11mA; Fin=1MHz

-71

-73

-75

-77

ENOB (bits)

-79

-81

-83

Dynamic Parameters (dB)

-85

2.25 2.35 2.45 2.55 2.65

THD

SFDR

VCCB (V)

Linearity vs. Fs

Icca=11mA; Fin=1MHz

64
62
60
58
56
54
52

Dynamic parameters (dB)

50

5 15253545

Fs (MHz)

ENOB

SNR

SINAD

10

9.5

9

8.5

8

7.5

7

Distortion vs. Fs

Icca=11mA; Fin=1MHz

-50

-55

-60

-65

ENOB (bits)

-70

-75

-80

Dynamic parameters (dB)

-85
5 15253545

THD

SFDR

Fs (MHz)

11/19

TSA1001

y

p

(

)

R

Linearity vs. Fs

Icca=11mA; Fin=15MHz

64
62
60
58
56
54
52

Dynamic parameters (dB)

50

5 15253545

Fs (MHz)

Linearity vs. Fin
Fs=25MSPS; Icca=11mA

70
68
66
64
62
60
58
56

Dynamic parameters (dB)

54

0 204060

SINAD

Fin (MH z)

SINAD

SNR

SNR

ENOB

ENOB

10

9.8

9.6

9.4

9.2
9

8.8

8.6

8.4

8.2
8

10

9.5

9

8.5

8

7.5

7

Distortion vs. Fs

Icca=11mA; Fin=15MHz

-50

-55

-60

-65

-70

ENOB (bits)

-75

-80

-85

Dynamic parameters (dB)

-90
5 15253545

THD

SFDR

Fs (MHz)

Distortion vs. Fin

Fs=25MSPS; Icca=11mA

-40

-45

dB

-50

-55

-60

-65

arameters

ENOB (bits)

-70

-75

-80

namic

-85

D

-90
010203040506070

Fin (MH z)

THD

SFD

Linearity vs.Temperatur e

Fs=25MSPS; Icca=11mA; Fin=5MHz

60

59.8

59.6

59.4

59.2
59

58.8

58.6

58.4

58.2

Dynamic Parameters (dB)

58

-50 0 50 100

SNR

SINAD

ENOB

Temperature (°C)

10

9.95

9.9

9.85

9.8

9.75

9.7

9.65

9.6

Distortion vs. Temperature

Fs=25MSPS; Icca=11mA; Fin=5MHz;

80

78

76

74

72

70

Dynamic Parameters (dB)

68

-50 0 50 100

THD

SFDR

Temperature (°C)

12/19

TSA1001 APPLICATION NOTE

DETAILED INFORMATION

The TSA1001 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.

The pipeline structure cons ists of 9 internal con­version stages in whi ch the analog signal is fed
and sequencially converted into digital data.

Each 8 first stages consists of an Analog to Digital
converter, a Digital to Analog converter, a Sample
and Hold and a gain of 2 amplifier. A 1. 5bit conver­sion resolution is achieved in e ach s tage . The lat­est stage simply is a comparator. Each res ulting
LSB-MSB couple is then time shifted to recover
from the conversion delay. Digital data correction
completes the process ing by recovering from the
redundancy of the (LSB-MSB) couple for each

OPERATIONAL MODES DESCRIPTION

Inputs Outputs

Analog input differential level DFSB OEB OR DR Most Significant Bit (MSB)

(VIN-VINB) > RANGE H L H CLK D9

-RANGE > (VIN-VINB) H L H CLK D9

RANGE> (VIN-VINB) >-RANGE H L L CLK D9

(VIN-VINB) > RANGE L L H CLK Complemented D9

-RANGE > (VIN-VINB) L L H CLK Complemented D9

RANGE> (VIN-VINB) >-RANGE L L L CLK Complemented D9

XXHHZHZHZ

stage. The corrected data are outputed through
the digital buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the fall­ing edge of the Data Ready signal.
The advantages of such a convert er reside in the
combination of pipeline architec ture and the most
advanced technologies. The highest dynamic per­formances are achieved while consumption re­mains at the lowest level.
Some functionalities hav e been added i n order to
simplify as much as possible the application
board. These operational m odes are described in
the following table.
The TSA1001 is pin to pin compatible with the
8bits/40Msps TSA0801, the 10bits/50Msps
TSA1002 and t he 12bits/50Msps TSA1201. T his
ensures a conformity within the product family and
above all, an easy upgrade of the application.

Data Format Select (DFSB)

When set to low level (VIL), the digital input DFSB

provides a tw o’s complement d igital output MSB.
This can be of interest when performing some fur­ther signal processing.

When set to high level (VIH), DFSB provides a
standard binary output coding.

Output Enable (OEB)

When set to low level (VIL), all digital outputs re­main active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. This results in

13/19

lower consumption while the converter goes on
sampling.
When OEB is set to low level again, , the data is
then valid on the output with a very short Ton de­lay.
The timing diagram summarizes this operating cy­cle.

Out of Range (OR)

This function is im plemented on the output stage
in order to set up an "Out of Range" flag whenever
the digital data are over the full scale range.
Typically, there is a detection of all the dat a bei ng
at ’0’ or all the data being at ’1’. This ends up with
an output signal OR which is in low level state

TSA1001

(VOL) when the data stay within the range, or in
high level state (VOH) when the data is out of the
range.

Data Ready (DR)

The Data Ready output is an image of the clock
being synchronized on the output data (D0 to D9).
This is a very helpful signal that simplifies the syn­chronization of the measurement equipment or
the cont ro llin g DSP.

As digital output, DR goes in high impedance state
when OEB is as serted to High level as described
in the timing diagram.

DRIVING THE ANALOG INPUT
Differentia l inp u t s

The TSA1001 has been designed to obtain opti­mum performances when being differentially driv­en. An RF trans former is a good wa y to achieve
such performances.

Figure 5 describes the schematics. The input s ig­nal is fed to the primary of the transformer, while
the secondary drives both A DC inputs. The com­mon mode voltage of the ADC (INCM) is connect­ed to the center-tap of the secondary of the trans­former in order to bias the input signal around this
common voltage, internally set to 0.56V. The
INCM is decoupl ed to maintain a low noi se level
on this node. Our evaluation board is mounted
with a 1:1 ADT1-1 tran sformer from Minicircuits.
You might a lso use a higher impedance ratio (1:2
or 1:4) to reduce the driving requirement on the
analog signal source.

Each analog input can drive a 1Vpp amplitude in­put signal, so the resultant differential amplitude is
2Vpp.

Figure 5 : Differential input configuration

Analog source

50Ω

ADT1-1

1:1

330pF

100pF

10nF

VIN

TSA1001

VINB

INCM

470nF

Single-ended input configuration

Some applications may requi re a single-ende d in­put which is easily achieved with the configuration
reported on Figure 6.

In this case, it is recommended to use an
AC-coupled analog input and connect the other
analog input to the common mode voltage of the
circuit (INCM) so as to properly bi as the ADC. The
INCM may remain at the same internal level
(0.56V) thus driving only a 1Vpp i nput amplitude,
or it must be increased to 0.9V to drive a 2Vpp
input amplitude. You wi ll get higher pe rform ances
using a 2Vpp signal.

Figure 6 : Single-ended input configuration

Signal source

50Ω

100nF

330pF

VIN

TSA1001

VINB

INCM

10nF

470nF

0.9V

Dynamic characteristics, while not being as re­markable as for differential configuration, are still
of very good quality. Measurements done at
25Msps, 1MHz input frequency, -1dBFS input lev­el sum up these performances. An SFDR of

-69.5dBc, an SNR of 59.5dB and an ENOB Full
Scale of 9.7bits are achieved.

REFERENCE CONNECTION
Inte rnal ref erence

In the standard configuration, the ADC is bi ased
with the internal reference voltage. VREFM pin is
connected to Analog Ground while VREFP is
internally set to a voltage of 1.03V. It is
recommended to d ecouple the V R EF P i n order to
minimize low and high frequency noise. Refer to
Figure 7 for the schematics.

Figure 7 : Internal reference setting

VIN

1.03V
VREFP

330pF

10nF

470nF

TSA1001

VINB

VREFM

14/19

TSA1001

External reference

It is possible to use an external reference voltage
instead of the internal one for specific applications
requiring even better linearity or enhanced
temperature behaviour. In this case, the amplitude
of the external voltage must be at least equal to
the internal one (1.03V). Using the
STMicroelectronics Vref TS821 leads to optimum
performances when configured as shown on
Figure 8.

Figure 8 : External reference setting

1k

Ω

10nF

470nF

VCCA

VIN

TSA1001

VINB

VREFP

VREFM

330pF

TS821

external
reference

At 15Msps sampling frequency, 1MHz input fre­quency and -1dBFS amplitude signal, perfor­mances can be improved of up to 2dBc on SFD R
and 0.3dB on SINAD. At 25Msps sampling fre­quency, 1MHz input frequency and -1dBFS ampli­tude signal, performanc es can be improve d of up
to 1dBc on SFDR and 0.5dB on SINAD.

This can be very helpful for example for multichan­nel application to keep a good matching among
the sampling frequency range.

Clock input

The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture jit­ter; the use of low jitter crystal controlled oscillator
is recommended.

The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from

the ADC output ones to avoid digital noise modu­lation at the output.

It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.

Power con s um p t io n optimizatio n

The internal architecture of the TSA10 01 enables
to optimize the power c onsumption according to
the sampling frequency of the application. For this

purpose, a resistor is placed between I POL and
the analog Ground pins.

The TSA1001 will com bine highest performa nces
and lowest consumption at 25Msps when Rpol is
equal to 25kΩ.

At lower sampling frequency range (< 10Msps),
this value of resistor may be adjusted in order to
decrease the analog current without any
degradation of dynamic performances.

As an example, 10mW total power consumption is
achieved at 5 Msps with Rpol equal to 390kΩ.

The table below sums up the relevant data.

Total power consumption optimization
depending on Rpol value

Fs (Msps) 5 15 25

kΩ)

Rpol (
Optimized

power (mW)

390 40 25

10 25 35

Layout precautions

To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:

- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is mandatory for high speed circuit
applications to provide low inductance and low
resistance common return.

The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.

- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.

- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the am plifier will be im proved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.

- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.

- Choose component sizes as small as possible
(SMD).

15/19

TSA1001

EVAL1002 evaluation board

The characterization of the board has been made
with a fully ADC devoted test bench as shown on
Figure 10. The analog signal must be filtered t o be
very pure.

The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the octal
buffers 74LCX573.
All characterization measurements have been
made with: SFSR=+0.2dB for static parameters.­SFSR=-0.5dB for dynamic parameters.

Figure 9 : Analog to Digital Converter characterization bench

Power

HP8644B

Sine wave
Generator

Vin

HP8133A

ADC

evaluation

board

ck

Pulse

Generator

data

dataready

Analyzer

TLA704

Logic

HP8644B

Sine Wave
Generator

16/19

Figure 10 : TSA1001 Evaluation board schematic

TSA1001

J6

123456789

DR

2

VCCB2

1

J17

VDDBUFF3V

+

C34

47µ

2
1

J13

2
1

J11

2
1

J10

OEB

2
1

J9

DFSB

R10

47K

R11

47K

R12

47K

R13

47K

10nF

C26

C39

C37

470nF

VCCB1

10nF

C25

C27

C28

470nF

AVCC

C14

C15

10nF

C16

470nF

Raj1

47K

R2

D1D2D3D4D5

DO

20

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

330pF

OEB1D02D13D24D35D46D57D68D79GND

R19

47K

R18

47K

R17

47K

R16

47K

R15

47K

R14

47K

330pF

330pF

1K

1011121314151617181920212223242526272829303132

D7D8D9

D6

D10

D11

20

12

11

LE

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

U2

36

D0

37

DR

38
39
40
41

NC

42

NC

43

OEB

44

DFSB

45

AVCC

46

AVCC

47

AGND

48

Ipol1Vref P2Vref M3AGND4Vin5AGND6VINB7AGND8INCM9AGND10AVCC11AVCC

C11

330pF

C12

10nF

C13

470nF

C30

330pF

10nF

C31

C32

470nF

74LCX573

OEB1D02D13D24D35D46D57D68D79GND

10

2.5VCCBUFF

GNDBUFF

2.5VCCBUFF

8-14bits ADC

TSA1001

U3

27

D928D829D730D631D532D433D334D235D1

D1225D1126D10

D13
OR

2.5VCCBUFF
GNDBUFF
GNDBUFF
DGND
NC
DGND
CLK
DGND
DVCC
DVCC

12

C2

330pF

C4

10nF

C3

470nF

32PIN

OR

D12

D13

12

11

LE

74LCX573

10

24
23
22
21
20
19
18
17
16
15
14
13

C38

C29

C40

470nF

+

C17

10µF

T1

43
2

6

C20

10nF

C33

330pF

VCCB1

1
2

+

J18

330pF

C18

10nF

C19

470nF

C24

T2-AT1-1WT

R3

50

1

330pF

C21

10nF

C22

470nF

C23

VccB1

10µ

C35

47µ

J4

CLJ/SMB

1
2

J16

CON2

C36

47µ

+

1

10µ

2

J15

DVCC

AVCC

C5

330pF

C8

330pF

C1

100pF

C6

10nF

C9

10nF

4326

C7

470nF

C10

470nF

T2

T2-AT1-1WT

R1

50

1

1

2

1

J2

2

Vref P

J5

Vref M

J1

Vin

1

2

1

J7

Regl com mode

J8

C41

10µF

C42

47µF

+

1

2

2

Mes co m Mode

1

2

1

2

1

2

1

J12

AVCC

J19

AGND

J20

DGND

J21

2

GndB2

J22

GndB1

17/19

TSA1001

Regl com mode

74LCX 573

74LCX 573

Figure 11 : Printed circuit board - Top side silkscreen

Print ed circui t board - Li st of comp onents

Part Design Footprint Part Design Footprint Part Design Foo tprint P art D esign F ootprint

ator

Type
10 u F C 2 4 1210
10 u F C 2 3 1210
10 u F C 4 1 1210
10 u F C 2 9 1210
100pF C1 603
10 n F C 12 6 0 3
10 n F C 3 9 6 0 3
10 n F C 15 6 0 3
10 n F C 4 0 6 0 3
10 n F C 2 7 6 0 3
10 n F C 4 6 0 3
10 n F C 2 1 6 0 3
10 n F C 3 1 6 0 3
10 n F C 6 6 0 3
10 n F C 9 6 0 3
10 n F C 18 6 0 3
1K

R2 603

Ω

32P IN J6 IDC32
330pF C 25 603

330pF C 26 603

ator

Type
330pF C33 603 470nF C7 805 AVCC J12 FICHE2M M
330pF C20 603 470nF C16 805 CLJ/SM B J4 SM B/H
330pF C8 603 470nF C19 805 AGND J19 FICHE2MM
330pF C2 603 470nF C3 805 DFSB J9 FICHE2M M
330pF C5 603
330pF C11 603
330pF C30 603
330pF C17 603
330pF C14 603
47uF C36 C A P
47uF C34 C A P
47uF C35 C A P
47uF C42 C A P
470nF C22 805
470nF C32 805
470nF C37 805
470nF C38 805
470nF C13 805
470nF C28 805
470nF C10 805 C O N 2 J16 SIP2

Type

47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
50
50

ator

Ω R12 603 DGND J20 FICHE2MM
Ω

R14 603 DVCC J15 FICHE2M M

Ω R11 603 GndB1 J22 FICHE2M M
Ω

Raj1 VR5 GndB2 J21 FICHE2MM

Ω R 10 603 M es com m o de J8 F ICH E 2M M
Ω

R19 603 OEB J10 FICHE2MM

Ω R13 603
Ω

R15 603 T2-A T1-1WT T2 ADT

Ω

R16 603 T2-A T1-1WT T1 ADT

Ω

R17 603 VccB1 J18 FICHE2MM

Ω

R18 603 VDDBUFF3V J17 FICHE2M M

Ω

R3 603 Vin J1 SM B/H

Ω

R1 603 VrefM J5 FICHE2M M
U3 T S SO P 20 VrefP J2 F ICH E2M M
U2 TS S OP 2 0 TS A 1001 U1 T Q F P 48

Type

ator

J7 F ICH E 2M M

18/19

PACKAGE MECHANICAL DATA
48 PINS - PLASTIC PACKAGE

48 37

e

1

36

E3

E1

TSA1001

A

A2

A1

0,10 mm
.004 inch

SEATING PLANE

B

E

12

13 24

D3

25

c

D1

D

L1

L

0,25 mm
.010 inch

K

Millimeters Inches

Dim.

Min. Typ. Max. Min. Typ. Max.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.216

e 0.50 0.0197

E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.216

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0° (min.), 7° (max.)

Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lication or otherwise under any patent or patent rig hts of STMicroelectronics. Specificat ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.

© The ST logo is a registered trademark of STMicroelectronics

GAGE PLANE

© 2000 STM icroelectronics - Pri n ted in Italy - All Ri g h ts Reserved

STMicr o el ectronics GROUP OF COMPANI E S

Australi a - Brazil - China - Finland - F rance - Germany - Hong Kong - I ndi a - Italy - Japan - Malaysia - Malta - Morocc o

Singapo re - Spain - Swe den - Switzerl and - United Kingdom

© http://www.st.com

19/19