Datasheet TS80C52X2 Datasheet (TEMIC)

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8-bit CMOS Microcontroller 0-60 MHz

1. Description

TS80C52X2

TEMIC TS80C52X2 is high performance CMOS ROM,
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.

In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) andaX2speed
improvement mechanism.

2. Features

● 80C52 Compatible

• 8051 pin and instruction compatible

• Four 8-bit I/O ports

• Three 16-bit timer/counters

• 256 bytes scratchpad RAM

● High-Speed Architecture

• 40 MHz @ 5V, 30MHz @ 3V

• X2 Speed Improvement capability (6 clocks/

machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

● Dual Data Pointer

● On-chip ROM/EPROM (8K-bytes)

● Programmable Clock Out and Up/Down Timer/

Counter 2

● Asynchronous port reset

The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.

The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.

● Interrupt Structure with

• 6 Interrupt sources,

• 4 level priority interrupt system

● Full duplex Enhanced UART

• Framing error detection

• Automatic address recognition

● Low EMI (inhibit ALE)

● Power Control modes

• Idle mode

• Power-down mode

• Power-off Flag

● Once mode (On-chip Emulation)

● Power supply: 4.5-5V, 2.7-5.5V

● Temperature ranges: Commercial (0 to 70

Industrial (-40 to 85oC)

● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9 footprint), CQPJ44 (window), CDIL40
(window)

o

C) and

Rev. B - Jan. 25, 1999 1

Preliminary

TS80C52X2

Table 1. Memory size

3. Block Diagram

XTAL1
XTAL2

PROG

ALE/

PSEN

EA/V

PP

RD

WR

ROM (bytes) EPROM (bytes)

TOTAL RAM

(bytes)

TS80C32X2 0 0 256
TS80C52X2 8k 0 256
TS87C52X2 0 8k 256

RxD

(3)
(3)

CPU

(3)(3)

EUART

Timer 0
Timer 1

TxD

C51

CORE

RAM
256x8

INT
Ctrl

IB-bus

Vss

Vcc

ROM

/EPROM

8Kx8

Parallel I/O Ports & Ext. Bus

Port 0

Port 1

Port 2

T2EX

(1) (1)

Timer2

Port 3

T2

(3) (3) (3) (3)

RESET

P1

T0

T1

INT1

INT0

(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3

P0

P2

P3

2 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

4. SFR Mapping

The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port registers: P0, P1, P2, P3

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• Power and clock control registers: PCON

• PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi

• Interrupt system registers: IE, IP, IPH

• Others: AUXR, CKCON

Table 2. All SFRs with their address and their reset value

Bit

address-

able

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h FFh
F0h

E8h EFh
E0h

D8h DFh
D0h

C8h

C0h C7h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

B

0000 0000

ACC

0000 0000

PSW

0000 0000

T2CON

0000 0000

IP

XX00 0000

P3

1111 1111

IE

0X00 0000

P2

1111 1111

SCON

0000 0000

P1

1111 1111

TCON

0000 0000

P0

1111 1111

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

T2MOD

XXXX XX00

SADEN

0000 0000

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

SP

0000 0111

RCAP2L

0000 0000

AUXR1

XXXX 0XX0

TL0

0000 0000

DPL

0000 0000

Non Bit addressable

RCAP2H

0000 0000

TL1

0000 0000

DPH

0000 0000

TL2

0000 0000

TH0

0000 0000

TH2

0000 0000

TH1

0000 0000

AUXR

XXXXXX00

IPH

XX00 0000

CKCON

XXXX XXX0

PCON

00X1 0000

F7h

E7h

D7h

CFh

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

reserved

Rev. B - Jan. 25, 1999 3

Preliminary

TS80C52X2

5. Pin Configuration

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5
P1.6

P1.7

RST
P3.0/RxD
P3.1/TxD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

P3.6/WR

P3.7/RD

XTAL2
XTAL1

VSS

1

2

3
4

5

6
7

8
9
10
11

12

13

14
15
16
17

18
19

20

PDIL/

CDIL40

40

39
38

37
36

35
34
33

32
31
30

29

28

27
26

25

24

23
22

21

VCC
P0.0
P0.1

P0.2

P0.3

P0.4
P0.5
P0.6
P0.7
EA/VPP
ALE/PROG
PSEN
P2.7

P2.6
P2.5

P2.4
P2.3

P2.2
P2.1
P2.0

P1.4

P1.3

P1.1/T2EX

P1.2

P1.0/T2

VSS1/NIC*

VCC

RST

P3.0/RxD

NIC*

P3.1/TxD
P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

P0.0/AD0

P0.1/AD1

P1.5
P1.6
P1.7

P0.2/AD2

P0.3/AD3

P1.4

5 4 3 2 1 6

7

8
9
10
11

12
13

14
15
16
17

P1.3

PLCC/CQPJ 44

P1.1/T2EX

P1.2

P1.0/T2

VSS1/NIC*

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

NIC*

VSS

XTAL2

XTAL1

P3.7/RD

P3.6/WR

VCC

P0.0/AD0

P2.0/A8

P2.1/A9

P0.2/AD2

P0.1/AD1

P2.2/A10

P2.3/A11

P0.3/AD3

39

38
37
36
35

34

33

32
31
30
29

P2.4/A12

P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

P3.2/INT0
P3.3/INT1

*NIC: No Internal Connection

P1.5
P1.6
P1.7
RST

P3.0/RxD

NIC*

P3.1/TxD

P3.4/T0

P3.5/T1

43 42 41 40 3944

1

2

3
4

5

6
7

8
9
10
11

38 37 36 35 34

PQFP44

VQFP44

12 13 14 15 16 17 18 19 20 21 22

VSS

NIC*

XTAL1

P3.7/RD

P3.6/WR

XTAL2

P2.0/A8

P2.1/A9

P2.2/A10

33

32
31
30
29

28

27

26
25
24
23

P2.3/A11

P2.4/A12

P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

4 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 3. Pin Description for 40/44 pin packages

MNEMONIC

V

SS

Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V

CC

P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

P1.0-P1.7 1-8 2-9 40-44

P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

P3.0-P3.7 10-17 11,

Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,

PIN NUMBER

DIL LCC VQFP 1.4

20 22 16 I Ground: 0V reference

40 44 38 I

1-3

1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

5,

13-19

10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe

7-13

TYPE

Power Supply: This is the power supply voltage for normal, idle and power-

down operation

written to them float and can be used as high impedance inputs.Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for Port 1 include:

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification:
P2.0 to P2.4

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.

resets the device. An internal diffused resistor to VSSpermits a power-on reset
using only an external capacitor to V

NAME AND FUNCTION

CC.

Rev. B - Jan. 25, 1999 5

Preliminary

TS80C52X2

Table 3. Pin Description for 40/44 pin packages

MNEMONIC

ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte

PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When

EA/V

PP

XTAL1 19 21 15 I

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier

PIN NUMBER TYPE

of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.

executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally

held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is
held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must
be held low for ROMless devices. This pin also receives the 12.75V programming
supply voltage (VPP) during EPROM programming. If security level 1 is
programmed, EA will be internally latched on Reset.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.

NAME AND FUNCTION

6 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

6. TS80C52X2 Enhanced Features

In comparison to the original 80C52, the TS80C52X2 implements some new features, which are:

• The X2 option.

• The Dual Data Pointer.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mode.

• The ALE disabling.

• Some enhanced features are also located in the UART and the timer 2.

6.1 X2 Feature

The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:

● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

● Save power consumption while keeping same CPU power (oscillator power saving).

● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

● Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.

6.1.1 Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.

XTAL1:2

XTAL1

F

XTAL

2

0
1

X2

CKCON reg

Figure 1. Clock Generation Diagram

F

OSC

state machine: 6 clock cycles.
CPU control

Rev. B - Jan. 25, 1999 7

Preliminary

TS80C52X2

XTAL1

XTAL1:2

X2 bit

CPU clock

X2 ModeSTD Mode STD Mode

Figure 2. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.

8 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 4. CKCON Register

CKCON - Clock Control Register (8Fh)

7 6 5 4 3 2 1 0

- - - - - - - X2

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 -

0 X2

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

CPU and peripheral clock bit

Reset Value = XXXX XXX0b
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F

OSC=FXTAL

OSC=FXTAL

).

/2).

Rev. B - Jan. 25, 1999 9

Preliminary

TS80C52X2

6.2 Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).

External Data Memory

07

DPS

AUXR1(A2H)

DPH(83H) DPL(82H)

DPTR1

DPTR0

Figure 3. Use of Dual Pointer

10 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 5. AUXR1: Auxiliary Register 1

7 6 5 4 3 2 1 0

- - - - - - - DPS

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 -

0 DPS

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Data Pointer Selection

Reset Value = XXXX XXX0
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Clear to select DPTR0.
Set to select DPTR1.

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.

Rev. B - Jan. 25, 1999 11

Preliminary

TS80C52X2

ASSEMBLY LANGUAGE

; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.

12 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

6.3 Timer 2

The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the TEMIC 8-bit Microcontroller Hardware
description.

Refer to the TEMIC 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate
Generator Modes.

In TS80C52X2 Timer 2 includes the following enhancements:

● Auto-reload mode with up or down counter

● Programmable clock-output

6.3.1 Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the TEMIC 8-bit Microcontroller Hardware description).
If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin
controls the direction of count.

/12 (timer operation) or external pin T2 (counter operation)

OSC

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.

Rev. B - Jan. 25, 1999 13

Preliminary

TS80C52X2

XTAL1

F

XTAL

F

:12

OSC

T2

(DOWN COUNTING RELOAD VALUE)

FFh

(8-bit)

TL2

(8-bit)

RCAP2L

(8-bit)

(UP COUNTING RELOAD VALUE)

0
1

C/T2

T2CONreg

FFh

(8-bit)

TH2

(8-bit)

RCAP2H

(8-bit)

Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1)

TR2

T2CONreg

T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting

TOGGLE

TF2

T2CONreg

T2CONreg

EXF2

TIMER 2

INTERRUPT

6.3.2 Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The
input clock increments TL2 at frequency F
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers :

Clock OutFrequency–

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz

OSC

16)

/2

to 4 MHz (F

/4). The generated clock signal is brought out to T2 pin (P1.0).

OSC

(F
Timer 2 is programmed for the clock-out mode as follows:

● Set T2OE bit in T2MOD register.

● Clear C/T2 bit in T2CON register.

● Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.

● Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different

one depending on the application.

/2. The timer repeatedly counts to overflow from a loaded value.

OSC

F

--------------------------------------------------------------------------------------=
4 65536 RCAP2H– RCAP2L⁄()×

osc

14 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

● To start the timer, set TR2 run control bit in T2CON register.

It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.

T2EX

T2

XTAL1

:2

TR2

T2CON reg

Toggle

QD

EXEN2

T2CON reg

TL2

(8-bit)

RCAP2L

(8-bit)

T2OE

T2MOD reg

EXF2

T2CON reg

TH2

(8-bit)

RCAP2H

(8-bit)

OVEFLOW

TIMER 2

INTERRUPT

Figure 5. Clock-Out Mode C/T2=0

Rev. B - Jan. 25, 1999 15

Preliminary

TS80C52X2

Table 6. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7 6 5 4 3 2 1 0

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number

7 TF2

6 EXF2

5 RCLK

4 TCLK

3 EXEN2

2 TR2

1 C/T2#

Bit

Mnemonic

Description

Timer 2 overflow Flag

Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

Receive Clock bit

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to

clock the serial port.

Timer 2 Run control bit

Clear to turn off timer 2.
Set to turn on timer 2.

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

OSC

).

0 CP/RL2#

Reset Value = 0000 0000b
Bit addressable

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.

16 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 7. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7 6 5 4 3 2 1 0

- - - - - - T2OE DCEN

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 T2OE

0 DCEN

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Timer 2 Output Enable bit

Down Counter Enable bit

Reset Value = XXXX XX00b
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.

Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.

Rev. B - Jan. 25, 1999 17

Preliminary

TS80C52X2

6.4 TS80C52X2 Serial I/O Port

The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

● Framing error detection

● Automatic address recognition

6.4.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).

RITIRB8TB8RENSM2SM1SM0/FE

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD = 1)
SM0 to UART mode control (SMOD = 0)

PCON (87h)

IDLPDGF0GF1POF-SMOD0SMOD1

To UART framing error control

Figure 6. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.

18 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.).

RXD

SMOD0=X

FE

SMOD0=1

SMOD0=0

SMOD0=1

SMOD0=1

D7D6D5D4D3D2D1D0

Start

bit

RI

Data byte

Stop

bit

Figure 7. UART Timings in Mode 1

RXD

RI

RI

FE

Start

bit

Data byte Ninth

D8D7D6D5D4D3D2D1D0

bit

Stop

bit

Figure 8. UART Timings in Modes 2 and 3

6.4.2 Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).

Rev. B - Jan. 25, 1999 19

Preliminary

TS80C52X2

6.4.3 Given Address

Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:

SADDR 0101 0110b
SADEN 1111 1100b
Given 0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A: SADDR 1111 0001b

SADEN 1111 1010b
Given 1111 0X0Xb

Slave B: SADDR 1111 0011b

Slave C: SADDR 1111 0010b

The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).

SADEN 1111 1001b
Given 1111 0XX1b

SADEN 1111 1101b
Given 1111 00X1b

6.4.4 Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:

SADDR 0101 0110b

Broadcast =SADDR OR SADEN 1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:

Slave A: SADDR 1111 0001b

SADEN 1111 1100b

SADEN 1111 1010b
Broadcast 1111 1X11b,

Slave B: SADDR 1111 0011b

Slave C: SADDR= 1111 0010b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.

20 Rev. B - Jan. 25, 1999

SADEN 1111 1001b
Broadcast 1111 1X11B,

SADEN 1111 1101b
Broadcast 1111 1111b

Preliminary

TS80C52X2

6.4.5 Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards

compatible with the 80C51 microcontrollers that do not support automatic address recognition.

SADEN - Slave Address Mask Register (B9h)

7 6 5 4 3 2 1 0

Reset Value = 0000 0000b
Not bit addressable

SADDR - Slave Address Register (A9h)

7 6 5 4 3 2 1 0

Reset Value = 0000 0000b
Not bit addressable

Rev. B - Jan. 25, 1999 21

Preliminary

TS80C52X2

Table 8. SCON Register

SCON - Serial Control Register (98h)

7 6 5 4 3 2 1 0

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number

7 FE

6 SM1

5 SM2

4 REN

3 TB8

Bit

Mnemonic

SM0

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM1 SM0 Mode Description Baud Rate

0 0 0 Shift Register F
0 1 1 8-bit UART Variable

1 0 2 9-bit UART F
1 1 3 9-bit UART Variable

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.

Reception Enable bit

Clear to disable serial reception.
Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.

XTAL

XTAL

/12

/64 or F

XTAL

/32

2 RB8

1 TI

0 RI

Reset Value = 0000 0000b
Bit addressable

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

Receive Interrupt flag

Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.

22 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 9. PCON Register

PCON - Power Control Register (87h)

7 6 5 4 3 2 1 0

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number

7 SMOD1

6 SMOD0

5 -

4 POF

3 GF1

2 GF0

1 PD

0 IDL

Bit

Mnemonic

Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.
Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.

Reset Value = 00X1 0000b
Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.

Rev. B - Jan. 25, 1999 23

Preliminary

TS80C52X2

6.5 Interrupt System

The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9.

INT0

TF0

INT1

TF1

RI
TI

TF2

EXF2

Individual Enable

IE0

IE1

IPH, IP

3
0

3
0
3
0
3
0
3
0

3
0

Global Disable

High priority
interrupt

Interrupt
polling
sequence, decreasing
from high to low priority

Low priority
interrupt

Figure 9. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 11.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 12.) and in the Interrupt Priority High register (See Table 13.).
shows the bit values and priority levels associated with each combination.

24 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 10. Priority Level Bit Values

IPH.x IP.x Interrupt Level Priority

0 0 0 (Lowest)
0 1 1
1 0 2
1 1 3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.

Table 11. IE Register

IE - Interrupt Enable Register (A8h)

7 6 5 4 3 2 1 0

EA - ET2 ES ET1 EX1 ET0 EX0

Bit

Number

7 EA

6 -

5 ET2

4 ES

3 ET1

2 EX1

1 ET0

Bit

Mnemonic

Description

Enable All interrupt bit

Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt

enable bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.

Serial port Enable bit

Clear to disable serial port interrupt.
Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.

External interrupt 1 Enable bit

Clear to disable external interrupt 1.
Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.

0 EX0

External interrupt 0 Enable bit

Clear to disable external interrupt 0.
Set to enable external interrupt 0.

Reset Value = 0X00 0000b
Bit addressable

Rev. B - Jan. 25, 1999 25

Preliminary

TS80C52X2

Table 12. IP Register

IP - Interrupt Priority Register (B8h)

7 6 5 4 3 2 1 0

- - PT2 PS PT1 PX1 PT0 PX0

Bit

Number

7 -

6 -

5 PT2

4 PS

3 PT1

2 PX1

1 PT0

0 PX0

Bit

Mnemonic

Reserved

Reserved

Timer 2 overflow interrupt Priority bit

Serial port Priority bit

Timer 1 overflow interrupt Priority bit

External interrupt 1 Priority bit

Timer 0 overflow interrupt Priority bit

External interrupt 0 Priority bit

Reset Value = XX00 0000b
Bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

Refer to PT2H for priority level.

Refer to PSH for priority level.

Refer to PT1H for priority level.

Refer to PX1H for priority level.

Refer to PT0H for priority level.

Refer to PX0H for priority level.

26 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 13. IPH Register

IPH - Interrupt Priority High Register (B7h)

7 6 5 4 3 2 1 0

- - PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number

7 -

6 -

5 PT2H

4 PSH

3 PT1H

2 PX1H

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority High bit

PT2H PT2 Priority Level
0 0 Lowest
01
10
1 1 Highest

Serial port Priority High bit

PSH PS Priority Level
0 0 Lowest
01
10
1 1 Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level
0 0 Lowest
01
10
1 1 Highest

External interrupt 1 Priority High bit

PX1H PX1 Priority Level
0 0 Lowest
01
10
1 1 Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level

1 PT0H

0 PX0H

0 0 Lowest
01
10
1 1 Highest

External interrupt 0 Priority High bit

PX0H PX0 Priority Level
0 0 Lowest
01
10
1 1 Highest

Reset Value = XX00 0000b
Not bit addressable

Rev. B - Jan. 25, 1999 27

Preliminary

TS80C52X2

6.6 Idle mode

An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during normal operation or
during and Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.

The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the
hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.

6.7 Power-Down Mode

To save maximum power, a power-down mode can be invoked by software (Refer to Table 9., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last

instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCCcan be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.

CC

Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 10.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C52X2 into power-down mode.

INT0

INT1

XTAL1

Power-down phase Oscillator restart phase Active phaseActive phase

Figure 10. Power-Down Exit Waveform

Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.

Exit from power-down by either reset or external interrupt does not affect the internal RAM content.

NOTE:If idle mode is activated with power-downmode (IDL and PD bits set), the exit sequenceisunchanged,when execution is vectoredto interrupt,
PD and IDL bits are cleared and idle mode is not entered.

28 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

Table 14. The state of ports during idle and power-down modes

Mode

Idle Internal 1 1 Port Data* Port Data Port Data Port Data

Idle External 1 1 Floating Port Data Address Port Data
Power Down Internal 0 0 Port Data* Port Data Port Data Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data

* Port 0 can force a "zero" level. A "one" will leave port floating.

Program
Memory

ALE PSEN PORT0 PORT1 PORT2 PORT3

Rev. B - Jan. 25, 1999 29

Preliminary

TS80C52X2

6.8 ONCE Mode (ON Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using TS80C52X2 without removing the circuit from
the board. The ONCE mode is invoked by driving certain pins of the TS80C52X2; the following sequence must
be exercised:

● Pull ALE low while the device is in reset (RST high) and PSEN is high.

● Hold ALE low as RST is deactivated.

While the TS80C52X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 15. External Pin Status during ONCE Mode

ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2

Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active

30 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

6.9 Power-Off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCCswitch-on. A warm start reset occurs while VCCis still applied to

the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 16.). POF is set by hardware when VCCrises

from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.

Table 16. PCON Register

PCON - Power Control Register (87h)

7 6 5 4 3 2 1 0

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number

7 SMOD1

6 SMOD0

5 -

4 POF

3 GF1

2 GF0

1 PD

0 IDL

Bit

Mnemonic

Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.
Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.

Reset Value = 00X1 0000b
Not bit addressable

Rev. B - Jan. 25, 1999 31

Preliminary

TS80C52X2

6.10 Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.

Table 17. AUXR Register

AUXR - Auxiliary Register (8Eh)

7 6 5 4 3 2 1 0

- - - - - - EXTRAM AO

Bit

Number

7 -

6 -

5 -

4 -

3 -

2 -

1 EXTRAM

0 AO

Bit

Mnemonic

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

EXTRAM bit

ALE Output bit

Reset Value = XXXX XX00b
Not bit addressable

Description

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

The value read from this bit is indeterminate. Do not set this bit.

See Table 7.

Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.

32 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

7. TS80C52X2

7.1 ROM Structure

The TS80C52X2 devices are divided in three different arrays:

● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Kbytes.

● the encryption array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.

● the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 bytes.

7.2 ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

7.2.1 Encryption Array

Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.

7.2.2 Program Lock Bits

The lock bits when programmed according to Table 18. will provide different level of protection for the on-chip
code and data.

Table 18. Program Lock bits

Program Lock Bits

Security

level

1 U U U

2 P U U

U: unprogrammed
P: programmed

LB1 LB2 LB3

No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVCinstruction executed from external program memory returns
non encrypted data.

MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset.

Protection description

7.2.3 Signature bytes

The TS80C52X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 9.

Rev. B - Jan. 25, 1999 33

Preliminary

TS80C52X2

8. TS87C52X2

8.1 EPROM Structure

The TS87C52X2 is divided in two different arrays:

● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Kbytes.

● the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.

In addition a third non programmable array is implemented:

● the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.

8.2 EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

8.2.1 Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.

8.2.2 Program Lock Bits

The three lock bits, when programmed according to Table 19., will provide different level of protection for the
on-chip code and data.

Table 19. Program Lock bits

Program Lock Bits

Security

level

1 U U U

2 P U U

3 U P U Same as 2, also verify is disabled.
4 U U P Same as 3, also external execution is disabled.

U: unprogrammed,
P: programmed

WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.

LB1 LB2 LB3

Noprogramlockfeatures enabled. Code verify will still be encrypted by theencryption
array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.

MOVCinstruction executedfrom external program memory aredisabledfrom fetching
code bytes from internal memory,
programming of the EPROM is disabled.

Protection description

EA is sampled and latched on reset, and further

34 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

8.2.3 Signature bytes

The TS80/87C52X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process
described in section 9.

8.3 EPROM Programming

8.3.1 Set-up modes

In order to program and verify the EPROM or to read the signature bytes, the TS87C52X2 is placed in specific
set-up modes (See Figure 11.).

Control and program signals must be held at the levels indicated in Table 33.

8.3.2 Definition of terms

Address Lines:P1.0-P1.7, P2.0-P2.4, P3.4, P3.5 respectively for A0-A12
Data Lines:P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals:ALE/PROG, EA/VPP.

Table 20. EPROM Set-Up Modes

Mode RST PSEN

Program Code data 1 0 12.75V 0 1 1 1 1

Verify Code data 1 0 1 1 0 0 1 1

Program Encryption Array
Address 0-3Fh

Read Signature Bytes 1 0 1 1 0 0 0 0

Program Lock bit 1 1 0 12.75V 1 1 1 1 1

Program Lock bit 2 1 0 12.75V 1 1 1 0 0

Program Lock bit 3 1 0 12.75V 1 0 1 1 0

1 0 12.75V 0 1 1 0 1

ALE/

PROG

EA/

VPP

P2.6 P2.7 P3.3 P3.6 P3.7

Rev. B - Jan. 25, 1999 35

Preliminary

TS80C52X2

PROGRAM
SIGNALS*

EA/VPP
ALE/

PROG

+5V

VCC

D0-D7

A0-A7

A8-A12

CONTROL
SIGNALS*

* See Table 31. for proper value on these inputs

RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7

XTAL14 to 6 MHz

P0.0-P0.7

P1.0-P1.7

P2.0-P2.4

VSS

GND

Figure 11. Set-Up Modes Configuration

8.3.3 Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.

To program the TS87C52X2 the following sequence must be exercised:

● Step 1: Activate the combination of control signals.

● Step 2: Input the valid address on the address lines.

● Step 3: Input the appropriate data on the data lines.

● Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).

● Step 5: Pulse ALE/PROG once.

● Step 6: Lower EA/VPP from VPP to VCC

Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 12.).

8.3.4 Verify algorithm

Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C52X2.

P 2.7 is used to enable data output.
To verify the TS87C52X2 code the following sequence must be exercised:

● Step 1: Activate the combination of program and control signals.

● Step 2: Input the valid address on the address lines.

● Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See Figure 12.)

36 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.

A0-A12

D0-D7

ALE/PROG

EA/VPP

Control signals

Programming Cycle

Data In

100µs

12.75V
5V
0V

Figure 12. Programming and Verification Signal’s Waveform

Read/Verify Cycle

Data Out

8.4 EPROM Erasure (Windowed Packages Only)

Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.

Erasure leaves all the EPROM cells in a 1’s state (FF).

8.4.1 Erasure Characteristics

The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2rating for 30 minutes, at a distance
of about 25 mm, should be sufficient.

Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.

Rev. B - Jan. 25, 1999 37

Preliminary

TS80C52X2

9. Signature Bytes

The TS80/87C52X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the
procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table

33. shows the content of the signature byte for the TS80/87C52X2.

Table 21. Signature Bytes Content

Location Contents Comment

30h 58h Manufacturer Code: TEMIC
31h 57h Family Code: C51 X2
60h 2Dh Product name: TS80C52X2
60h ADh Product name: TS87C52X2
60h 20h Product name: TS80C32X2
61h FFh Product revision number

38 Rev. B - Jan. 25, 1999

Preliminary

10. Electrical Characteristics

TS80C52X2

10.1 Absolute Maximum Ratings

Ambiant Temperature Under Bias:
C = commercial 0°Cto70°C
I = industrial -40°Cto85°C
Storage Temperature -65°Cto+150°C
Voltage on VCCto V
Voltage on VPPto V
Voltage on Any Pin to V
Power Dissipation 1 W

NOTES

Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

1.
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.

2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

SS

SS

SS

(1)

-0.5Vto+7V

-0.5Vto+13V

-0.5VtoVCC+ 0.5 V

(2)

Rev. B - Jan. 25, 1999 39

Preliminary

TS80C52X2

10.2 DC Parameters for Standard Voltage

TA =0°Cto+70°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.
TA = -40°Cto+85°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.

Table 22. DC Parameters in Standard Voltage

Symbol Parameter Min Typ Max Unit Test Conditions

V

V

V

V

V

V

Input Low Voltage -0.5 0.2 VCC - 0.1 V

IL

Input High Voltage except XTAL1, RST 0.2 VCC+ 0.9 VCC + 0.5 V

IH

Input High Voltage, XTAL1, RST 0.7 V

IH1

OL

Output Low Voltage, ports 1, 2, 3

OL1

Output Low Voltage, port 0, ALE, PSEN

Output High Voltage, ports 1, 2, 3 VCC - 0.3

OH

(6)

(6)

CC

VCC - 0.7
VCC - 1.5

VCC + 0.5 V

0.3

0.45

1.0

0.3

0.45

1.0

V
V
V

V
V
V

V
V
V

IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA

IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA

IOH = -10 µA
IOH = -30 µA
I

= -60 µA

OH

(4)
(4)
(4)

(4)
(4)
(4)

VCC = 5 V ± 10%

V

Output High Voltage, port 0, ALE, PSEN VCC - 0.3

OH1

VCC - 0.7
VCC - 1.5

V
V
V

IOH = -200 µA
I

= -3.2 mA

OH

IOH = -7.0 mA
VCC = 5 V ± 10%

R

RST Pulldown Resistor 50

RST

(5)

90

200 kΩ

I

I

I

C

I

I

Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V

IL

Input Leakage Current ±10 µA 0.45 V < Vin < V

LI

Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V

TL

Capacitance of I/O Buffer 10 pF Fc = 1 MHz

IO

Power Down Current

PD

CC

Power Supply Current
Freq = 1 MHz

(7)

Icc op
Icc idle

(5)

10

50 µA

1.8
1

mA
mA

A = 25°C

T

2.0 V < V

CC <

VCC = 5.5 V

5.5 V

(1)

CC

(3)

Freq = 6 MHz

Icc op
Icc idle

(5)

10

4

mA
mA

VCC = 5.5 V

(2)

Freq ≥ 12 MHz
Icc op = 1.25 Freq (MHz) + 5 mA

Icc idle = 0.36 Freq (MHz) + 2.7 mA

13@12 MHz

16@16MHz

5.5@12Mz

7@16 MHz

mA

mA

40 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

10.3 DC Parameters for Low Voltage

TA =0°Cto+70°C; VSS=0V;VCC= 2.7 V to 5.5 V ± 10%;F=0to30MHz.
TA = -40°Cto+85°C; VSS=0V;VCC= 2.7 V to 5.5 V ± 10%;F=0to30MHz.

Table 23. DC Parameters for Low Voltage

Symbol Parameter Min Typ Max Unit Test Conditions

V

V

V

V

V

V

V

OH1

I

I

I

R

RST

Input Low Voltage -0.5 0.2 VCC - 0.1 V

IL

Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V

IH

Input High Voltage, XTAL1, RST 0.7 V

IH1

OL

Output Low Voltage, ports 1, 2, 3

OL1

Output Low Voltage, port 0, ALE, PSEN

Output High Voltage, ports 1, 2, 3 0.9 V

OH

(6)

(6)

Output High Voltage, port 0, ALE, PSEN 0.9 V

Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V

IL

Input Leakage Current ±10 µA 0.45 V < Vin < V

LI

Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V

TL

RST Pulldown Resistor 50

CC

CC

CC

90

(5)

VCC + 0.5 V

0.45 V

0.45 V

V IOH = -10 µA

V IOH = -40 µA

200 kΩ

IOL = 0.8 mA

IOL = 1.6 mA

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

I

I

CC

Power Down Current

PD

Power Supply Current

(7)

Active Mode 16MHz
Idle Mode 16MHz

TBD

TBD
TBD

(5)

(5)
(5)

TBD µA

TBD
TBD

mA
mA

VCC = 2.0 V to 5.5 V

VCC = 3.3 V
VCC = 3.3 V

(4)

(4)

CC

(3)

(1)
(2)

NOTES

1. Operating I

is measured with all output pins disconnected; XTAL1 driven with T

CC

CLCH

, T

= 5 ns (see Figure 16.), VIL = VSS + 0.5 V,

CHCL

VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..

2. Idle ICCis measured with all output pins disconnected; XTAL1 driven with T

CLCH,TCHCL

= 5 ns, VIL=VSS+ 0.5 V,VIH=VCC- 0.5 V; XTAL2

N.C; Port 0 = VCC; EA = RST = VSS (see Figure 14.).

3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 15.).

4. Capacitance loading on Ports0 and 2 may cause spurious noise pulses to be superimposed on the V

s of ALE and Ports 1 and 3. The noise is

OL

due to external bus capacitance discharging into the Port0 and Port2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V

peak 0.6V. A Schmitt Triggeruse is not necessary.

OL

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.

6. Under steady state (non-transient) conditions, I

must be externally limited as follows:

OL

Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA

Ports 1, 2 and 3: 15 mA
Maximum total I

for all output pins: 71 mA

OL

IfIOLexceedsthe test condition,VOLmayexceed the relatedspecification. Pinsare notguaranteedto sinkcurrentgreaterthan the listedtestconditions.

7. For other values, please contact your sales office.

Rev. B - Jan. 25, 1999 41

Preliminary

TS80C52X2

V

CC

I

CC

V

CC

V

CC

EA

RST

P0

V

CC

(NC)

CLOCK
SIGNAL

XTAL2
XTAL1

V

SS

Figure 13. ICCTest Condition, Active Mode

V

CC

I

CC

V

CC

V

CC

P0

RST

EA

(NC)

CLOCK
SIGNAL

XTAL2
XTAL1

V

SS

Figure 14. ICCTest Condition, Idle Mode

All other pins are disconnected.

All other pins are disconnected.

V

CC

I

CC

V

CC

V

CC

P0

RST

EA

(NC)

XTAL2
XTAL1

V

SS

All other pins are disconnected.

Figure 15. ICCTest Condition, Power-Down Mode

42 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

VCC-0.5V

0.45V

T

CHCL

T

CLCH

= T

CHCL

= 5ns.

T

CLCH

0.7V

CC

0.2VCC-0.1

Figure 16. Clock Signal Waveform for ICCTests in Active and Idle Modes

10.4 AC Parameters

10.4.1 Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.

Example:T
T

= Time for ALE Low to PSEN Low.

LLPL

TA =0to+70°C; VSS=0V;VCC=5V± 10%; -M and -V ranges.
TA = -40°Cto+85°C; VSS=0V; VCC=5V± 10%; -M and -V ranges.
TA =0to+70°C; VSS=0V;2.7V<V
TA = -40°Cto+85°C; VSS=0V;2.7V<V
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.)

Table 24., Table 27. and Table 30. give the description of each AC symbols.

= Time for Address Valid to ALE Low.

AVLL

CC <

5.5 V; -L range.

5.5 V; -L range.

CC <

Table 25., Table 28. and Table 31. give for each range the AC parameter.

Table 26., Table 29. and Table 32. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula.
Example:
T

in X2 mode for a -V part at 25 MHz:

LLIV

x= 22
T= 40ns
T

=2T-x=2x40-22=58ns

LLIV

Rev. B - Jan. 25, 1999 43

Preliminary

TS80C52X2

10.4.2 External Program Memory Characteristics

Table 24. Symbol Description

Symbol Parameter

T Oscillator clock period

T

T

T

T

T

T

T

T

T

T

T

T

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

PLAZ

ALE pulse width

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction FloatAfter PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

Table 25. AC Parameters for Fix Clock

Speed

(see ordering)

Symbol Min Max Min Max Min Max

-M -V -L Units

T 25 17 50 ns

T

T

T

T

T

T

T

T

T

T

T

T

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

PLAZ

40 25 60 ns

10 7 20 ns

10 7 20 ns

70 45 125 ns

10 7 20 ns

60 45 105 ns

25 25 60 ns

0 0 0 ns

18 12 30 ns

18 12 30 ns

85 53 145 ns

10 10 10 ns

44 Rev. B - Jan. 25, 1999

Preliminary

Table 26. AC Parameters for a Variable Clock

TS80C52X2

Symbol Type Standard

X2 Clock -M -V -L Units

Clock

T

T

T

T

T

T

T

T

T

T

T

T

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

PLAZ

Min 2 T - x T - x 10 8 40 ns

Min T - x 0.5 T - x 15 10 30 ns

Min T - x 0.5 T - x 15 10 30 ns

Max 4 T - x 2 T - x 30 22 75 ns

Min T - x 0.5 T - x 15 10 30 ns

Min 3 T - x 1.5 T - x 15 5 45 ns

Max 3 T - x 1.5 T - x 50 25 90 ns

Min x x 0 0 0 ns

Max T - x 0.5 T - x 7 5 20 ns

Min T - x 0.5 T - x 7 5 20 ns

Max 5 T - x 2.5 T - x 40 30 105 ns

Max x x 10 10 10 ns

10.4.3 External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

ADDRESS

OR SFR-P2

12 T

CLCL

T

LHLL

T

T

LLAX

AVLL

T

LLIV

T

LLPL

T

TPLAZ

PLIV

T

PLPH

T

PXIX

T

PXIZ

T

PXAV

A0-A7A0-A7 INSTR ININSTR IN INSTR IN

T

AVIV

Figure 17. External Program Memory Read Cycle

ADDRESS A8-A15ADDRESS A8-A15

Rev. B - Jan. 25, 1999 45

Preliminary

TS80C52X2

10.4.4 External Data Memory Characteristics

Table 27. Symbol Description

Symbol Parameter

T

RLRH

T

WLWH

T

RLDV

T

RHDX

T

RHDZ

T

LLDV

T

AVDV

T

LLWL

T

AVWL

T

QVWX

T

QVWH

T

WHQX

T

RLAZ

T

WHLH

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

46 Rev. B - Jan. 25, 1999

Preliminary

Table 28. AC Parameters for a Fix Clock

TS80C52X2

Speed

-M -V -L Units

(see ordering)

Symbol Min Max Min Max Min Max

T

T

WLWH

T

T

RHDX

T

T

T

AVDV

T

T

AVWL

T

QVWX

T

QVWH

T

WHQX

RLRH

RLDV

RHDZ

LLDV

LLWL

105 85 200 ns

105 90 200 ns

100 60 155 ns

0 0 0 ns

15 13 40 ns

160 100 310 ns

165 100 360 ns

40 110 30 65 90 60 ns

40 27 100 ns

3 0 18 ns

145 90 280 ns

10 7 20 ns

T

RLAZ

T

WHLH

0 0 0 ns

5 45 5 29 20 80 ns

Rev. B - Jan. 25, 1999 47

Preliminary

TS80C52X2

Table 29. AC Parameters for a Variable Clock

Symbol Type Standard

Clock

T

RLRH

T

WLWH

T

RLDV

T

RHDX

T

RHDZ

T

LLDV

T

AVDV

T

LLWL

T

LLWL

T

AVWL

T

QVWX

T

QVWH

T

WHQX

Min 6 T - x 3 T - x 45 15 100 ns

Min 6 T - x 3 T - x 45 10 100 ns

Max 5 T - x 2.5 T - x 25 23 95 ns

Min x x 0 0 0 ns

Max 2 T - x T - x 35 20 60 ns

Max 8 T - x 4T -x 40 33 90 ns

Max 9 T - x 4.5 T - x 60 50 90 ns

Min 3 T - x 1.5 T - x 35 20 60 ns

Max 3 T + x 1.5 T + x 35 15 60 ns

Min 4 T - x 2 T - x 60 40 100 ns

Min T - x 0.5 T - x 22 17 32 ns

Min 7 T - x 3.5 T - x 30 27 70 ns

Min T - x 0.5 T - x 15 10 30 ns

X2 Clock -M -V -L Units

T

T

WHLH

T

WHLH

RLAZ

Max x x 0 0 0 ns

Min T - x 0.5 T - x 20 12 30 ns

Max T + x 0.5 T + x 20 12 30 ns

10.4.5 External Data Memory Write Cycle

ALE

PSEN

WR

PORT 0

PORT 2

ADDRESS

OR SFR-P2

Figure 18. External Data Memory Write Cycle

A0-A7 DATA OUT

T

LLAX

T

AVWL

T

LLWL

T

WLWH

T

QVWX

T

QVWH

ADDRESS A8-A15 OR SFR P2

T

WHLH

T

WHQX

48 Rev. B - Jan. 25, 1999

Preliminary

10.4.6 External Data Memory Read Cycle

ALE

T

LLDV

TS80C52X2

T

WHLH

PSEN

RD

T

LLAX

PORT 0

PORT 2

ADDRESS

OR SFR-P2

A0-A7 DATA IN

T

AVWL

Figure 19. External Data Memory Read Cycle

10.4.7 Serial Port Timing - Shift Register Mode

Table 30. Symbol Description

Symbol Parameter

T

XLXL

T

QVHX

T

XHQX

T

XHDX

T

XHDV

T

LLWL

T

AVDV

T

RLAZ

ADDRESS A8-A15 OR SFR P2

Serial port clock cycle time
Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

T

RLRH

T

RHDX

T

RHDZ

Table 31. AC Parameters for a Fix Clock

Speed

(see ordering)

Symbol Min Max Min Max Min Max

T

XLXL

T

QVHX

T

XHQX

T

XHDX

T

XHDV

-M -V -L

300 200 600 ns

200 117 367 ns

20 13 50 ns

0 0 0 ns

200 117 367 ns

Units

Rev. B - Jan. 25, 1999 49

Preliminary

TS80C52X2

Table 32. AC Parameters for a Variable Clock

Symbol Type Standard

X2 Clock -M -V -L

Clock

T

T

QVHX

T

XHQX

T

XHDX

T

XHDV

XLXL

Min 12 T 6 T ns

Min 10 T - x 5 T - x 50 50 133 ns

Min 2 T - x T - x 30 20 50 ns

Min x x 0 0 0 ns

Max 10 T - x 5 T- x 50 50 133 ns

10.4.8 Shift Register Timing Waveforms

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE to SBUF
INPUT DATA

CLEAR RI

0123456 87

T

XLXL

T

QVXH

01234567

T

XHDV

T

XHQX

VALIDVALID

T

XHDX

Units

SET TI

VALIDVALID

VALID VALID VALID VALID

SET RI

Figure 20. Shift Register Timing Waveforms

50 Rev. B - Jan. 25, 1999

Preliminary

10.4.9 EPROM Programming and Verification Characteristics

TA =21°Cto27°C; VSS= 0V; VCC=5V± 10%.

Table 33. EPROM Programming Parameters

TS80C52X2

Symbol

V

PP

I

PP

1/T

CLCL

T

AVGL

T

GHAX

T

DVGL

T

GHDX

T

EHSH

T

SHGL

T

GHSL

T

GLGH

T

AVQV

T

ELQV

T

EHQZ

Parameter Min Max Units

Programming Supply Voltage 12.5 13 V

Programming Supply Current 75 mA

Oscillator Frquency 4 6 MHz

Address Setup to PROG Low 48 T

Adress Hold after PROG 48 T

Data Setup to PROG Low 48 T

Data Hold after PROG 48 T

(Enable) High to V

PP

VPP Setup to PROG Low 10 ms

V

Hold after PROG 10 ms

PP

PROG Width 90 110 ms

Address to Valid Data 48 T

ENABLE Low to Data Valid 48 T

Data Float after ENABLE

CLCL

CLCL

CLCL

CLCL

48 T

CLCL

0 48 T

CLCL

CLCL

CLCL

10.4.10 EPROM Programming and Verification Waveforms

PROGRAMMING

P1.0-P1.7
P2.0-P2.4

P0

T

DVGL

T

AVGL

ADDRESS

DATA IN

T

GHDX

T

GHAX

ALE/PROG

T

GHSL

V

CC

T

ELQV

EA/V

CC

CONTROL

T

SHGL

T

GLGH

V

V

CC

T

EHSH

PP

SIGNALS

(ENABLE)

Figure 21. EPROM Programming and Verification Waveforms

Rev. B - Jan. 25, 1999 51

VERIFICATION

ADDRESS

T

AVQV

DATA OUT

T

EHQZ

Preliminary

TS80C52X2

10.4.11 External Clock Drive Characteristics (XTAL1)

Table 34. AC Parameters

Symbol Parameter Min Max Units

T

CLCL

T

CHCX

T

CLCX

T

CLCH

T

CHCL

T

CHCX/TCLCX

Oscillator Period 25 ns

High Time 5 ns

Low Time 5 ns

Rise Time 5 ns

Fall Time 5 ns

Cyclic ratio in X2 mode 40 60 %

10.4.12 External Clock Drive Waveforms

VCC-0.5 V

0.45 V

0.7V

CC

0.2VCC-0.1 V
T

CHCL

Figure 22. External Clock Drive Waveforms

T

CLCX

T

CLCL

T

CLCH

T

CHCX

10.4.13 AC Testing Input/Output Waveforms

VCC-0.5 V

INPUT/OUTPUT

0.45 V

Figure 23. AC Testing Input/Output Waveforms

AC inputs during testing are driven at VCC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIHmin for a logic “1” and VILmax for a logic “0”.

0.2VCC+0.9

0.2VCC-0.1

10.4.14 Float Waveforms

FLOAT

VOH-0.1 V

VOL+0.1 V

V

LOAD

V

V

LOAD

LOAD

Figure 24. Float Waveforms

+0.1 V

-0.1 V

52 Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOLlevel occurs. IOL/IOH≥±20mA.

10.4.15 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.

INTERNAL

CLOCK

XTAL2

ALE

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

P2 (EXT)

READ CYCLE

RD

P0

P2

WRITE CYCLE

WR

P0

STATE4 STATE5
P1 P2 P1 P2

DAT A

SAMPLED

FLOAT FLOAT

PCL OUT

INDICATES ADDRESS TRANSITIONS

DPL OR Rt OUT

DPL OR Rt OUT

STATE6

P1 P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

STATE1 STATE2 STATE3 STATE4

P1 P2 P1 P2 P1 P2

THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION

DAT A

SAMPLED

PCL OUT

SAMPLED

FLOAT

FLOAT

STATE5

P1 P2 P1 P2

DAT A

PCLOUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)

PCL OUT

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P2

PORT OPERATION

MOV DEST P0

MOV DEST PORT (P1, P2, P3)

(INCLUDES INT0, INT1, TO, T1)

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

DATA OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

OLD DATA

P0 PINS SAMPLED

P1, P2, P3 PINS SAMPLED

RXD SAMPLED RXD SAMPLED

NEW DATA

P1, P2, P3 PINS SAMPLED

PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)

P0 PINS SAMPLED

Figure 25. Clock Waveforms

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.

Rev. B - Jan. 25, 1999 53

Preliminary

TS80C52X2

11. Ordering Information

TS

87C52X2

Part Number
80C32X2: Romless
80C52X2: 8K ROM
87C52X2: 8K OTP

TEMIC Semiconductors

-M

-M: VCC: 5V +/- 10%
40 MHz, standard mode
20 MHz, X2 mode

-V: VCC: 5V +/- 10%
40 MHz, standard mode
30 MHz, X2 mode

-L: VCC: 2.7 to 5.5 V
30 MHz, standard mode
20 MHz, X2 mode

C

Packages:
A: PDIL 40
B: PLCC 44
C: PQFP F1 (13.9 mm footprint)
E: VQFP 44 (1.4mm)

EPROM-UV Erasable (*)
J: Window CDIL 40*
K: Window CQPJ 44*

Temperature Range
C: Commercial 0 to 70oC
I: Industrial -40 to 85oC

B

R

Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and

Dry Pack

(*) Check with TEMIC Sales Office for availability

Table 35. Maximum Clock Frequency

Code

Standard Mode, oscillator frequency
Standard Mode, internal frequency

X2 Mode, oscillator frequency
X2 Mode, internal equivalent frequency

-M -V -L Unit

40
40

20
40

40
40

30

60

30
30

20

40

MHz

MHz

54 Rev. B - Jan. 25, 1999

Preliminary

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