
Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Repeaters
Mobile Infrastructure
CDMA / WCDMA / LTE
General Purpose Wireless
400-4000 MHz
+27.5 dBm P1dB
+44 dBm Output IP3
17.8 dB Gain at 2140 MHz
+5 V Single Supply, 135 mA Current
Internal RF overdrive protection
Internal DC overvoltage protection
On chip ESD protection
SOT-89 Package
The TQP7M9102 is a high linearity driver amplifier in a
low-cost, RoHS compliant, surface mount package. This
InGaP/GaAs HBT delivers high performance across a
broad range of frequencies with +44 dBm OIP3 and +27.5
dBm P1dB while only consuming 135 mA quiescent
current. All devices are 100% RF and DC tested.
The TQP7M9102 incorporates on-chip features that
differentiate it from other products in the market. The
amplifier integrates an on-chip DC over-voltage and RF
over-drive protection. This protects the amplifier from
electrical DC voltage surges and high input RF input
power levels that may occur in a system. On-chip ESD
protection allows the amplifier to have a very robust Class
2 HBM ESD rating.
The TQP7M9102 is targeted for use as a driver amplifier
in wireless infrastructure where high linearity, medium
power, and high efficiency are required. The device an
excellent candidate for transceiver line cards in current
and next generation multi-carrier 3G / 4G base stations.
0.5 W High Linearity Amplifier
869−960 MHz Evaluation Board
2.11–2.17 GHz Evaluation Board
2.5–2.7 GHz Evaluation Board
Standard T/R size = 1000 pieces on a 7” reel
RF IN GND RF OUT / V
CC
1 2 3
Backside Paddle - GND
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Recommended Operating Conditions
Electrical specifications are measured at specified test
conditions. Specifications are not guaranteed over all
recommended operating conditions.
RF Input Power, CW, 50Ω, T=25°C
Operation of this device outside the parameter ranges
given above may cause permanent damage.
Electrical Specifications
Test conditions unless otherwise noted: VCC=+5V, Temp.=+25 °C, matched 2140 MHz reference circuit
Operational Frequency Range
Pout = +9 dBm/tone, ∆f = 1 MHz
Notes:
1. ACLR test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Probability
Performance Summary Table
Test conditions unless otherwise noted: VCC =+5V, Temp.= +25 °C, band specific matching networks
(1)
Notes:
1. Reference designs for the various frequencies are either included on this datasheet or may be obtained by contacting
sjcapplications.engineering@tqs.com.
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Device Characterization Data
Note: The gain for the unmatched device in a 50 ohm system is shown as the black trace labeled "Gain (S21)". In a circuit tuned for a particular
frequency, it is expected that actual gain will be higher, up to the maximum stable gain. The maximum stable gain is shown as the red trace
[Gmax]. The impedance Smith chart plots are shown from 0.01 to 4 GHz.
Test Conditions: VCC=+5 V, ICQ=135 mA (typ.), Temp.=+25 °C, unmatched 50 Ohm system, reference plane at device leads
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5 3 3.5 4
Gain and Maximum Stable Gain
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-1 -0.75-0.5-0.25 0 0.250.50.75 1
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
746 – 768 MHz Reference Design
1. See Evaluation Board PCB Information for material and stack up.
2. The recommended component values are dependent upon the frequency of operation.
3. All components are of 0603 size unless stated on the schematic.
4. Critical component placement locations:
Distance from U1 Pin Pad 1 (left edge) to R1 (right edge): 0 mils
Distance from U1 Pin Pad 1 (left edge) to C6 (right edge): 60 mils
Distance from U1 Pin Pad 1 (left edge) to C5 (right edge): 230 mils
Distance from U1 Pin Pad 3 (right edge) to L2 (left edge): 0 mils
Bill of Material 746 – 768 MHz Reference Design
½ W High Linearity Amplifier
CAP, 0603, +/-5%. 100V NPO/COG
CAP, 0603, +/-2%. 50V. NPO/COG
CAP, 0603, +/-0.1PF. 100V. NPO/COG
CAP, 0603, 10%, X5R , 10V
IND, 0603, +/-0.3. >5600MHZ
Cap., Chip, 10%, 10V, X5R
Typical Performance 746 – 768 MHz Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
Pout= +18 dBm/tone, f= 1 MHz
J4
J3
U1
L1
C2
C3
C4
C1
R1
C5
L2
C6
U1
TQP7M9102
J4 GND
J3 Vcc
1
2,4
3
J1
RF
Input
J2
RF
Output
L1
0805
33 nH
C1
100 pF
C4
1.0 uF
C3
100 pF
R1
0402
3.0
C6
4.7 pF
C2
100 pF
L2
4.7 nH
C5
12 pF
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots 746 – 768 MHz Reference Design
18
19
20
21
22
745 750 755 760 765 770
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-15
-10
-5
0
745 750 755 760 765 770
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-15
-10
-5
0
745 750 755 760 765 770
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
30
35
40
45
50
15 16 17 18 19 20 21
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
869 – 894 MHz Evaluation Board (TQP7M9102−PCB900)
Notes:
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. The recommended component values are dependent upon the frequency of operation.
4. All components are of 0603 size unless stated on the schematic.
5. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 90 mils (4.3 deg. at 920 MHz)
Distance from R1 (left edge) to C5 (right edge): 70 mils (3.3 deg. at 920 MHz)
Distance from U1 Pin 3 (right edge) to L2 (left edge): 120 mils (5.7 deg. at 920 MHz)
Distance from U1 Pin 3 (right edge) to C6 (left edge): 370 mils (17.6 deg. at 920 MHz)
Bill of Material TQP7M9102−PCB900
TQP7M9102 Amplifier, SOT-89 pkg.
Resistor, Chip, 0603, 5%, 1/16W
Inductor, 0603, +/-0.3 nH
Inductor, 0805, 5%, Coilcraft CS Series
Cap., Chip, 0603, +/-0.1pF. 200V.
Cap., Chip, 0603, +/-0.1pF. 200V.
Cap., Chip, 5%, 50V, NPO/COG
Cap., Chip, 10%, 10V, X5R
Typical Performance TQP7M9102−PCB900
Test conditions unless otherwise noted: VCC=+5V, ICQ=137 mA (typ.), Temp.=+25 °C
Pout= +19 dBm/tone, Δf=1 MHz
Notes:
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Probability
J4
J3
U1
L1
C2
C3
C4
C1
R1
C5
L2
C6
U1
TQP7M9102
J4 GND
J3 Vcc
1
2,4
3
J1
RF
Input
J2
RF
Output
L1
33 nH
0805
C1
100 pF
C4
1 uF
C3
100 pF
C2
100 pF
C5
8.2 pF
C6
3.3 pF
R1
1.8
L2
3.3 nH
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots TQP7M9102−PCB900
Test conditions unless otherwise noted: VCC=+5V, ICQ=137 mA (typ.), Temp.=+25 °C
19
20
21
22
23
24
860 880 900 920 940 960
Gain (dB)
Freq (MHz)
Gain vs. Frequency
-25
-20
-15
-10
-5
0
860 880 900 920 940 960
|S11| (dB)
Freq (MHz)
Input Return Loss vs. Frequency
-25
-20
-15
-10
-5
0
860 880 900 920 940 960
|S22| (dB)
Freq (MHz)
Output Return Loss vs. Frequency
-65
-60
-55
-50
-45
-40
-35
12 13 14 15 16 17 18 19 20
+85°C
+25°C
−40°C
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Freq.=920 MHz
36
38
40
42
44
46
11 13 15 17 19 21
+85°C
+25°C
−40°C
Freq.=920 MHz
1 MHz Tone Spacing
25
26
27
28
29
30
860 880 900 920 940 960
-65
-60
-55
-50
-45
-40
-35
12 13 14 15 16 17 18 19 20
960 MHz
920 MHz
869 MHz
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Temp.=+25°C
30
35
40
45
50
11 13 15 17 19 21
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 Vs. Pout/Tone
960 MHz
920 MHz
869 MHz
1 MHz Tone Spacing
Temp.=+25°C
19
21
23
25
27
29
-3 -1 1 3 5 7
Output Power vs. Input Power
−40°C
+25°C
+85°C
Freq.= 920 MHz
120
140
160
180
200
220
240
260
12 14 16 18 20 22 24 26 28
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
700 – 1000 MHz Evaluation Board (TQP7M9102−PCB900)
Notes:
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. The recommended component values are dependent upon the frequency of operation.
4. All components are of 0603 size unless stated on the schematic.
5. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 90 mils (4.3 deg. at 920 MHz)
Distance from R1 (left edge) to C5 (right edge): 70 mils (3.3 deg. at 920 MHz)
Distance from U1 Pin 3 (right edge) to L2 (left edge): 120 mils (5.7 deg. at 920 MHz)
Distance from U1 Pin 3 (right edge) to C6 (left edge): 370 mils (17.6 deg. at 920 MHz)
Bill of Material TQP7M9102−PCB900
TQP7M9102 Amplifier, SOT-89 pkg.
Resistor, Chip, 0603, 5%, 1/16W
Inductor, 0805, 5%, Coilcraft CS Series
Cap., Chip, 0603, ±0.1pF. 200V. NPO/COG
Cap., Chip, 0603, ±0.1pF. 200V. NPO/COG
Cap., Chip, 5%, 50V, NPO/COG
Cap., Chip, 10%, 10V, X5R
Typical Performance TQP7M9102−PCB900
Test conditions unless otherwise noted: VCC=+5V, ICQ=137 mA (typ.), Temp.=+25 °C
Pout= +19 dBm/tone, Δf=1 MHz
Notes:
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Probability
J4
J3
U1
L1
C2
C3
C4
C1
R1
C5
L2
C6
U1
TQP7M9102
J4 GND
J3 Vcc
1
2,4
3
J1
RF
Input
J2
RF
Output
L1
33 nH
0805
C1
100 pF
C4
1 uF
C3
100 pF
C2
100 pF
C5
8.2 pF
C6
3.3 pF
R1
1.8
L2
3.3 nH
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots TQP7M9102−PCB900
Test conditions unless otherwise noted: VCC=+5V, ICQ=137 mA (typ.), Temp.=+25 °C
19
20
21
22
23
24
860 880 900 920 940 960
Gain (dB)
Freq (MHz)
Gain vs. Frequency
-25
-20
-15
-10
-5
0
860 880 900 920 940 960
|S11| (dB)
Freq (MHz)
Input Return Loss vs. Frequency
-25
-20
-15
-10
-5
0
860 880 900 920 940 960
|S22| (dB)
Freq (MHz)
Output Return Loss vs. Frequency
-65
-60
-55
-50
-45
-40
-35
12 13 14 15 16 17 18 19 20
+85°C
+25°C
−40°C
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Freq.=920 MHz
36
38
40
42
44
46
11 13 15 17 19 21
+85°C
+25°C
−40°C
Freq.=920 MHz
1 MHz Tone Spacing
25
26
27
28
29
30
860 880 900 920 940 960
-65
-60
-55
-50
-45
-40
-35
12 13 14 15 16 17 18 19 20
960 MHz
920 MHz
869 MHz
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Temp.=+25°C
30
35
40
45
50
11 13 15 17 19 21
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 Vs. Pout/Tone
960 MHz
920 MHz
869 MHz
1 MHz Tone Spacing
Temp.=+25°C
19
21
23
25
27
29
-3 -1 1 3 5 7
Output Power vs. Input Power
−40°C
+25°C
+85°C
Freq.= 920 MHz
120
140
160
180
200
220
240
260
12 14 16 18 20 22 24 26 28
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
700 – 1000 MHz Reference Design
Notes:
1. The recommended component values are dependent upon the frequency of operation.
2. All components are of 0603 size unless stated on the schematic.
3. Entire Bias network values are critical of linearity performance.
4. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 10 mils (0.5 deg at 920 MHz)
Distance from R1 (left edge) to C7 (right edge): 10 mils (0.5 deg at 920 MHz)
Distance from C7 (left edge) to L2 (right edge): 10 mils (0.5 deg at 920 MHz)
Distance from L2 (left edge) to C6 (right edge): 20 mils (1.0 deg at 920 MHz)
Distance from U1 Pin 3 (right edge) to L3 (left edge): 290 mils (13.8 deg at 920 MHz)
Distance from L3 (right edge) to C8 (left edge): 20 mils (1.0 deg at 920 MHz)
Bill of Material 700 – 1000 MHz Reference Design
½ W High Linearity Amplifier
0805, 5%, cer core,0805 Coilcraft
0603, ± 0.3 nH, multilayer, Toko
0603, ± 0.3 nH, multilayer, Toko
0603, ± 0.1 pF, 200 V, NPO/COG, AVX U Series
0603, ± 0.1 pF, 200 V, NPO/COG, AVX U Series
J4 J3
U1
L2
C7
C8
L1
C2
C3
C4
C1
R1
C6
L3
C5
U1
TQP7M9102
J4 GND
J3 Vcc
1
2,4
3
C7
12.0 pF
J1
RF
Input
J2
RF
Output
L1
33 nH
0805
C5
1.0 uF
C3
100 pF
R1
1.2
C8
3.3 pF
C2
100 pF
C1
100 pF
C6
4.7 pF
L2
5.6 nH
L3
2.7 nH
C4
0.1 uF
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Typical Performance 700 – 1000 MHz Reference Design
Test conditions unless otherwise noted: V
CC
= +5 V, ICQ=135 mA , Temp = +25 °C, 50 Ω system
Pout= +16 dBm / tone, f= 1 MHz
Performance Plots 700 – 1000 MHz Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
19
20
21
22
23
24
700 750 800 850 900 950 1000
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
700 750 800 850 900 950 1000
Return Loss (dB)
Frequency (MHz)
Return Loss vs. Frequency
Input Return Loss
Output Return Loss
30
35
40
45
50
11 13 15 17 19 21
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
700 MHz
850 MHz
1000 MHz
25
26
27
28
29
30
700 750 800 850 900 950 1000
P1dB (dBm)
Frequency (MHz)
P1dB vs. Frequency
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
1800 – 2200 MHz 1 Watt Reference Design
Notes:
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. 0 Ω resistors (R2) may be replaced with copper trace in the target application layout.
4. The recommended component values are dependent upon the frequency of operation.
5. All components are of 0603 size unless stated on the schematic.
6. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 25 mils
Distance from U1 Pin 1 (left edge) to C1 (right edge): 145 mils
Distance from U1 Pin 1 (left edge) to C5 (right edge): 90 mils
Distance from U1 Pin 3 (right edge) to C6 (left edge): 145 mils
Bill of Material 1800 – 2200 MHz 1 Watt Reference Design
½ W High Linearity Amplifier
CAP, 0603, +/-1%. 200V NPO/COG
CAP, 0603, +/-0.1pF. 200V. NPO/COG
Ind, chip, 0603, +/-0.3nH >6000MHz
CAP, 0603, 10%, X5R , 10V
CAP, 0603, +/-0.1pF. 200V. NPO/COG
Typical Performance 1800 – 2200 MHz 1 Watt Reference Design
Test conditions unless otherwise noted: VCC =+5V, ICQ=137 mA (typ.), Temp= +25°C
Pout= +15 dBm/tone, f= 1 MHz
J4 J3
U1
C6
L1
C2
C3
L2
C5
C4
R1
C1
U1
TQP7M9102
J4 GND
J3 +5V
1
2,4
3
C5
1.5 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
(0805)
C2
22 pF
C1
1.5 pF
C4
1.0 uF
C6
1.8 pF
C3
22 pF
R1
2.7
L2
2.2 nH
TQP7M9102
½ W High Linearity Amplifier

TQP7M9102
Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots 1800 – 2200 MHz 1 Watt Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
10
12
14
16
18
20
1800 1900 2000 2100 2200
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-25
-20
-15
-10
-5
0
1800 1900 2000 2100 2200
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-20
-15
-10
-5
0
1800 1900 2000 2100 2200
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
25
30
35
40
45
9 10 11 12 13 14 15 16 17 18 19
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
2110 – 2170 MHz Evaluation Board (TQP7M9102−PCB2140)
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. The recommended component values are dependent upon the frequency of operation.
4. All components are of 0603 size unless stated on the schematic.
5. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to C5 (right edge): 35 mils (3.9 deg. at 2140 MHz)
Distance from U1 Pin 1 (left edge) to C1 (right edge): 90 mils (9.9 deg. at 2140 MHz)
Distance from U1 Pin 3 (right edge) to C6 (left edge): 210 mils (23.2 deg. at 2140 MHz)
Bill of Material TQP7M9102−PCB2140
TQP7M9102 Amplifier, SOT-89 pkg.
Cap., Chip, 0603, +/-1%. 200V NPO/COG
Inductor, 0805, Coilcraft CS Series
Cap., Chip, 0603, +/-0.1pF. 200V. NPO/COG
Cap., Chip, 0603, +/-0.1pF. 200V. NPO/COG
Cap., Chip, 5%, 50V, NPO/COG
Cap., Chip, 10%, 10V, X5R
Cap., Chip, 0603, +/-0.1pF. 200V. NPO/COG
Cap., Chip, 0603, +/-0.05pF, 50V
Typical Performance TQP7M9102−PCB2140
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp=+25 °C
Pout= +9 dBm/tone, Δf=1 MHz
Notes:
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Prob
J4
J3
U1
L1
C2
C3
C4
R1
C1
C5
C6
U1
TQP7M9102
J4 GND
J3 Vcc
1
2,4
3
C5
1.8 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
C2
3.3 pF
C1
1.5 pF
C4
1.0 uF
C3
22 pF
C6
0.8 pF
R1
22 pF
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots TQP7M9102−PCB2140
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
15
16
17
18
19
20
2110 2120 2130 2140 2150 2160 2170
Gain (dB)
Freq (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
2110 2120 2130 2140 2150 2160 2170
|S11| (dB)
Freq (MHz)
Input Return Loss vs. Frequency
-20
-15
-10
-5
0
2110 2120 2130 2140 2150 2160 2170
|S22| (dB)
Freq (MHz)
Output Return Loss vs. Frequency
-65
-60
-55
-50
-45
-40
-35
14 15 16 17 18 19 20
+85°C
+25°C
−40°C
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Freq.= 2140 MHz
38
40
42
44
46
7 9 11 13 15 17
+85°C
+25°C
−40°C
Freq.=2140 MHz
1 MHz Tone Spacing
25
26
27
28
29
30
2110 2120 2130 2140 2150 2160 2170
-65
-60
-55
-50
-45
-40
-35
14 15 16 17 18 19 20
2170 MHz
2140 MHz
2110 MHz
W-CDMA 3GPP Test Model 1+64 DPCH
PAR = 10.2 dB @ 0.01% Probability
3.84 MHz BW
Temp.=+25°C
30
35
40
45
50
7 9 11 13 15 17
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 Vs. Pout/Tone
2170 MHz
2140 MHz
2110 MHz
1 MHz Tone Spacing
Temp.=+25°C
19
21
23
25
27
29
2 4 6 8 10 12
Output Power vs. Input Power
Freq.=2140 MHz
−40°C
+25°C
+85°C
120
140
160
180
200
220
240
260
12 14 16 18 20 22 24 26 28
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
2300 – 2700 MHz Reference Design
Notes:
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. 0 Ω resistors (R2) may be replaced with copper trace in the target application layout.
4. The recommended component values are dependent upon the frequency of operation.
5. All components are of 0603 size unless stated on the schematic.
6. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 10 mils
Distance from U1 Pin 1 (left edge) to C1 (right edge): 80 mils
Distance from U1 Pin 1 (left edge) to C5 (right edge): 235 mils
Distance from U1 Pin 3 (right edge) to C6 (left edge): 165 mils
Bill of Material 2300 – 2700 Reference Design
½ W High Linearity Amplifier
CAP, 0603, ± 0.05 pF, 50V, ACCU-P
CAP, 0603, ± 0.05 pF, 50V, ACCU-P
CAP, 0603, 5%, 50V, NPO/COG
CAP, 0603, 10%, X5R , 10V
RES, 0603, 5%, 1/16W, Chip
J4 J3
U1
C6
L1
C2
C3
R2
C5
C4
R1
C1
U1
TQP7M9102
J4 GND
J3 +5V
1
2,4
3
C5
1.5 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
(0805)
C2
22 pF
C1
1.8 pF
C4
1.0 uF
C6
0.9 pF
C3
22 pF
R1
2.2
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Typical Performance 2300 – 2700 Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp=+25 °C
Pout= +9 dBm / Tone, Δf = 1 MHz
Performance Plots 2300 – 2700 Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
11
12
13
14
15
16
2300 2400 2500 2600 2700
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
2300 2400 2500 2600 2700
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-15
-10
-5
0
2300 2400 2500 2600 2700
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
35
40
45
50
9 11 13 15 17 19
OIP3 (dBm)
Pout / Tone (dBm)
OIP3 vs. Pout / Tone
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
2.5 – 2.7 GHz Evaluation Board (TQP7M9102−PCB2600)
Notes:
1. See Evaluation Board PCB Information for material and stack up.
2. Components shown on the silkscreen but not on the schematic are not used.
3. 0 Ω resistors (R2) may be replaced with copper trace in the target application layout.
4. The recommended component values are dependent upon the frequency of operation.
5. All components are of 0603 size unless stated on the schematic.
6. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to R1 (right edge): 13 mils
Distance from U1 Pin 1 (left edge) to C1 (right edge): 70 mils
Distance from U1 Pin 1 (left edge) to C5 (right edge): 148 mils
Distance from U1 Pin 3 (right edge) to C6 (left edge): 78 mils
Bill of Material TQP7M9102−PCB2600
½ W High Linearity Amplifier
CAP, 0603, ± 0.05 pF, 50V, ACCU-P
CAP, 0603, ± 0.05 pF, 50V, ACCU-P
CAP, 0603, 5%, 50V, NPO/COG
CAP, 0603, 10%, X5R , 10V
CAP, 0603, ± 0.05 pF, 50V, ACCU-P
RES, 0402, 1%, 1/16W. CHIP.
RES, 0603, 5%, 1/16W, Chip
Typical Performance TQP7M9102−PCB2600
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
Pout= +11 dBm/tone, Δf=1 MHz
Notes:
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Prob.
J4 J3
U1
C6
L1
C2
C3
R2
C5
C4
R1
C1
U1
TQP7M9102
J4 GND
J3 +5V
1
2,4
3
C5
1.5 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
(0805)
C2
22 pF
C1
1.8 pF
C4
1.0 uF
C6
0.6 pF
C3
22 pF
R1
1.0
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots TQP7M9102−PCB2600
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp.=+25 °C
10
11
12
13
14
15
16
17
2300 2400 2500 2600 2700 2800 2900
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
2300 2400 2500 2600 2700 2800 2900
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-20
-15
-10
-5
0
2300 2400 2500 2600 2700 2800 2900
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
25
26
27
28
29
30
2500 2550 2600 2650 2700
P1dB (dBm)
Frequency (MHz)
P1dB vs. Frequency
30
35
40
45
50
8 9 10 11 12 13 14 15
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
-65
-60
-55
-50
-45
-40
-35
11 12 13 14 15 16 17 18 19 20 21
ACLR (dBc)
Pout (dBm)
ACLR vs. Output Power
WCDMA Test Model 1+64 Channels,
PAR=10.3dB @ .01% probability,
3.84MHz BW, ±5MHz offset
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
3400 – 3600 MHz Reference Design
Notes:
7. See Evaluation Board PCB Information for material and stack up.
8. Components shown on the silkscreen but not on the schematic are not used.
9. 0 Ω resistors (R2) may be replaced with copper trace in the target application layout.
10. The recommended component values are dependent upon the frequency of operation.
11. All components are of 0603 size unless stated on the schematic.
12. Critical component placement locations:
Distance from U1 Pin 1 (left edge) to C1 (right edge): 87 mils
Distance from U1 Pin 1 (left edge) to C5 (right edge): 210 mils
Distance from U1 Pin 3 (right edge) to C6 (left edge): 105 mils
Bill of Material 3400 – 3600 MHz Reference Design
0.25 W High Linearity Amplifier
RES , 0603, 5PCT. 1/16W. CHIP
CAP, 0603, 5%, 50V, NPO/COG
CAP, 0603, 10%, X5R , 10V
Inductor, 0805, 5%, Coilcraft CS series
Typical Performance 3400 – 3600 MHz Reference Design
Test conditions unless otherwise noted: VCC=+5V, ICQ=137 mA (typ.), Temp.=+25°C
Pout= +11 dBm/tone, Δf=1 MHz
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Prob
J4 J3
U1
C6
L1
C2
C3
R2
C5
C4
C1
U1
TQP7M9102
J4 GND
J3 +5V
1
2,4
3
C5
0.8 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
(0805)
C2
22 pF
C1
0.7 pF
C4
1.0 uF
C6
0.7 pF
C3
22 pF
R2
0
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots 3400 – 3600 MHz Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp=+25°C
12
13
14
15
16
3400 3450 3500 3550 3600
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
3400 3450 3500 3550 3600
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-20
-15
-10
-5
0
3400 3450 3500 3550 3600
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
30
35
40
45
50
9 10 11 12 13 14 15 16 17 18 19
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
-60
-55
-50
-45
-40
-35
-30
11 12 13 14 15 16 17 18 19 20 21
ACLR (dBC)
Pout (dBm)
ACRL vs. Pout
WCDMA Test Model 1+64 Channels,
PAR=10.3dB @ .01% probability,
3.84MHz BW, ±5MHz offset
22
23
24
25
26
27
28
29
3400 3450 3500 3550 3600
P1dB (dBm)
Frequency (MHz)
P1dB vs. Frequency
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Application Note 1.8-2.2 GHz (1/2 Watt - 1 Watt) Tunable Reference Design
This applications note describes the ability to take the TQP7M9102 1.8-2.2 GHz design and tune it from 1/2 Watt to 1
Watt simply by changing the output match (one component). By use of Load-Pull data we were able to see the
capability of this part to be tuned from +27 dBm P1dB to +30 dBm by trading off OIP3 performance. This gives the
end user the option to run the TQP7M9102 as a 1 Watt device over a wide frequency band.
Below are the different Reference Design options which show the performance trade-offs between P1dB and OIP3 by
changing the value and placement of C6.
1. All components are of 0603 size unless stated on the schematic.
2. The recommended component values are dependent upon the frequency of operation.
3. Critical component placement locations:
Distance between U1 Pin 1 Pad to R1 (right edge): 10 mil
Distance between U1 Pin 1 Pad to C1 (right edge): 110 mil
Distance between U1 Pin 1 Pad to C5 (right edge): 65 mil
Distance between U1 Pin 3 Pad to C6 (left edge): see below:
Electrical Length at
2 GHz (degrees)
J4 J3
U1
C6
L1
C2
C3
L2
C5
C4
R1
C1
J1 J2
U1
TQP7M9102
J4 GND
J3 +5V
1
2,4
3
C5
1.5 pF
J1
RF
Input
J2
RF
Output
L1
18 nH
(0805)
C2
22 pF
C1
1.8 pF
C4
1.0 uF
C6
0.8 - 2.0 pF
C3
22 pF
R1
2.7
L2
2.2 nH
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Performance Plots 1.8-2.2 GHz (1/2 Watt - 1 Watt) Tunable Reference Design
Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 mA (typ.), Temp=+25°C
13
14
15
16
17
1800 1900 2000 2100 2200
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
-20
-15
-10
-5
0
1800 1900 2000 2100 2200
Input Return Loss (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
-20
-15
-10
-5
0
1800 1900 2000 2100 2200
Output Return Loss (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
35
40
45
50
55
9 10 11 12 13 14 15 16 17 18 19
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
35
40
45
50
55
9 10 11 12 13 14 15 16 17 18 19
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
35
40
45
50
55
9 10 11 12 13 14 15 16 17 18 19
OIP3 (dBm)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
25
26
27
28
29
30
31
1800 1900 2000 2100 2200
P1dB (dBm)
Frequency (MHz)
P1dB vs. Frequency
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Pin Configuration and Description
RF input. External DC Block required. Requires conjugate match for optimal
performance.
RF/DC ground. Use recommended via pattern to minimize inductance and
thermal resistance. See PCB Mounting Pattern for suggested footprint.
RF output, matched to 50 ohms. External DC Block and bias voltage required.
Evaluation Board PCB Information
PCB Material (stackup):
1 oz. Cu top layer
0.014 inch Nelco N-4000-13, εr=3.7
1 oz. Cu MIDDLE layer 1
Core Nelco N-4000-13
1 oz. Cu middle layer 2
0.014 inch Nelco N-4000-13
1 oz. Cu bottom layer
Finished board thickness is 0.062±.006
50 ohm line dimensions: width = .028”, spacing = .028”.
The pad pattern shown has been developed and tested for
optimized assembly at Triquint Semiconductor. The PCB
land pattern has been developed to accommodate lead
and package tolerances. Since surface mount processes
vary from supplier to supplier, careful process
development is recommended.
RF IN GND RF OUT / V
CC
1 2 3
Backside Paddle - GND
TQP7M9102
½ W High Linearity Amplifier

Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Package Marking and Dimensions
Package Marking
Product ID:
7M9102
Lot code:
YXXX
1. All dimensions are in millimeters. Angles are in degrees.
2. Dimension and tolerance formats conform to ASME Y14.4M-1994.
3. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
4. Contact plating: NiPdAu
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation.
4. Do not remove or minimize via hole structure in the PCB. Thermal and RF grounding is critical.
5. We recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
6. Ensure good package backside paddle solder attach for best electrical and thermal performance.
TQP7M9102
½ W High Linearity Amplifier

TQP7M9102
Datasheet: Rev. K 01-26-16
Disclaimer: Subject to change without notice
© 2016 TriQuint Semiconductor, Inc
www.triquint.com / www.qorvo.com
Product Compliance Information
ESD Sensitivity Ratings
Caution! ESD-Sensitive Device
ESD Rating: Class 2
Value: >2000V to <4000V
Test: Human Body Model (HBM)
Standard: ESAD/JEDEC Standard JS-001-2012
ESD Rating: Class C3
Value: ≥ 1000 V
Test: Charged Device Model (CDM)
Standard: JEDEC Standard JESD22-C101F
Solderability
Compatible with both lead-free (260°C maximum reflow
temperature) and tin/lead (245°C maximum reflow
temperature) soldering processes.
Contact plating: NiPdAu
RoHs Compliance
This part is compliant with EU 2002/95/EC RoHS
directive (Restrictions on the Use of Certain Hazardous
Substances in Electrical and Electronic Equipment).
This product also has the following attributes:
Lead Free
Halogen Free (Chlorine, Bromine)
Antimony Free
TBBP-A (C15H12Br402) Free
PFOS Free
SVHC Free
MSL Rating: Level 1
Test: 260°C convection reflow
Standard: JEDEC Standard IPC/JEDEC J-STD-020
The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information
contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein.
TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information
contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information
is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain
and verify the latest relevant information before placing orders for TriQuint products. The information contained herein
or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other
intellectual property rights, whether with regard to such information itself or anything described by such information.
TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining
applications, or other applications where a failure would reasonably be expected to cause severe personal injury or
death.
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.triquint.com Tel: 877-800-8584
Email: customer.support@qorvo.com
For information about the merger of RFMD and TriQuint as Qorvo:
Web: www.qorvo.com
For technical questions and application information:
Email: sjcapplications.engineering@qorvo.com
½ W High Linearity Amplifier