Page 1
T R I Q U I N T S E M I C O N D U C T O R , I N C .
1
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SWITCHING
PRODUCTS
Min Max Units
Data Rate/Port 1.25 Gb/s
Jitter 150 ps peak-peak
Channel Propagation Delay 2000 ps
Ch-to-Ch Propagation Delay Skew 500 ps
The TQ8015 is a non-blocking 16 x 16 digital crosspoint switch capable of
data rates greater than 1.25 Gigabits per second per port. Utilizing a fully
differential internal data path and ECL I/O, the TQ8015 offers a high data
rate with exceptional signal fidelity. The symmetrical switching and noise
rejection characteristics inherent in differential logic result in low jitter and
signal skew. The TQ8015 is ideally suited for digital video, data
communications and telecommunication switching applications.
The non-blocking architecture uses 16 fully independent 16:1 multiplexers
(see diagram on page 2), allowing each output port to be independently
programmed to any input port. The switch is configured by sequentially
loading each multiplexer’s 4-bit program latch (OA0:3) with the desired
input port address (IA0:3) and enabling the LOAD pin. When complete, the
CONFIGURE pin is strobed and all new configurations are simultaneously
transferred into the switch multiplexers. Data integrity is maintained on all
unchanged data paths.
Typical output waveform with all
channels driven
Features
• >20 Gb/s aggregate BW
• 1.25 Gb/s/port NRZ data rate
• Non-blocking architecture
• 500 ps delay match
• Differential ECL-level data
I/O; CMOS-level control inputs
• Low jitter and signal skew
• Fully differential data path
• Double buffered configuration
latches
• 132-pin MQFP package
Applications
Telecom/Datacom Switching
Hubs and Routers
Video Switching
TQ8015
1.25 Gigabit/sec
16x16 Digital ECL
Crosspoint Switch
Electrical Characteristics
Input
Buffers
Output
Buffers
16 x 16
Crosspoint
Switch
Matrix
64
64
(R2)
Sixteen 4-Bit Latches
(R1)
Sixteen 4-Bit Addressable
Output Select Latches
4
4
4:16
Decoder
VCC
VEE
GND
O0..15
O0..15
D0..15
D0..15
CONFIGURE
RESET
LOAD
IA0..3
OA0..3
TQ8015
Page 2
TQ8015
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2
Figure 1. TQ8015 architecture.
Notes: 1. For die applications.
2. T
C
is measured at case top.
3. All voltages specified with respect to GND, defined as 0V.
4. Subject to I
OUT
and power dissipation limitations.
5. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired
and/or permanent damage to the device may occur.
Symbol Parameter Absolute Max. Rating Notes
T
STOR
Storage Temperature –65° C to +150° C
T
CH
Junction (Channel) Temperature –65° C to +150° C1
T
C
Case Temperature Under Bias –65° C to +125° C2
VCCSupply Voltage 0 V to +7 V 3
V
EE
Supply Voltage –7 V to 0 V 3
V
TT
Load Termination Supply Voltage VEE to 0 V 4
V
IN
Voltage Applied to Any ECL Input; Continuous VEE –0.5 V to +0.5 V
I
IN
Current Into Any ECL Input; Continuous –1.0 mA to +1.0 mA
V
IN
Voltage Applied to Any CMOS Input; Continuous –0.5 V to VCC +0.5 V
I
IN
Current Into Any CMOS Input; Continuous –1.0 mA to +1.0 mA
V
OUT
Voltage Applied to Any ECL Output VEE –0.5 V to +0.5 V 4
I
OUT
Current From Any ECL Output; Continuous –40 mA
P
D
Power Dissipation per Output P
OUT
= (GND – V
OUT
) x I
OUT
50 mW
Table 1. Absolute Maximum Ratings
5
DATA
OUT 15
(O15)
5
RESET
OUTPUT
SELECT ADDRESS
(OA0:3)
Input
Buffers
DATA
OUT 0
(O0)
Configuration
Register
Program Register
CONFIGURE
LOAD
4
16 X 1-BIT
MULTIPLEXER
16 X 1-BIT
MULTIPLEXER
.
.
.
.
.
.
.
.
.
.
.
.
DATA IN 0
(I0)
DATA IN 15
(I15)
4
INPUT ADDRESS
(IA0:3)
4:16
DECODE
Page 3
TQ8015
SWITCHING
PRODUCTS
3
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Signal Name/Level Description
I0 to I15, Data input true and complement. Differential data input ports.
NI0 to NI15 Differential ECL
O0 to O15, Data output true and complement. Differential data output ports.
NO0 to NO15 Differential ECL
IA0:3 Input address, CMOS Input port selection address that is written into the selected output port
program latches (OA0:3).
IA3 IA2 IA1 IA0 Input port
0000 0
0001 1
0010 2
:::: :
1111 15
OA0:3 Output select address, CMOS Output port selection address. Selects the output port program latches to
which the input port selection address (IA0:3) is written.
OA3 OA2 OA1 OA0 Output port
0000 0
0001 1
0010 2
:::: :
1111 15
LOAD CMOS Enables the selected output port program latches while set ‘high’.
Latches the data when set to a 'low' level.
CONFIGURE CMOS Transfers the program latches data to the configuration latches and
implements the switch changes while set ‘high’. Latches the data when
set to a ‘low’ level.
RESET CMOS Sets the switch into broadcast or pass-through configuration, overwriting
existing configurations.
Broadcast mode:
All output ports are connected to data input port 0. This
mode is selected by applying a RESET “high” pulse with CONFIGURE held “low”.
Symbol Parameter Min Typ Max Units Notes
T
C
Case Operating Temperature 0 85 °C1
VCCSupply Voltage 4.5 5.5 V
V
EE
Supply Voltage –5.5 –4.5 V
V
TT
Load Termination Supply Voltage –2.0 V 2
R
LOAD
Output Termination Load Resistance 50 Ω 2
Θ
JC
Thermal Resistance Junction to Case 7 °C/W
Table 2. Recommended Operating Conditions
3
Notes: 1. TC measured at case top. Use of adequate heatsink is required.
2. The V
TT
and R
LOAD
combination is subject to maximum output current and power restrictions.
3. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed,
singularly or in combination, the operating range specified.
Table 3. Pin Descriptions
Page 4
TQ8015
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4
Symbol Parameter Min Max Units Test Cond. Notes
V
IH
ECL Input Voltage High –1100 –500 mV
V
IL
ECL Input Voltage Low V
TT
–1500 mV
I
IH
ECL Input Current High +30 µAV
IH
= –0.7 V
I
IL
ECL Input Current Low –30 µAV
IL
= –2.0 V
V
ICM
ECL Input Common Mode Voltage –1500 –1100 mV
V
IDIF
ECL Input Differential Voltage (pk-pk) 400 1200 mV
V
IH
CMOS Input Voltage High 3.5 V
CC
V
V
IL
CMOS Input Voltage Low 0 1.5 V
I
IH
CMOS Input Current High +100 µAV
IH
= V
CC
I
IL
CMOS Input Current Low –100 µAV
IL
= 0 V
V
OCM
ECL Output Common Mode –1500 –1100 mV
V
ODIF
ECL Output Differential Voltage 600 mV
V
OH
ECL Output Voltage High –1000 –600 mV
V
OL
ECL Output Voltage Low V
TT
–1600 mV
I
OH
ECL Output Current High 20 27 mA
I
OL
ECL Output Current Low 0 8 mA
I
CC
Power Supply Current (+) 20 mA
I
EE
Power Supply Current (–) –950 mA
Table 4. DC Characteristics1 – Within recommended operating conditions, unless otherwise indicated.
Notes: 1. Test conditions unless otherwise indicated: VTT = –2.0 V, R
LOAD
= 50 W to V
TT.
Notes: 1. Test conditions: V
TT
= –2.0 V, R
LOAD
= 50 W to VTT; ECL inputs: VIH = –1.1 V; VIL = –1.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V;
ECL outputs: V
OH
> –1.0 V, VOL < –1.6 V; ECL inputs rise and fall times < 1 ns; CMOS inputs rise and fall times < 20 ns. A bit error
rate of 1E–13 BER or better for 2
23
–1PRBS pattern, jitter and rise/fall times are guaranteed through characterization.
2. 1.2 Gb/s Non-Return-Zero (NRZ) data equivalent to 600 MHz clock signal.
3. Rise and fall times are measured at the 20% and 80% points of the transition from V
OL
max to VOL min.
Symbol Parameter Min Typ Max Units Notes
Maximum Data Rate/Port 1.25 Gb/s 1,2
Jitter 150 ps pk-pk 1
T
1
Channel Propagation Delay 2000 ps
T
2
Ch-to-Ch Propagation Delay Skew 500 ps
T
3
CONFIG to Data Out (Oi) Delay 5 ns
T
4
LOAD Pulse Width 7 ns
T
5
CONFIG Pulse Width 7 ns
T
6
IAi to LOAD High Setup Time 0 ns
T
7
LOAD to IAi Low Hold Time 3 ns
T
8
OAi to LOAD High Setup Time 0 ns
T
9
LOAD to OAi Low Hold Time 3 ns
T
10
Load ↑ to CONFIG ↑ 0ns
T
11
RESET Pulse Width 10 ns
T
R,F
Output Rise or Fall Time 250 400 ps 3
Table 5. AC Characteristics1 – Within recommended operating conditions, unless otherwise indicated.
Page 5
TQ8015
SWITCHING
PRODUCTS
5
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Figure 2. Switch Configuration Timing
Output
Address
Input
Address
LOAD
RESET
CONFIGURE
A
D
B
D
C
D
D
D
E
D
F
D
G
D
A
O
B
O
C
O
D
O
E
O
F
O
G
O
T8 T7
T5
T6
T1
T9
T3
Invalid
Data Out
T10
T4
Data
1
In
Data
1
Out
Notes: 1. No data loss on unchanged paths.
Figure 5. Reset Timing
Output
Data
RESET
CONFIGURE
T11
T3
Broadcast Pass-through
Notes: 1. LOAD input must remain LOW to insure correct programming of the switch.
2. “Broadcast” is defined as data input 0 to all data outputs (0…15).
3. “Pass-through” is defined as data input 0 to data output 0, data input 1 to data output 1, and so on.
Page 6
TQ8015
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6
Typical Performance Data
0.5 0.7 0.9 1.1 1.3 1.5 1.7
12
10
8
6
4
2
0
Data Rate (Gb/s)
Data Eye Period (%)
Figure 4. Data Eye Closure
Percent RMS vs. Data Rate (typical)
0.5 0.7 0.9 1.1 1.3 1.5 1.7
45
40
35
30
25
20
15
10
Data Rate (Gb/s)
Jitter (ps)
Figure 6. RMS Jitter vs. Data Rate (typical)
Figure 5. Data Eye Closure
Time & Amplitude vs Data Rate (typical)
0.5 0.7 0.9 1.1 1.3 1.5 1.7
100
90
80
70
60
50
40
30
20
10
0
Data Rate (Gb/s)
Percent (%)
➤
% Recoverable Data Eye
Period – (P-P Jitter) x 100 / Period
➤
Inner Eye Amplitude
V (inner eye) x 100 / V (inner eye @ 400 Mb/s)
0.3 0.5 0.7 0.9 1.1 1.3 1.5
Page 7
TQ8015
SWITCHING
PRODUCTS
7
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Figure 7. Package Pinout
GND
NO1
O1
GND
NO0
O0
GND
IADD3
IADD2
GND
IADD1
IADD0
VEE
VCC
GND
CONFIGURE
LOAD
GND
OADD3
OADD2
GND
OADD1
OADD0
GND
D0
ND0
GND
D1
ND1
515253545556575859606162636465666768697071727374757677787980818283
17161514131211
10
987654321
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
GND
O12
NO12
GND
O13
NO13
GND
O14
NO14
GND
O15
NO15
GND
RESET
VEE
ND15
D15
GND
ND14
D14
GND
ND13
D13
GND
ND12
D12
GND
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NO11
O11
GND
NO10
O10
GND
NO9
O9
GND
NO8
O8
GND
NO7
O7
VCC
VEE
GND
NO6
O6
GND
NO5
O5
GND
NO4
O4
GND
NO3
O3
GND
NO2
O2
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
ND11
D11
GND
ND10
D10
GND
ND9
D9
GND
ND8
D8
GND
ND7
D7
GND
VCC
VEE
ND6
D6
GND
ND5
D5
GND
ND4
D4
GND
ND3
D3
GND
ND2
D2
Top View
132-Pin Package
Pin 1 Index
➤
NOTE: All unmarked pins are not connected.
Note: Unmarked pins are not connected.
Page 8
TQ8015
For additional information and latest specifications, see our website: www.triquint.com
8
Figure 8. Mechanical Dimensions (in inches)
Top view
Ordering Information
TQ8015-Q
1.25 16x16 Gb/s ECL Crosspoint Switch
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com Tel: (503) 615-9000
Email: sales@tqs.com Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions.
TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the
user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of
the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any
TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A November 1997
A
A
XXXX
YYWW
LOT CODE
DATE CODE
PIN 1
INDEX
TQ8015-Q
Section A-A
0.170 ± .010
SEATING PLANE
0.020
MIN.
0.140 ± .005
1. Part is symmetrical about the center axes.
2. Centerline bisects center pin in both directions.
3. See pad detail below.
0.550
± .003
0.400
REF. SQ.
17 117
51 83
116
84
50
18
0.467
± .003
0.010
PIN WIDTH
TYP.
0.540
± .003
0.015
0.010
0.053
0.512
0.025 TYP.
C
L
C
L
C
L
C
L
PAD LAYOUT DETAIL
Notes:
XXXX
YYWW
TQ8015-Q
PIN 1
INDEX
Bottom view
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