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WIRELESS COMMUNICATIONS DIVISION
Control
Logic
C2
C2
L1
VDD
TQ3631
DATA SHEET
GND
RF
IN
LNA
gnd
GND
RF
OUT
C3
50 ohm
RF Out
Control
Logic
Product Description
The TQ3631 is a 3V, RF LNA IC designed specifically for PCS band CDMA
applications. It’s RF performance meets the requirements of products designed to
the IS-95 specifications. The TQ3631 is designed to be used with the TQ5631
(CDMA mixer) which provides a complete CDMA receiver for 1900MHz phones.
The LNA incorporates on-chip switches which determine high, low and bypass mode
select. When used with the TQ5631 (CDMA RFA/mixer), four gain steps are
available for use which provide low current/high IP3 and gain. The RF output port is
internally matched to 50
of external components. The TQ3631 achieves excellent RF performance with low
current consumption, supporting long standby and talk times in portable applications.
Coupled with the very small SOT23-8 package, the part is ideally suited for PCS
band mobile phones.
Ω
, greatly simplifying the design and minimizing the number
3V PCS Band CDMA
LNA IC
Features
Small size: SOT23-8
Single 3V operation
Low-current operation
Gain Select
High IP3 performance
Few external components
Applications
IS-95 CDMA PCS Mobile Phones
Electrical Specifications
Parameter Min Typ Max Units
Frequency 1960 MHz
Gain 13.0 dB
Noise Figure 1.5 dB
Input 3rd Order Intercept 10.0 dBm
DC supply Current 11.0 mA
Note 1: Test Conditions: Vdd=2.8 V, RF=1960MHz, Tc=25C, CDMA High Gain state.
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TQ3631
Data Sheet
Electrical Characteristics
Parameter Conditions Min. Typ/Nom Max. Units
RF Frequency PCS band 1810 1960 1990 MHz
CDMA Mode-High Gain
Gain 12.0 13.0 dB
Noise Figure 1.5 2.2 dB
Input IP3 7.0 10.0 dBm
Input Return Loss (with external matching) 10 dB
Output Return Loss 10 dB
Supply Current 11.0 13.0 mA
CDMA Mode-High Gain-Low Linearity
Gain 10.0 11.5 dB
Noise Figure 1.6 2.8 dB
Input IP3 2.0 5.0 dBm
Input Return Loss (with external matching) 10 dB
Output Return Loss 10 dB
Supply Current 4.5 5.5 mA
Bypass Mode
Gain -2.5 -1.5 dB
Noise Figure 2.0 2.8 dB
Input IP3 30.0 dBm
Input Return Loss (with external matching) 10 dB
Output Return Loss 10 dB
Supply Current 1.0 2.0 mA
Supply Voltage 2.7 2.8 3.3 V
Note 1: Test Conditi ons: Vdd=2.8 V, RF=1960MHz, TC = 25° C, unless otherwise specified.
°
Note 2: Min/Max limits are at +25
C case temperature, unless otherwise specified.
Absolute Maximum Ratings
Parameter Value Units
DC Power Supply 5.0 V
Power Dissipation 500 mW
Operating Temperature -40 to 85 C
Storage Temperature -60 to 150 C
Signal level on inputs/outputs +20 dBm
Voltage to any non supply pin +0.3 V
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Typical Performance
Test Conditions, unless Otherwise Spec ified: Vdd=2.8V, Tc=25C, RF=1960MHz
TQ3631
Data Sheet
CDMA High Gain Mode
Gain v Freq v Temp
15.0
14.5
14.0
13.5
13.0
12.5
Gain (dB)
12.0
11.5
11.0
10.5
-30C
+25C
+85C
10.0
1920 1940 1960 1980 2000
Frequency (MHz)
CDMA High Gain Mode
IIP3 v Freq v Temp
10.0
9.5
9.0
8.5
IIP3 (dBm)
8.0
7.5
-30C
+25C
+85C
7.0
1920 1940 1960 1980 2000
Frequency (MHz)
CDMA High Gain Mode
Idd v Vdd v Temp
13.00
12.00
11.00
10.00
9.00
Idd (mA)
8.00
7.00
6.00
2.5 2.7 2.9 3.1 3.3
Vdd (V)
High Gain/Low Linearity Mode
Gain v Freq v Temp
13.0
12.5
12.0
11.5
11.0
10.5
Gain (dB)
10.0
9.5
9.0
8.5
8.0
1920 1940 1960 1980 2000
Frequency (MHz)
-30C
+25C
+85C
-30C
+25C
+85C
CDMA High Gain Mode
Noise Figure v Freq v Temp
2.00
1.80
1.60
1.40
1.20
1.00
0.80
Noise Figure (dB)
0.60
0.40
0.20
-30C
+25C
+85C
0.00
1920 1940 1960 1980 2000
Frequency (MHz)
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High Gain/Low Linearity Mode
IIP3 v Freq v Temp
5.0
4.8
4.6
4.4
4.2
4.0
3.8
IIP3 (dBm)
3.6
3.4
3.2
-30C
+25C
+85C
3.0
1920 1940 1960 1980 2000
Frequency (MHz)
Page 4
TQ3631
Data Sheet
High Gain/Low Linearity Mode
Noise Figure v Freq v Temp
2.50
2.00
1.50
1.00
Noise Figure (dB)
0.50
0.00
1920 1940 1960 1980 2000
Frequency (MHz)
High Gain/Low Linearity Mode
Idd v Vdd v Temp
5.50
5.00
4.50
4.00
Idd (mA)
3.50
3.00
2.50
2.5 2.7 2.9 3.1 3.3
Vdd (V)
-30C
+25C
+85C
-30C
+25C
+85C
BYPASS Mode
Noise Figure v Freq v Temp
3.00
2.50
2.00
1.50
1.00
Noise Figure (dB)
0.50
0.00
1920 1940 1960 1980 2000
Frequency (MHz)
BYPASS Mode
IIP3 v Freq v Temp
35.0
34.0
33.0
32.0
31.0
30.0
29.0
IIP3 (dBm)
28.0
27.0
26.0
-30C
+25C
+85C
25.0
1920 1940 1960 1980 2000
Frequency (MHz)
-30C
+25C
+85C
BYPASS Mode
Gain v Freq v Temp
0.0
-0.5
-1.0
-1.5
Gain (dB)
-2.0
-2.5
-30C
+25C
+85C
-3.0
1920 1940 1960 1980 2000
Frequency (MHz)
BYPASS Mode
Idd v Vdd v Temp
1.60
1.40
1.20
1.00
0.80
Idd (mA)
0.60
0.40
0.20
0.00
2.5 2.7 2.9 3.1 3.3
Vdd (V)
-30C
+25C
+85C
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Page 5
Application/Test Circuit
TQ3631
Data Sheet
Vdd
Control
Logic
C2
Vdd
C7
R1
GND
(paddle)
LNA input LNA output
L1
RF in
GND
RF
out
C8
Lbrd
LNA
GND
C3
Control Logic
Bill of Material for TQ3631 LNA Application/Test Circuit
Component Reference Designator Part Number Value Size Manufacturer
Receiver IC U1 TQ3631 SOT23-8 TriQuint Semiconductor
Capacitor C7 2.7pF 0402
Capacitor C8 1.5pF 0402
Resistor R1
3.3Ω
Inductor L1 3.9nH 0402 Panasonic
Inductor Lbrd See application note
0402
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TQ3631
Data Sheet
TQ3631 Product Description
The TQ3631 LNA uses a cascode low noise amplifier along with
signal path switching. A bias control circuit sets the quiescent
current for each mode and ensures peak performance over
process and temperature, see Figure 1. In the application,
CMOS level signals are applied to pins 1 and 5 and are
decoded by an internal logic circuit, this sets the device to the
desired mode. See Table 1 for truth table.
In the high gain mode, switches S1, S2, and S5 are closed, with
switches S3 and S4 open. In the bypass mode, switches S1,
S2, and S5 are open, with switches S3 and S4 closed. Six
internal switches ensures there are no parasitic feedback paths
for the RF signal. In the AMPS mode, control logic switches the
LNA into a low current bias condition.
Only three external components are. The chip uses an external
cap and inductor for the input match to pin 3. The output is
internally matched to 50 ohms at pin 6. A Vdd bypass cap is
required close to pin 8.
External degeneration of the cascode is required between pin 4
and ground. However, a small amount of PC board trace can
be used as the inductor. Alternatively, if an extra component
can be tolerated, a small value chip inductor could be used.
See Figure 2.
VDD
R1
VDD
8
C7
7
GND
LNA OUT
S2
6
RF
OUT
Control
Logic C3
5
LNA IN
Control
Logic C2
C8
1
2
GND
L1
3
RFIN
4
Lbrd
GND
DC
Bias and Switch Control Logic
S6
S1
S3 S4
S5
Figure 1 TQ3631 Simplified Schematic
Operation
MODE C2 C3 Typical Gain
High Gain 0
High Gain
1
0 1 11(dB)
0
13(dB)
0
Low linearity
Bypass 1 1 -2(dB)
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA’s is a straightforward
compromise between noise figure and gain. The TQ3631 is no
exception, even though it has 3 different modes. The device
was designed so that one only needs to optimize the input
match in the high gain mode. As long as the proper grounding
and source inductance are used, the other two modes will
perform well with the same match.
It is probably wise to synthesize the matching network
component values for some intermediate range of Gamma
values, and then by experimentation, find the one which
provides the best compromise between noise figure and gain.
The quality of the chip ground will have some effect on the
match, which is why some experimentation will likely be needed.
The input match will affect the output match to some degree, so
S22 should be monitored.
The values used on our evaluation board may be used as a
starting point.
Noise Parameter Analysis
A noise parameter analysis is shown on the next page for the
high gain mode. A “nominal” device was mounted directly on an
evaluation board with semi-rigid probes attached to the device
input and output pins. A value of Lbrd was chosen so that
13.0dB of gain was attained at conjugate match. The tuner was
removed and noise data was taken.
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Page 7
Gamma Opt analysis for TQ3631 High Gain Mode
TQ3631
Data Sheet
Freq.
(MHz)
1800 0.453 95.8 1.476 14.2
1960 0.459 109.4 1.178 9.58
2040 0.437 116.4 1.287 8.17
Opt Angle Fmin
(dB)
R noise
Gain Control via Pin 4 Inductance
The source connection of the LNA cascode is brought out
separately through pin 4. That allows the designer to make
some range of gain adjustment. The total amount of inductance
present at the source of the cascode is equal to the bond wire
plus package plus external inductance. One should generally
use an external inductance such that gain in the high gain
CDMA mode = 13.0dB. Although it is possible to increase the
gain of the TQ3631 by using little or no degeneration, input
intercept will be degraded.
Figure 2 shows how a spiral PC board trace can be used as the
external inductance. It is suggested that such a circuit be used
for the initial design prototype. Then the optimum inductance
can be found by simply solder bridging across the inductor. The
final PC board design can then include the proper shorted
version of the inductor.
Figure 2 Showing Lbrd and Grounding on Evaluation Board
Selection of the Vdd Bypass Cap for Optimum
Performance
The Vdd bypass capacitor has the largest effect on the LNA
output match, and is required for proper operation. Because the
input match affects the output match to some degree as well,
the process of picking the bypass cap value involves some
iteration. First, an input match is selected which gives adequate
gain and noise figure. Then the bypass capacitor is varied to
give the best output match. The demo board achieves 11-12dB
of return loss which is adequate for connection directly to the
input of a SAW filter.
Grounding
An optimal ground for the device is important in order to achieve
datasheet specified performance. Symptoms of a poor ground
include reduced gain and the inability to achieve <2:1 VSWR at
the output when the input is matched. It is recommended to use
multiple vias to a mid ground plane layer. The vias at pins 2 and
7 to this layer should be as close to the lead pads as possible
Additionally, the ground return on the Vdd bypass cap should
provide minimal inductance back to chip pins 2 and 7.
TQ3631 S-Parameters
Following are S-Parameter graphs for the high gain and high
mode. Data was taken on a single “nominal” device at 2.8v
Vdd. The reference planes were set at the end of the package
pins.
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TQ3631
Data Sheet
TQ3631 High Gain Mode S-Parameters S11
TQ3631 High Gain Mode S-Parameters S21
TQ3631 High Gain Mode S-Parameters S12
TQ3631 High Gain Mode S-Parameters S22
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Page 9
Package Pinout
TQ3631
Data Sheet
Control
Logic
C2
GND
RF
IN
GND
Pin Descriptions
Pin Name Pin # Description and Usage
C2 1 Control logic 2
GND 2 Ground, paddle
RF IN 3 RF input, off-chip matching required
DC GND 4 Source of input FET
C3 5 Control logic 3
RF OUT 6 RF output, no matching required
GND 7 Ground
Vdd 8 LNA Vdd, typical 2.8V, C7 capacitor required
C2
L1
VDD
GND
RF
OUT
C3
50 ohm
RF Out
Control
Logic
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Page 10
TQ3631
Data Sheet
Package Type: SOT23-8 Plastic Package
Note 1
PIN 1
FUSED LEAD
b
A
c
e
DESIGNATION DESCRIPTION METRIC ENGLISH NOTE
A OVERALL HEIGHT 1.20 +/-.25 mm 0.05 +/-.250 in 3
A1 STANDOFF .100 +/-.05 mm .004 +/-.002 in 3
b LEAD WIDTH .365 mm TYP .014 in 3
c LEAD THICKNESS .127 mm TYP .005 in 3
D PACKAGE LENGTH 2.90 +/-.10 mm .114 +/-.004 in 1,3
e LEAD PITCH .65 mm TYP .026 in 3
E LEAD TIP SPAN 2.80 +/-.20 mm .110 +/-.008 in 3
E1 PACKAGE WIDTH 1.60 +/-.10 mm .063 +/-.004 in 2,3
L FOOT LENGTH .45 +/-.10 mm .018 +/-.004 in 3
Theta FOOT ANGLE 1.5 +/-1.5 DEG 1.5 +/-1.5 DEG
Notes
1. The package length dimension includes allowance for mold mismatch and flashing.
2. The package width dimension includes allowance for mold mismatch and flashing.
3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error.
A1
E
E1
Note 2
DIE
L
θ
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com Tel: (503) 615-9000
Email: info_wireless@tqs.com Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: info_wireless@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of
this information, and all such inform ation shall be entirely at t he user's own ri sk. Prices and specifications are subject to change without notice. No patent rights or
licenses to a ny of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1 998 TriQuint Semiconductor, Inc. All right s reserved.
Revision A, March, 20 00
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