Datasheet TPS54418 Datasheet (TEXAS INSTRUMENTS)

100

95

90

85

80

75

70

65

60

55

50

0 0.5 1 1.5 2 2.5 3 3.5 4

V =5V, V =1.8V, fsw=500kHz

IN

O

Efficiency-%

LoadCurrent- A

PH

VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54418

EN

RT /CLK

SS

PWRGD

C

ss

R

T

R

3

C

1

C

BOOT

C

O

L

O

R

1

R

2

C

I

VOUT

VIN

AGND

GND

R4

R5

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

2.95 V to 6 V Input, 4 A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™)

1

FEATURES DESCRIPTION

2

• Two 30 m Ω (typical) MOSFETs for high

efficiency at 4 A loads

• 200kHz to 2MHz Switching Frequency

• 0.8 V ± 1% Voltage Reference Over

Temperature

• Synchronizes to External Clock

• Adjustable Slow Start/Sequencing

• UV and OV Power Good Output

• Low Operating and Shutdown Quiescent

Current

• Safe Start-up into Pre-Biased Output

• Cycle by Cycle Current Limit, Thermal and

Frequency Fold Back Protection

• – 40 ° C to 150 ° C Operating Junction

Temperature Range

• Thermally Enhanced 3mm × 3mm 16-pin QFN

APPLICATIONS

• Low-Voltage, High-Density Power Systems

• Point of Load Regulation for High Performance

DSPs, FPGAs, ASICs and Microprocessors

• Broadband, Networking and Optical

Communications Infrastructure

SIMPLIFIED SCHEMATIC

The TPS54418 device is a full featured 6 V, 4 A, synchronous step down current mode converter with two integrated MOSFETs.

The TPS54418 enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2 MHz switching frequency, and minimizing the IC footprint with a small 3mm x 3mm thermally enhanced QFN package.

The TPS54418 provides accurate regulation for a variety of loads with an accurate ± 1% Voltage Reference (VREF) over temperature.

Efficiency is maximized through the integrated 30m Ω MOSFETs and 350 µ A typical supply current. Using the enable pin, shutdown supply current is reduced to 2 µ A by entering a shutdown mode.

Under voltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the slow start pin. An open drain power good signal indicates the output is within 93% to 107% of its nominal voltage.

Frequency fold back and thermal shutdown protects the device during an overcurrent condition.

The TPS54418 is supported in the SwitcherPro Software Tool at www.ti.com/switcherpro .

For more SWIFT

TM

documentation, see the TI

website at www.ti.com/swift .

TM

1

2 SWIFT is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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ORDERING INFORMATION

T

J

– 40 ° C to 150 ° C 3 × 3 mm QFN TPS54418RTE

PACKAGE PART NUMBER

ABSOLUTE MAXIMUM RATINGS

VALUE UNIT

Input voltage VIN – 0.3 to 7 V

EN – 0.3 to 7 BOOT PH + 8 VSENSE – 0.3 to 3 COMP – 0.3 to 3 PWRGD – 0.3 to 7pau SS – 0.3 to 3 RT/CLK – 0.3 to 6

Output voltage BOOT-PH 8 V

PH – 0.6 to 7 PH 10 ns Transient – 2 to 7

Source current EN 100 µ A

RT/CLK 100 µ A

Sink current COMP 100 µ A

PWRGD 10 mA

SS 100 µ A Electrostatic discharge (HBM) 2 kV Electrostatic discharge (CDM) 500 V Operating Junction temperature, T Storage temperature, T

stg

j

– 40 to 150 ° C – 65 to 150 ° C

PACKAGE DISSIPATION RATINGS

(1) (2) (3)

over operating free-air temperature range (unless otherwise noted)

PACKAGE

RTE 37 ° C/W 1 ° C/W

(1) Maximum power dissipation may be limited by overcurrent protection (2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150 ° C. This is the point where

distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150 ° C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information.

(3) Test boards conditions:

a. 2 inches x 2 inches, 4 layers, thickness: 0.062 inch b. 2 oz. copper traces located on the top of the PCB c. 2 oz. copper ground planes on the 2 internal layers and bottom layer d. 4 thermal vias (10mil) located under the device package

THERMAL IMPEDANCE φJTTHERMAL CHARACTERISTIC

JUNCTION TO AMBIENT JUNCTION TO TOP

Product Folder Link(s): TPS54418

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

ELECTRICAL CHARACTERISTICS

TJ= – 40 ° C to 150 ° C, VIN = 2.95 to 6 V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage 2.95 6 V Internal under voltage lockout threshold No voltage hysteresis, rising and falling 2.6 2.8 V Shutdown supply current EN = 0 V, 25 ° C, 2.95 V ≤ VIN ≤ 6 V 2 5 µ A Quiescent Current - I

ENABLE AND UVLO (EN PIN)

Enable threshold Rising 1.16 1.25 1.37 V

Input current µ A

VOLTAGE REFERENCE (VSENSE PIN)

Voltage Reference 2.95 V ≤ VIN ≤ 6 V, – 40 ° C < TJ< 150 ° C 0.795 0.803 0.811 V

MOSFET

High side switch resistance m Ω

Low side switch resistance m Ω

ERROR AMPLIFIER

Input current 7 nA Error amplifier transconductance (gm) – 2 µ A < I(COMP) < 2 µ A, V(COMP) = 1 V 225 µ mhos Error amplifier transconductance (gm) during – 2 µ A < I(COMP) < 2 µ A, V(COMP) = 1 V, 70 µ mhos

slow start Vsense = 0.4 V Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ± 20 µ A COMP to Iswitch gm 13.0 A/V

CURRENT LIMIT

Current limit threshold 5.0 6.4 A

THERMAL SHUTDOWN

Thermal Shutdown 175 ° C Hysteresis 15 ° C

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Switching frequency range using RT mode 200 2000 kHz Switching frequency Rt = 400 k Ω 400 500 600 kHz Switching frequency range using CLK mode 300 2000 kHz Minimum CLK pulse width 75 ns RT/CLK voltage R(RT/CLK)= 400k Ω 0.5 V RT/CLK high threshold 1.6 2.2 V RT/CLK low threshold 0.4 0.6 V RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns PLL lock in time Measure at 500 kHz 14 µ s

PH (PH PIN)

Minimum On time Measured at 50% points on PH, IOUT = 4 A 60 ns

Minimum Off time Prior to skipping off pulses, BOOT-PH = 2.95 V, 60 ns

Rise/Fall Time VIN = 5 V 1.5 V/ns

q

VSENSE = 0.9 V, VIN = 5 V, 25 ° C, RT = 400 k Ω 350 500 µ A

Falling 1.18 Enable threshold + 50 mV -3.2 Enable threshold – 50 mV -0.65

BOOT-PH= 5 V 30 60 BOOT-PH= 2.95 V 44 70 VIN= 5 V 30 60 VIN= 2.95 V 44 70

Measured at 50% points on PH, VIN = 5 V, IOUT = 0 110 A

IOUT = 4 A

Product Folder Link(s): TPS54418

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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ELECTRICAL CHARACTERISTICS (continued)

TJ= – 40 ° C to 150 ° C, VIN = 2.95 to 6 V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

BOOT (BOOT PIN)

BOOT Charge Resistance VIN = 5 V 16 Ω BOOT-PH UVLO VIN = 2.95 V 2.1 V

SLOW START (SS PIN)

Charge Current V(SS) = 0.4 V 1.8 µ A SS to reference crossover 98% nominal 0.9 V SS discharge voltage (overload) VSENSE = 0 V 20 µ A SS discharge current (UVLO, EN, Thermal VIN = 5 V, V(SS) = 0.5 V 1.25 mA

Fault)

POWER GOOD (PWRGD PIN)

VSENSE falling (Fault) 91 % Vref

VSENSE threshold

Hysteresis VSENSE falling 2 % Vref Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 2 nA On resistance 100 Ω Output low I(PWRGD) = 3.5 mA 0.3 V Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 µ A 1.2 1.6 V

VSENSE rising (Good) 93 % Vref VSENSE rising (Fault) 107 % Vref VSENSE falling (Good) 105 % Vref

Product Folder Link(s): TPS54418

PWRGD

BOOT

PH

RT/CLK

EN

AGND

VIN

VSENSE

COMP

15 14 13

GND

12

11

10

9

8

765

16

GND

VIN

PH

1

2

3

4

SS

Thermal

Pad (17)

QFN16

RTEPACKAGE

(TOP VIEW)

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

DEVICE INFORMATION

PIN CONFIGURATION

PIN FUNCTIONS

NAME NO.

AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum

required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.

COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation

components to this pin.

EN 15 Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the

on/off threshold (adjust UVLO) with two additional resistors. GND 3, 4 Power Ground. This pin should be electrically connected directly to the power pad under the IC. PH 10, 11, The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier

12 MOSFET.

PowerPAD 17 GND pin should be connected to the exposed power pad for proper operation. This power pad should be

connected to any internal PCB ground plane using multiple vias for good thermal performance. PWRGD 14 An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,

over/under-voltage or EN shut down. RT/CLK 8 Resistor Timing or External Clock input pin. SS 9 Slow-start. An external capacitor connected to this pin sets the output voltage rise time. VIN 1, 2, 16 Input supply voltage, 2.95 V to 6 V. VSENSE 6 Inverting node of the transconductance (gm) error amplifier.

DESCRIPTION

Product Folder Link(s): TPS54418

ERROR

AMPLIFIER

Boot

Charge

Boot

UVLO

Current

Sense

Oscillator

withPLL

Frequency

Shift

Slope

Compensation

PWM

Comparator

Minimum

COMP Clamp

Maximum

Clamp

Voltage

Reference

Overload Recovery

VSENSE

SS

COMP

RT/CLK

PH

BOOT

VIN

AGND

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

TPS54418RTEBlockDiagram

Logic

Shutdown

PWRGD

POWERPAD

GND

Logic

Shutdown

107%

93%

S

LogicandPWM

Latch

i

1

i

hys

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

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Product Folder Link(s): TPS54418

450

460

470

480

490

500

510

520

530

540

550

f

-SwitchingFrequency-kHz

s

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

RT =400k , V =3.3V

W

I

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

HighSideRdson

V =3.3V

I

HighSideRdson

V =5V

I

LowSideRdson

V =3.3V

I

LowSideRdson

V =5V

I

RDSON-StaticDrain-SourceOn-StateResistance-

W

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3V

IN

6

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

7

HighSideSwitchCurrent- A

0.792

0.794

0.796

0.798

0.8

0.802

0.804

0.806

0.808

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V -VoltageReference-V

ref

V =3.3V

IN

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

2000

80 100 120 140 160 180 200

RT-ResistancekW

f

-SwitchingFrequency-KHz

s

200

300

400

500

600

700

800

900

1000

100 200 300 400 500 600 700 800 900 1000

RT-Resistance-kW

f -

SwitchingFrequncy-KHz

s

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

TYPICAL CHARACTERISTICS CURVES

HIGH SIDE AND LOW SIDE Rdson vs TEMPERATURE FREQUENCY vs TEMPERATURE

Figure 1. Figure 2.

HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE

Figure 3. Figure 4.

SWITCHING FREQUENCY vs RT RESISTANCE LOW SWITCHING FREQUENCY vs RT RESISTANCE HIGH

FREQUENCY RANGE FREQUENCY RANGE

Figure 5. Figure 6.

Product Folder Link(s): TPS54418

0

25

50

75

100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Vsense-V

VsenseFalling

VsenseRising

NormalSwitchingFrequency-%

140

160

180

200

220

240

260

280

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V

IN

EA

-Transconductance- A/Vm

1.15

1.16

1.17

1.18

1.19

1.2

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.3

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V,rising

IN

V =3.3V,falling

IN

EN-Threshold-V

40

45

50

55

60

65

70

75

80

85

90

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V

IN

EA

-Transconductance- A/Vm

EN PinCurrent- Am-

-3.75

-3.65

-3.55

-3.45

-3.35

-3.25

-3.15

-3.05

-2.95

-2.85

-2.75

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =5V,

Ien= Threshold+50mV

IN

EN-PinCurrent- Am

-1.25

-1.15

-1.05

-0.95

-0.85

-0.75

-0.65

-0.55

-0.45

-0.35

-0.25

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =5V,

Ien= Threshold-50mV

IN

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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TYPICAL CHARACTERISTICS CURVES (continued)

SWITHING FREQUENCY vs VSENSE TRANSCONDUCTANCE vs TEMPERATURE

Figure 7. Figure 8.

TRANSCONDUCTANCE (SLOW START) vs JUNCTION

TEMPERATURE ENABLE PIN VOLTAGE vs TEMPERATURE

Figure 9. Figure 10.

PIN CURRENT vs TEMPERATURE PIN CURRENT vs TEMPERATURE

Figure 11. Figure 12.

Product Folder Link(s): TPS54418

SS/TR-ChargeCurrent- Am

-3

-2.8

-2.6

-2.4

-2.2

-2

-1.8

-1.6

-1.4

-1.2

-1

V =5V

IN

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

SS/TR-DischargeCurrent- Am

85

87

89

91

93

95

97

99

101

103

105

V =5V

IN

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V

-InputV

oltage-V

IN

2

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

UVLOStartSwitching

UVLOStopSwitching

0

0.5

1

1.5

2

2.5

3

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

ShutdownSupplyCurrent- Am

V =3.3V

IN

ShutdownSupplyCurrent Am

0

0.5

1

1.5

2

2.5

3

3 3.5 4 4.5 5 5.5 6

V -InputVoltage-V

IN

T =25°C

J

300

310

320

330

340

350

360

370

380

390

400

V =3.3V

IN

I -SupplyCurrent- A

CC

m

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

TYPICAL CHARACTERISTICS CURVES (continued)

CHARGE CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE

Figure 13. Figure 14.

INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE

Figure 15. Figure 16.

SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE SUPPLY CURRENT vs TEMPERATURE

Figure 17. Figure 18.

Product Folder Link(s): TPS54418

I -SupplyCurrent- A

CC

m

300

310

320

330

340

350

360

370

380

390

400

3 3.5 4 4.5 5 5.5 6

V -InputVoltage-V

IN

T =25°C

J

PWRGD-Threshold-%V

r

ef

88

90

92

94

96

98

100

102

104

106

108

110

VsenseRising,V =3.3V

IN

VsenseRising

VsenseFalling

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

RDSON-StaticDrain-SourecOnStateResistance- W

0

20

40

60

80

100

120

140

160

180

200

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V

IN

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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TYPICAL CHARACTERISTICS CURVES (continued)

SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE

Figure 19. Figure 20.

PWRGD ON RESISTANCE vs TEMPERATURE

OVERVIEW

The TPS54418 is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock.

The TPS54418 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the pull up current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54418 is 350 µ A when not switching and under no load. When the device is disabled, the supply current is less than 5 µ A.

The integrated 30 m Ω MOSFETs allow for high efficiency power supply designs with continuous output currents up to 4 amperes.

Figure 21.

Product Folder Link(s): TPS54418

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

The TPS54418 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54418 to operate approaching 100%. The output voltage can be stepped down to as low as the 0.8 V reference.

The TPS54418 has a power good comparator (PWRGD) with 2% hysteresis. The TPS54418 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power

good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 105%.

The SS (slow start) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin for slow start. The SS pin is discharged before the output power up to ensure a repeatable restart after an over-temperature fault, UVLO fault or disabled condition.

The use of a frequency foldback circuit reduces the switching frequency during startup and over current fault conditions to help limit the inductor current.

DETAILED DESCRIPTION

FIXED FREQUENCY PWM CONTROL

The TPS54418 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response performance.

SLOPE COMPENSATION AND OUTPUT CURRENT

The TPS54418 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full duty cycle range.

BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION

The TPS54418 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be

0.1 µ F. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage.

To improve drop out, the TPS54418 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.5 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Since the supply current sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.

ERROR AMPLIFIER

The TPS54418 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is 225 µ A/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating using the SS voltage, the gm is 70 µ A/V. The frequency compensation components are placed between the COMP pin and ground.

Product Folder Link(s): TPS54418

O

0.8 V

R2 = R1

V 0.8 V

æ ö

´

ç ÷

-

è ø

VSENSE

V

O

+

-

TPS54418

R1

R2

0.8V

EN

i

1

i

hys

VIN

+

-

TPS54418

R1

R2

0.6 mA

2.55 mA

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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VOLTAGE REFERENCE

The voltage reference system produces a precise ± 1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier.

ADJUSTING THE OUTPUT VOLTAGE

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a 100 k Ω for the R1 resistor and use the Equation 1 to calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.

(1)

Figure 22. Voltage Divider Circuit

ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT

The TPS54418 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 23 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (V above 2.7 V. The rising threshold (V supply variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54418 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.55 µ A of hysteresis is added. When the EN pin is pulled below 1.18 V, the 2.55 µ A is removed. This additional current facilitates input voltage hysteresis.

Figure 23. Adjustable Under Voltage Lock Out

) should be set to provide enough hysteresis to allow for any input

START

Product Folder Link(s): TPS54418

)

STOP

-

× -

´

START STOP

6

0.944 V V

R1 =

2.59 10

-

×

- + × ´

6

ST OP

1.18 R1

R2 =

V 1.18 R1 3.2 10

Tss(mS) Iss( A)

Css(nF) =

Vref(V)

´ m

SS

TPS54418

EN

PWRGD

SS

EN

PWRGD

EN1=2V/div

PWRGD1=2V/div

Vout1=1/div

Vout2=1V/div

Time=5msec/div

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

SLOW START PIN

The TPS54418 regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the SS pin to ground implements a slow start time. The TPS54418 has an internal pull-up current source of 1.8 µ A which charges the external slow start capacitor. Equation 4 calculates the required slow start capacitor value where Tss is the desired slow start time in ms, Iss is the internal slow start charging current of 1.8 µ A, and Vref is the internal voltage reference of 0.8 V.

If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown event occurs, the TPS54418 stops switching and the SS is discharged to 0 volts before reinitiating a powering up sequence.

SEQUENCING

Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device. Figure 24 shows the sequential method. The power good is coupled to the EN pin on the TPS54418 which enables the second power supply once the primary supply reaches regulation.

Ratiometric start up can be accomplished by connecting the SS pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 4 . The ratiometric method is illustrated in Figure 26 .

(2)

(3)

(4)

Figure 24. Sequential Start-Up Sequence Figure 25. Sequential Startup using EN and PWRGD

Product Folder Link(s): TPS54418

EN1=2V/div

Vout1=1V/div

Vout2=1V/div

Time=5msec/div

SS

TPS54418

EN

PWRGD

SS

TPS54418

EN

PWRGD

W

1.0793

311890

RT (k ) =

Fsw(kHz)

0.9393

133870

Fsw(kHz)

RT(k )=W

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

Figure 26. Schematic for Ratiometric Start-Up Sequence Figure 27. Ratiometric Start-Up using Coupled SS Pins

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CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)

The switching frequency of the TPS54418 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 1000k Ω and minimum of 85 k Ω , respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figures TBD and TBD, or Equation 5 .

To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input voltage and minimum controllable on time should be considered.

The minimum controllable on time is typically 60 ns at full current load and 110 ns at no load, and limits the maximum operating input voltage or output voltage.

OVERCURRENT PROTECTION

The TPS54418 implements a cycle by cycle current limit. During each switching cycle the high side switch current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp functions as a switch current limit.

FREQUENCY SHIFT

To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54418 implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%, then 75%, then 50%, then 25% as the voltage decreases from 0.8 to 0 volts on VSENSE pin to allow the low side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.8 volts. See Figure 7 for details.

Product Folder Link(s): TPS54418

(5)

(6)

TPS54418

Clock

Source

PLL

R

T

RT/CLK

SYNCClock=2V/div

PH=2V/div

Time=500nsec/div

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

REVERSE OVERCURRENT PROTECTION

The TPS54418 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is more than 1.3 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs.

SYNCHRONIZE USING THE RT/CLK PIN

The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 28 . To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least 75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin.

Figure 28. Synchronizing to a System Clock Figure 29. Plot of Synchronizing to System Clock

POWER GOOD (PWRGD PIN)

The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is recommended to use a pull-up resistor between the values of 1k Ω and 100k Ω to a voltage source that is 6 V or less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.

OVERVOLTAGE TRANSIENT PROTECTION

The TPS54418 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next clock cycle.

THERMAL SHUTDOWN

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175 ° C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 160 ° C, the device reinitiates the power up sequence by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15 ° C.

Product Folder Link(s): TPS54418

VSENSE

COMP

VO

R1

R3

C1

C2

R2

CO RO

gm

225 uA/V

0.8 V

PowerStage

13.0 A/V

PH

R

ESR

C

OUT

R

L

b

a

c

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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SMALL SIGNAL MODEL FOR LOOP RESPONSE

Figure 30 shows an equivalent model for the TPS54418 control loop which can be modeled in a circuit simulation

program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 225 µ A/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the R analysis.

with a current source with the appropriate load step amplitude and step rate in a time domain

L

Figure 30. Small Signal Model for Loop Response

SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL

Figure 30 is a simple small signal model that can be used to understand how to design the frequency

compensation. The TPS54418 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 7 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 30 ) is the power stage transconductance. The gm for the TPS54418 is 13.0 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 8 . As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 9 ]. The combined effect is highlighted by the dashed line in the right half of Figure 31 . As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

Product Folder Link(s): TPS54418

VO

R

L

VC

fp

fz

Adc

gm

ps

R

ESR

C

OUT

s

1+

2 × z

vo

= Adc

vc

s

1+

2 × p

æ ö ç ÷

p ¦

è ø

´

æ ö ç ÷

p ¦

è ø

ps L

Adc = gm R´

¦

´ ´ p

OU T L

1

p =

C R 2

¦

´ ´ p

OUT ESR

1

z =

C R 2

Vref

VO

R1

R3

C1

C2

R2

CO

5pF

RO

gm

ea

COMP

VSENSE

Type 2 A

Type 2 B

R3

C1

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

(7) (8)

SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION

The TPS54418 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 32 . The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type 2A, one additional high frequency pole is added to attenuate high frequency noise.

Figure 32. Types of Frequency Compensation

The design guidelines for TPS54418 loop compensation are as follows:

1. Tthe modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 11 and Equation 12 .

Derating the output capacitor (C capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, fc. Equation 13 is the geometric mean of the modulator pole and the esr zero and Equation 14 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency.

) may be needed if the output voltage is a high percentage of the

OUT

Product Folder Link(s): TPS54418

(9)

(10)

¦

p ´ ´

Iout m ax

p m od =

2 V out Cout

¦

p ´ ´

1

z m o d =

2 R es r Cout

¦ ¦ ´ ¦

C

= p mod z mod

¦

¦ ¦ ´

C

sw

= p mod

2

p ¦ ´ ´

´ ´

OUT

ea ps

2 × c Vo C

R3 =

gm Vref gm

¦

´ ´ p

OU T L

1

p =

C R 2

´

L OUT

R C

C1 =

R3

´

OUT

Resr C

C2 =

R3

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

2. R3 can be determined by

Where is the gm

amplifier gain (225 µ A/V), gm

ea

ps

3. Place a compensation zero at the dominant pole

4. C2 is optional. It can be used to cancel the zero from Co ’ s ESR.

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(11)

(12) (13)

(14)

(15)

is the power stage gain (13 A/V).

. C1 can be determined by

(16)

(17)

Product Folder Link(s): TPS54418

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

APPLICATION INFORMATION

DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE

This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level. For this example, we start with the following known parameters:

Output Voltage 1.8 V Transient Response 1 to 2A load step Δ Vout = 3% Maximum Output Current 4 A Input Voltage 3.3 V nom. 3 V to 5 V Output Voltage Ripple < 30 mV p-p Start Input Voltage (rising VIN) 3.1 V Stop Input Voltage (falling VIN) 2.8 V Switching Frequency (Fsw) 1000 kHz

SELECTING THE SWITCHING FREQUENCY

The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest switching frequency possible since this produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter ’ s performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a high efficiency operation. Using Equation 5 , R4 is calculated to be 180 k Ω . A standard 1% 182 k Ω value was chosen in the design.

Figure 33. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO

OUTPUT INDUCTOR SELECTION

The inductor selected works for the entire TPS54418 input voltage range. To calculate the value of the output inductor, use Equation 18 . K maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, K

is a coefficient that represents the amount of inductor ripple current relative to the

IND

is normally from 0.1 to 0.3 for the majority of applications.

IND

Product Folder Link(s): TPS54418

´

´ ´ ¦

Vinmax Vout Vout

L1 =

Io Kind Vinmax sw

´

´ ¦

Vinmax Vout Vout

Iripple =

L1 Vinmax sw

æ ö

´ -

´

ç ÷

´ ´ ¦

è ø

2

1 Vo (Vinm ax Vo)

ILrms = Io +

12 Vinmax L1 sw

Iripple

ILpeak = Iout +

2

2 Iout

Co >

sw Vout

´ D

¦ ´ D

1 1

Co >

Voripple

8 sw

Iripple

´

´ ¦

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

For this design example, use K

= 0.3 and the inductor value is calculated to be 0.96 µ H. For this design, a

IND

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nearest standard value was chosen: 1.0 µ H. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from

Equation 20 and Equation 21 .

For this design, the RMS inductor current is 4.014 A and the peak inductor current is 4.58 A. The chosen inductor is a TOKO FDV0630-1R0M. It has a current rating of 9.1 A.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

(18)

(19)

(20)

(21)

OUTPUT CAPACITOR

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary to accomplish this.

For this example, the transient load response is specified as a 3% change in Vout for a load step from 1A (25% load) to 2A (50%). For this example, Δ Iout = 2-1 = 1.0 A and Δ Vout= 0.03 × 1.8 = 0.054 V. Using these numbers gives a minimum capacitance of 37 µ F. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,

Equation 23 yields 4.8uF.

Where Δ Iout is the change in output current, Fsw is the regulators switching frequency and Δ Vout is the allowable change in the output voltage.

Product Folder Link(s): TPS54418

(22)

(23)

Voripple

Resr <

Iripple

´ -

´ ´ ´ ¦

Vo ut (Vinm ax Vout)

Ico rm s =

12 Vinm ax L 1 sw

( )

Vinmin Vout

Vout

Icirm s = Iout

Vinmin V inmin

-

´ ´

Ioutm ax 0 .25

Vin =

Cin s w

´

D

´ ¦

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification. Equation 24 indicates the ESR should be less than 26 m Ω . In this case, the ESR of the ceramic capacitor is much less than 26 m Ω .

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 22 µ F 10 V X5R ceramic capacitors with 3 m Ω of ESR are used.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 333 mA.

INPUT CAPACITOR

The TPS54418 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µ F of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54418. The input ripple current can be calculated using Equation 26 .

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 µ F and one 0.1 µ F 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27 . Using the design example values, Ioutmax=4 A, Cin=10 µ F, Fsw=1 MHz, yields an input voltage ripple of 99 mV and a rms input ripple current of 1.96 A.

(24)

(25)

SLOW START CAPACITOR

The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54418 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start capacitor value can be calculated using Equation 28 . For the example circuit, the slow start time is not too critical since the output capacitor value is 44 µ F which does not require much current to charge to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In TPS54418, Iss is 2 µ A and Vref is 0.8 V.

Product Folder Link(s): TPS54418

(26)

(27)

Tss(ms) Iss( A)

Css(nF) =

Vref(V)

´ m

-

× -

´

START STOP

6

0.944 V V

R1 =

2.59 10

-

×

- + × ´

6

ST OP

1.18 R1

R2 =

V 1.18 R1 3.2 10

-

Vref

R7 = R6

Vo Vref

( )

(

)

( )

Voutmin Ontimemin Fsmax Vinmax Ioutmin 2 RDS Ioutmin RL RDS= ´ ´ - ´ ´ - ´ +

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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BOOTSTRAP CAPACITOR SELECTION

A 0.1 µ F ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating.

UNDER VOLTAGE LOCK OUT SET POINT

The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54418. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 3.1 V (V continue to do so until the input voltage falls below 2.8 V (V

The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 29 and Equation 30 can be used to calculate the resistance values necessary. From Equation 29 and Equation 30 , a 48.7 k Ω between Vin and EN and a 32.4 k Ω between EN and ground are required to produce the 3.1 and 2.8 volt start and stop voltages.

). After the regulator starts switching, it should

START

).

STOP

(28)

(29)

OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION

For the example design, 100 k Ω was selected for R6. Using Equation 31 , R7 is calculated as 80 k Ω . The nearest standard 1% resistor is 80.5 k Ω .

Due to the internal design of the TPS54418, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal vlotage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by

Equation 32

Where: Voutmin = minimum achieveable output voltage Ontimemin = minimum contollable on-time (60 ns typical. 110 nsec no load) Fsmax = maximum switching frequency including tolerance Vinmax = maximum input voltage Ioutmin = minimum load current RDS = minimum high side MOSFET on resistance (30 - 44 m Ω ) RL = series resistance of output inductor

There is also a maximum acheivable output voltage which is limited by the minimum off time. The maximum output voltage is given by Equation 33

(30)

(31)

(32)

Product Folder Link(s): TPS54418

( )

Voutmax 1 Offtimemax Fsmax Vinmin Ioutmax 2 RDS Ioutmax RL RDS= - ´ ´ - ´ ´ - ´ +

¦

p ´ ´

Iout m ax

p m od =

2 V out Cout

¦

p ´ ´

1

z m o d =

2 R es r Cout

¦ ¦ ´ ¦

C

= p mod z mod

¦

¦ ¦ ´

C

sw

= p mod

2

gm

2 × c Vo Co

R3 =

Gm Vref VI

p ¦ ´ ´

´ ´

´Ro Co

C3 =

R3

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

Where: Voutmax = maximum achieveable output voltage Offtimeman = maximum off time (60 nsec typical) Fsmax = maximum switching frequency including tolerance Vinmin = minimum input voltage Ioutmax = maximum load current RDS = maximum high side MOSFET on resistance (60 - 70 m Ω ) RL = series resistance of output inductor

COMPENSATION

There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54418. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.

To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 34 and

Equation 12 . For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V

capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 36 and Equation 37 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 8.04 kHz and fzmod is 2412 kHz. Equation 36 is the geometric mean of the modulator pole and the esr zero and Equation 37 is the mean of modulator pole and the switching frequency. Equation 36 yields 139 kHz and Equation 37 gives 63 kHz. Use the lower value of

Equation 36 or Equation 37 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the

compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).

(33)

The compensation design takes the following steps:

1. Set up the anticipated cross-over frequency. Use Equation 38 to calculate the compensation network ’ s resistor value. In this example, the anticipated cross-over frequency (fc) is 35 kHz. The power stage gain (gm

) is 13 A/V and the error amplifier gain (gm

ps

ea

) is 225 µ A/V.

2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network ’ s capacitor can be calculated from Equation 39 .

3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it.

From the procedures above, the compensation network includes a 7.5 k Ω resistor and a 2700 pF capacitor.

(34)

(35) (36)

(37)

(38)

(39)

Product Folder Link(s): TPS54418

0

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100

0.001 0.01 0.1 1 10

OutputCurrent- A

3.3Vin,1.8Vout

5Vin,1.8Vout

Efficiency-%

50

55

60

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80

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95

100

0 1 2 3 4

OutputCurrent- A

3.3Vin,1.8Vout

5Vin,1.8Vout

Efficiency-%

Vout=50mV/div(accoupled)

Iout=2 A /div(0A to4 A loadstep)

Time=500 μsec/div

Vout=50mV/div(accoupled)

Iout=1 A /div(1A to3 A loadstep)

Time=600 μsec/div

Vin=5V/div

EN=2V/div

SS=2V/div

Vout=2V/div

Time=5msec/div

Vin=5V/div

EN=2V/div

SS=2V/div

Vout=2V/div

Time=5msec/div

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

APPLICATION CURVES

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EFFICIENCY EFFICIENCY

vs vs

LOAD CURRENT LOAD CURRENT

Figure 34. Figure 35.

TRANSIENT RESPONSE, 2 A STEP TRANSIENT RESPONSE, 4 A STEP

Figure 36. Figure 37.

POWER UP VOUT, VIN POWER DOWN VOUT, VIN

Figure 38. Figure 39.

Product Folder Link(s): TPS54418

Vin=5V/div

EN=2V/div

SS=2V/div

Vout=2V/div

Time=5msec/div

Vin=5V/div

EN=2V/div

SS=2V/div

Vout=2V/div

Time=5msec/div

Vout=10mV/div(accoupled)

PH=2V/div

Time=500nsec/div

Vout=10mV/div(accoupled)

PH=2V/div

Time=500msec/div

Vin=100mV/div(accoupled)

PH=2V/div

Time=500nsec/div

Vin=100mV/div(accoupled)

PH=2V/div

Time=500nsec/div

TPS54418

www.ti.com

........................................................................................................................................................................................................ SLVS946 – MAY 2009

POWER UP VOUT, EN POWER DOWN VOUT, EN

Figure 40. Figure 41.

OUTPUT RIPPLE, 0 A OUTPUT RIPPLE, 4 A

Figure 42. Figure 43.

INPUT RIPPLE, 0 A INPUT RIPPLE, 4 A

Figure 44. Figure 45.

Product Folder Link(s): TPS54418

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0 1 2 3 4

OutputCurrent- A

PercentDeviation-%

Vin=3.3

Gain

-60

-50

-40

-30

-20

-10

0

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Frequency-Hz

-180

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-90

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-30

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180

Phase-Deg

100

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10000

100000

1000000

Phase

Gain

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0 1 2 3 4

OutputCurrent- A

PercentDeviation-%

Vin=5.0V

-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

3 4 5 6

InputVoltage-V

Iout=2 A

PercentDeviation-%

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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LOAD REGULATION

vs

CLOSED LOOP RESPONSE, VIN (3.3 V), 4 A LOAD CURRENT

Figure 46. Figure 47.

LOAD REGULATION REGULATION

vs vs

LOAD CURRENT INPUT VOLTAGE

Figure 48. Figure 49.

POWER DISSIPATION ESTIMATE

The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).

Pcon = Io Pd = ƒ sw × Iout × 0.7 × 60 × 10

Psw = 2 × Vin Pgd = 2 × Vin × 3 × 10 Pq = 350 × 10

Where:

IOUT is the output current (A). Rdson is the on-resistance of the high-side MOSFET ( Ω ). VOUT is the output voltage (V).

2

× Rdson

2

× ƒ sw × Io × 0.25 × 10

-6

× Vin

-9

× ƒ sw

Product Folder Link(s): TPS54418

20

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130

140

150

0 0.5 1 1.5 2 2.5 3 3.5

Tj-JunctionTemperature

PowerDissapated(W)

Ta=roomtemperature,noairflow

TPS54418

www.ti.com

........................................................................................................................................................................................................ SLVS946 – MAY 2009

VIN is the input voltage (V). ƒ sw is the switching frequency (Hz).

So

Ptot = Pcon + Pd + Psw + Pgd + Pq

For given TA,

TJ = TA + Rth × Ptot

For given TJMAX = 150 ° C

TAmax = TJ max – Rth × Ptot

Where:

Ptot is the total device power dissipation (W). TA is the ambient temperature ( ° C). TJ is the junction temperature ( ° C). Rth is the thermal resistance of the package ( ° C/W). TJMAX is maximum junction temperature ( ° C). TAMAX is maximum ambient temperature ( ° C).

There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator. As an example, the maximum ambient temperature versus power dissapation for the EVM is shown in Figure 51 .

Figure 50. Junction Temperature vs IC Power Dissipation

Product Folder Link(s): TPS54418

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0 0.5 1 1.5 2 2.5 3 3.5

PowerDissapated(W)

TAmax-Maximum AmbientTemperature-C

Tjmax=150 C,noairflow°

TPS54418

SLVS946 – MAY 2009 ........................................................................................................................................................................................................

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Figure 51. Maximum Ambient Temperature vs IC power Dissipation

LAYOUT

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 52 for a PCB layout example. The GND pins and AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors. For operation at full rated load, the top side ground area along with any additional internal ground planes must provide adequate heat dissipating area.

Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output inductor. Since the PH connection is the switching node, the output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

Product Folder Link(s): TPS54418

VIN

GND

EN

GND

VSENSE

SS

PH

PWRGD

BOOT

RT/CLK

COMP

AGND

PH

BOOT CAPACITOR

VOUT

OUTPUT INDUCTOR

OUTPUT FILTER CAPACITOR

SLOWSTART CAPACITOR

COMPENSATION NETWORK

TOPSIDE GROUND AREA

VIA toGroundPlane

FREQUENCY SET RESISTOR

ANALOG GROUND TRACE

VIN INPUT BYPASS CAPACITOR

VIN

UVLOSET RESISTRORS

FEEDBACK RESISTORS

VIA to Ground Plane

EXPOSED POWERPAD AREA

TPS54418

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........................................................................................................................................................................................................ SLVS946 – MAY 2009

Figure 52. PCB Layout Example

Product Folder Link(s): TPS54418

PACKAGE OPTION ADDENDUM

www.ti.com 1-Jun-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPS54418RTER ACTIVE QFN RTE 16 3000 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

no Sb/Br)

TPS54418RTET ACTIVE QFN RTE 16 250 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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Datasheet TPS54418 Datasheet (TEXAS INSTRUMENTS)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

SIMPLIFIED SCHEMATIC

ABSOLUTE MAXIMUM RATINGS

PACKAGE DISSIPATION RATINGS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

TYPICAL CHARACTERISTICS CURVES

OVERVIEW

DETAILED DESCRIPTION

FIXED FREQUENCY PWM CONTROL

SLOPE COMPENSATION AND OUTPUT CURRENT

BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION

ERROR AMPLIFIER

VOLTAGE REFERENCE

ADJUSTING THE OUTPUT VOLTAGE

ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT

SLOW START PIN

SEQUENCING

CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)

OVERCURRENT PROTECTION

FREQUENCY SHIFT

REVERSE OVERCURRENT PROTECTION

SYNCHRONIZE USING THE RT/CLK PIN

POWER GOOD (PWRGD PIN)

OVERVOLTAGE TRANSIENT PROTECTION

THERMAL SHUTDOWN

SMALL SIGNAL MODEL FOR LOOP RESPONSE

SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL

SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION

APPLICATION INFORMATION

DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE

SELECTING THE SWITCHING FREQUENCY

OUTPUT INDUCTOR SELECTION

OUTPUT CAPACITOR

INPUT CAPACITOR

SLOW START CAPACITOR

BOOTSTRAP CAPACITOR SELECTION

UNDER VOLTAGE LOCK OUT SET POINT

OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION

COMPENSATION

APPLICATION CURVES

POWER DISSIPATION ESTIMATE

LAYOUT