Page 1
V = 50 mV / div (-950 mV dc offset)
O
I = 1 A / div (0.75 to 2.25 A load step,
slew rate = 1 A / µsec)
O
Time = 50 µsec / div
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TPS54328
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TPS54328 4.5-V to 18-V Input, 3-A Synchronous Step-Down Converter With Eco-Mode™
1 Features
1
• D-CAP2™ Mode Enables Fast Transient
Response
• Low Output Ripple and Allows Ceramic Output
Capacitor
• Wide Input Voltage Range: 4.5 V to 18 V
• Output Voltage Range: 0.76 V to 7 V
• Highly Efficient Integrated FETs Optimized for
Lower Duty Cycle Applications
– 100 mΩ (High-Side) and 70 mΩ (Low-Side)
• High Efficiency, Less Than 10 µA at Shutdown
• High Initial Bandgap Reference Accuracy
• Adjustable Soft Start
• Pre-Biased Soft Start
• 700-kHz Switching Frequency (fSW)
• Cycle-By-Cycle Overcurrent Limit
• Auto-Skip Eco-Mode™ for High Efficiency at Light
Load
2 Applications
• Wide Range of Applications for Low Voltage
Systems
– Digital TV Power Supplies
– High Definition Blu-ray Disc™ Players
– Networking Home Terminals
– Digital Set Top Boxes (STB)
3 Description
The TPS54328 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54328
enables system designers to complete the suite of
various end-equipment power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54328 uses the D-CAP2 mode control that
provides a fast transient response with no external
compensation components.
The adaptive on-time control supports seamless
transition between PWM mode at higher load
conditions and Eco-mode operation at light loads.
Eco-mode allows the TPS54328 to maintain high
efficiency during lighter load conditions. The
TPS54328 also has a proprietary circuit that enables
the device to adopt to both low equivalent series
resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
input (VIN).
The output voltage can be programmed from 0.76 V
to 7 V. The device also features an adjustable soft
start time. The TPS54328 is available in 8-pin DDA
and 10-pin DRC packages, and is designed to
operate over the ambient temperature range of –40°C
to 85°C.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54328
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HSOP (8) 4.89 mm × 3.90 mm
VSON (10) 3.00 mm × 3.00 mm
(1)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Simplified Schematic TPS54320 Transient Response
Page 2
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
www.ti.com
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
7 Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application.................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
10.3 Thermal Considerations........................................ 17
11 Device and Documentation Support................. 18
11.1 Device Support...................................................... 18
11.2 Documentation Support ........................................ 18
11.3 Receiving Notification of Documentation Updates 18
11.4 Community Resources.......................................... 18
11.5 Trademarks ........................................................... 18
11.6 Electrostatic Discharge Caution............................ 18
11.7 Glossary ................................................................ 18
12 Mechanical, Packaging, and Orderable
Information........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2012) to Revision D Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
• Changed heartsick to heatsink in Thermal Considerations section...................................................................................... 17
Changes from Revision B (April 2012) to Revision C Page
• Changed the Description text to include the DRC package................................................................................................... 1
• Added the DRC-10 pin Package to the ORDERING INFORMATION table........................................................................... 1
• Added Figure 17................................................................................................................................................................... 16
Changes from Revision A (January 2012) to Revision B Page
• Deleted Swift™ from the data sheet title................................................................................................................................ 1
• Changed Figure 9 and Figure 10 ......................................................................................................................................... 13
Changes from Original (November 2010) to Revision A Page
• Added condition to the TYPICAL CHARACTERISTICS title line, all pages........................................................................... 6
• Changed the Functional Block Diagram................................................................................................................................. 8
2
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Page 3
1EN 10 VIN
2VFB 9 VIN
3VREG5 8 VBST
4SS 7 SW
5GND 6 SW
Not to scale
Thermal Pad
1EN 8 VIN
2VFB 7 VBST
3VREG5 6 SW
4SS 5 GND
Not to scale
Thermal Pad
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5 Pin Configuration and Functions
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
DDA Package
8-Pin HSOP
Top View
DRC Package
10-Pin VSON
Top View
Pin Functions
PIN
NAME HSOP VSON
EN 1 1 I Enable input control. Active high.
GND
5 — —
— 5 — Ground pin. Connect sensitive SS and VFB returns to GND at a single point.
SS 4 4 I Soft-start control. An external capacitor must be connected to GND.
SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET.
VBST 7 8 I
VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider.
VIN 8 9, 10 I Input voltage supply pin.
VREG5 3 3 O
Exposed
Back side — —
Thermal
Pad
— Back side —
I/O DESCRIPTION
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB
returns to GND at a single point.
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between
VBST and SW pins. An internal diode is connected between VREG5 and VBST.
5.5-V power-supply output. A capacitor (typically 1 µF) must be connected to GND. VREG5
is not active when EN is low.
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
Thermal pad of the package. PGND power ground return of internal low-side FET. Must be
soldered to achieve appropriate dissipation.
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SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VIN, EN –0.3 20
VBST –0.3 26
VBST (10 ns transient) –0.3 28
Input voltage
Output voltage
Voltage from GND to thermal pad, V
Operating junction temperature, T
Storage temperature, T
stg
diff
J
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VBST (vs SW) –0.3 6.5
VFB, SS –0.3 6.5
SW –2 20
SW (10-ns transient) –3 22
VREG5 –0.3 6.5
GND –0.3 0.3
(1)
MIN MAX UNIT
V
V
–0.2 0.2 V
–40 150 °C
–55 150 °C
6.2 ESD Ratings
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1)
(2)
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
V
I
OUT
T
T
IN
OUT
A
J
Supply input voltage 4.5 18 V
VBST –0.1 24
VBST (10-ns transient) –0.1 27
VBST(vs SW) –0.1 5.7
SS –0.1 5.7
Input voltage
EN –0.1 18
VFB –0.1 5.5
SW –1.8 18
SW (10-ns transient) –3 21
GND –0.1 0.1
Output voltage VREG5 –0.1 5.7 V
Output current I
VREG5
0 10 mA
Operating free-air temperature –40 85 °C
Operating junction temperature –40 150 °C
VALUE UNIT
±2000
±500
V
V
4
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TPS54328
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SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
6.4 Thermal Information
TPS54328
THERMAL METRIC
(1)
UNITDDA (HSOP) DRC (VSON)
8 PINS 10 PINS
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
Junction-to-ambient thermal resistance 42.1 43.9 °C/W
Junction-to-case (top) thermal resistance 50.9 55.4 °C/W
Junction-to-board thermal resistance 31.8 18.9 °C/W
Junction-to-top characterization parameter 5 0.7 °C/W
Junction-to-board characterization parameter 13.5 19.1 °C/W
Junction-to-case (bottom) thermal resistance 7.1 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VIN= 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I
VIN
I
VINSDN
LOGIC THRESHOLD
V
ENH
V
ENL
VFBVOLTAGE AND DISCHARGE RESISTANCE
V
FBTH
I
VFB
VREG5 OUTPUT
V
VREG5
V
LN5
V
LD5
I
VREG5
MOSFET
R
DS(ON)H
R
DS(ON)L
CURRENT LIMIT
I
OCL
THERMAL SHUTDOWN
T
SDN
ON-TIME TIMER CONTROL
t
ON
t
OFF(MIN)
SOFT START
I
SSC
I
SSD
(1) Not production tested.
Operating non-switching supply current VIN current, TA= 25°C, EN = 5 V, VFB= 0.8 V 800 1200 µA
Shutdown supply current VIN current, TA= 25°C, EN = 0 V 1.8 10 µA
EN high-level input voltage EN 1.6 V
EN low-level input voltage EN 0.45 V
VFB threshold voltage
TA= 25°C, V
Eco-mode operation
TA= 25°C, V
operation
= 1.05 V, I
OUT
= 1.05 V, continuous mode
OUT
OUT
= 10 mA,
772 mV
749 765 781 mV
VFB input current VFB= 0.8 V, TA= 25°C 0 ±0.1 µA
VREG5 output voltage TA= 25°C, 6 V < VIN< 18 V, 0 < I
Line regulation 6 V < VIN< 18 V, I
Load regulation 0 mA < I
Output current VIN= 6 V, V
High-side switch resistance TA= 25°C, V
< 5 mA 100 mV
VREG5
VREG5
BST
= 5 mA 25 mV
VREG5
= 4 V, TA= 25°C 60 mA
– SW = 5.5 V 100 mΩ
< 5 mA 5.2 5.5 5.7 V
VREG5
Low-side switch resistance TA= 25°C 70 mΩ
Current limit L
Thermal shutdown threshold
= 1.5 µH
OUT
Shutdown temperature
Hysteresis
ON time VIN= 12 V, V
(1)
, TA= –20ºC to 85ºC 3.5 4.2 5.7 A
(1)
(1)
= 1.05 V 150 ns
OUT
165
30
Minimum off time TA= 25°C, VFB= 0.7 V 260 310 ns
SS charge current VSS= 0 V 1.4 2 2.6 µA
SS discharge current VSS= 0.5 V 0.05 0.1 mA
°C
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Page 6
1.04
1.05
1.06
1.07
1.08
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I - Output Current - A
O
V - Output Voltage - V
O
V = 5.5 V
IN
V = 12 V
IN
V = 18 V
IN
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12 14 16 18 20
EN-InputVoltage-V
V =18V
IN
EN-InputCurrent- Am
0
200
400
600
800
1000
1200
-50
0
50 100 150
T - Junction Temperature - °C
j
I - Supply Current - µA
VIN
0
2.0
4.0
6.0
8.0
10.0
-50
0
50 100 150
T - Junction Temperature - °C
j
I - Supply Current - µA
VINSDN
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
Electrical Characteristics (continued)
over operating free-air temperature range, VIN= 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO
UVLO UVLO threshold
Wake up VREG5 voltage 3.45 3.75 4.05
Hysteresis VREG5 voltage 0.17 0.32 0.45
6.6 Typical Characteristics
VIN= 12 V, TA= 25°C (unless otherwise noted).
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V
Figure 1. VIN Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
Figure 3. EN Current vs EN Voltage
6
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Figure 4. 1.05-V Output Voltage vs Output Current
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1.04
1.05
1.06
1.07
1.08
0 5 10 15 20
V - Input Voltage - V
IN
V - Output Voltage - V
O
I = 10 mA
O
I = 1 A
O
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Typical Characteristics (continued)
VIN= 12 V, TA= 25°C (unless otherwise noted).
Figure 5. 1.05-V Output Voltage vs Input Voltage
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
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SW
VBST
EN
VFB
GND
VO
4
5
6
2
1
7
VIN
SS
VIN
VREG5
EN
Logic
SW
PGND
Protection
Logic
Ref
SS
UVLO
UVLO
Softstart
SS
REF
TSD
Ref
VREG5
8
VIN
Ceramic
Capacitor
3
SGND
SGND
PGND
PWM
+
-
+
OCP
+
-
VREG5
XCON
VREG5
Control Logic
1 shot
ON
SW
PGND
ZC
+
-
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TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
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7 Detailed Description
7.1 Overview
The TPS54328 is a 3-A, synchronous, step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of lowESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54328 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
8
Page 9
C6(nF) x V x 1.1
C6(nF) x 0.765 x 1.1
REF
t (ms) = =
SS
I ( A) 2
SS
m
( )
( )
2
1
- ×
= =
× ×
IN OUT OUT
OUT LL
IN
V V V
I
L fsw V
TPS54328
www.ti.com
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
Feature Description (continued)
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage (VIN) and the output voltage (V
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2 mode control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54328 uses an adaptive on-time control scheme and does not have a dedicated onboard oscillator. The
TPS54328 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is V
/ VIN, the frequency is constant.
OUT
7.3.3 Auto-Skip Eco-Mode Control
The TPS54328 is designed with Auto-Skip Eco-Mode to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
I
OUT(LL)
current can be calculated in Equation 1.
OUT
) to
(1)
7.3.4 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
2 µA.
(2)
The TPS54328 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that V
starts and ramps up smoothly
OUT
into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.
7.3.5 Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
V
, the on-time, and the output inductor value. During the on time of the low-side FET switch, this current
OUT
decreases linearly. The average value of the switch current is the load current I
. The TPS54328 constantly
OUT
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
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Feature Description (continued)
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
7.3.6 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54328 is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
TPS54328 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS54328 can operate in the normal switching modes. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS54328 operates at a quasi-fixed frequency of
700 kHz.
7.4.2 Standby Operation
When the device is operating in either normal CCM or forced CCM, it may be placed in standby operation mode
by asserting the EN pin low.
10
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TPS54328
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SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54328 is typically used as step down converters, which convert a voltage from 4.5 V to 18 V to a lower
voltage. WEBENCH®software is available to aid in the design and analysis of circuits.
8.2 Typical Application
Figure 6. Schematic Diagram
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER EXAMPLE VALUE
Input voltage 4.5 V to 18 V
Output voltage 1.05 V
Output current 3 A
Output voltage ripple 50 mV
PP
8.2.2 Detailed Design Procedure
To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
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Page 12
2 2
=
IPP
Lo(RMS) O
1
+
12
I I I
lpp
= +
Ipeak
O
2
I
I I
V V
V
IN(max)
OUT
OUT
= x
IPP
V L x
IN(max)
O SW
-
I
f
F =
P
OUT OUT
1
2 L x Cp
V = 0.765 x
OUT
R1
1 +
R2
æ ö
÷
ç
÷
ç
÷
÷
ç
è ø
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
www.ti.com
• Input voltage ripple
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate V
OUT
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance is more
susceptible to noise and voltage errors from the VFB input current is more noticeable.
(3)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54328 is an LC circuit. This LC filter has a double pole at:
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54328. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high-frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values in Table 2.
Table 2. Recommended Component Values
OUTPUT VOLTAGE
(V)
1 6.81 22.1 — 1.5 22 – 68
1.05 8.25 22.1 — 1.5 22 – 68
1.2 12.7 22.1 — 1.5 22 – 68
1.8 30.1 22.1 5 - 22 2.2 22 – 68
2.5 49.9 22.1 5 - 22 2.2 22 – 68
3.3 73.2 22.1 5 - 22 2.2 22 – 68
5 124 22.1 5 - 22 3.3 22 – 68
6.5 165 22.1 5 - 22 3.3 22 – 68
R1 (kΩ) R2 (kΩ) C4 (pF) L1 (µH) C8 + C9 (µF)
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
(5)
12
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(6)
(7)
Product Folder Links: TPS54328
Page 13
EN = 10 V / div
SS = 5 V / div
V = 500 mV / div
O
Time = 2 msec / div
V = 50 mV / div (-950 mV dc offset)
O
I = 1 A / div (0.75 to 2.25 A load step,
slew rate = 1 A / µsec)
O
Time = 50 µsec / div
IN
OUT OUT
=
Co(RMS)
IN
O SW
V x (V - V )
12 x V x L x
I
f
TPS54328
www.ti.com
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
For this design example, the calculated peak current is 3.49 A and the calculated RMS current is 3.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of
11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54328 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.271 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS54328 requires an input decoupling capacitor and a bulk capacitor is required depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. TI recommends an
additional 0.1-µF capacitor from VIN to ground to improve the stability of the over-current limit function. The
capacitor voltage rating requires to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST and SW pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. TI
recommends using a ceramic capacitor.
8.2.3 Application Curves
Figure 7. 1.05 V, Load Transient Response
Figure 8. Start-up Waveform
Product Folder Links: TPS54328
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13
Page 14
V = 50 mV / div (-950 mV dc offset)
O
SW = 10 V / div
Time = 1 µsec / div
V = 50 mV / div (-950 mV dc offset)
O
SW = 10 V / div
Time = 1 µsec / div
400
450
500
550
600
650
700
750
800
850
900
0 0.5 1 1.5 2 2.5 3
I - Output Current - A
O
F - Switching Frequency - kHz
S
V = 1.05 V
O
V = 3.3 V
O
V = 1.8 V
O
V = 12 V
IN
400
450
500
550
600
650
700
750
800
850
900
0 5 10 15 20
V - Input Voltage - V
IN
F - Switching Frequency - kHz
S
V = 1.05 V
O
V = 3.3 V
O
V = 1.8 V
O
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3
Iout−Output Current (A)
Efficiency (%)
VO = 3.3V
VO = 2.5 V
VO = 1.8 V
G008
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Iout−Output Current (A)
Efficiency (%)
VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
G009
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
Figure 9. Efficiency vs Output Current Figure 10. Light Load Efficiency vs Output Current
www.ti.com
Figure 11. Switching Frequency vs Input Voltage
Figure 13. Voltage Ripple at Output
14
Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
I
= 3 A
OUT
Product Folder Links: TPS54328
Figure 12. Switching Frequency vs Output Current
I
= 30 mA
OUT
Figure 14. DCM Voltage Ripple at Output
Page 15
V = 50 mV / div
IN
SW = 5 V / div
Time = 1 µsec / div
TPS54328
www.ti.com
I
= 3 A
OUT
Figure 15. Voltage Ripple at Input
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
9 Power Supply Recommendations
The TPS54328 is designed to operate from input supply voltage of 4.5 V to 18 V. Buck converters require the
input voltage to be higher than the output voltage for proper operation. The maximum recommended operating
duty cycle is 65%. Using that criteria, the minimum recommended input voltage is V
OUT
/ 0.65.
10 Layout
10.1 Layout Guidelines
• Keep the input switching current loop as small as possible.
• Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
• Keep the pattern lines for VIN and PGND broad.
• Exposed pad of device must be connected to PGND with solder.
• VREG5 capacitor must be placed near the device, and connected PGND.
• Output capacitor must be connected to a broad pattern of the PGND.
• Voltage feedback loop must be as short as possible, and preferably with ground shield.
• Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
• Providing sufficient vias is preferable for VIN, SW and PGND connection.
• PCB pattern for VIN, SW, and PGND must be as broad as possible.
• VIN capacitor must be placed as near as possible to the device.
Product Folder Links: TPS54328
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15
Page 16
VFB
VREG5
SS
GND
EN VIN
VBST
SW
EXPOSED
THERMAL PAD
AREA
BOOST
CAPACITOR
VOUT
VIA to Ground Plane
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
POWER GROUND
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
VIN
HIGH FREQUENCY
BYPASS
CAPACITOR
VIN
SW
VFB
VREG5
SS
GND
EN
VIN
VBST
SW
EXPOSED
THERMAL PAD
AREA
BOOST
CAPACITOR
VOUT
VIA to Ground Plane
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
POWER GROUND
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
10.2 Layout Example
www.ti.com
16
Figure 16. PCB Layout
Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
Figure 17. PCB Layout for the DRC Package
Product Folder Links: TPS54328
Page 17
TPS54328
www.ti.com
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
10.3 Thermal Considerations
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heat
sink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used
as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD™ Thermally Enhanced Package and PowerPAD™ Made Easy.
The exposed thermal pad dimensions for this package are shown in Figure 18.
Figure 18. Thermal Pad Dimensions
Product Folder Links: TPS54328
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17
Page 18
TPS54328
SLVSAN2D –NOVEMBER 2010–REVISED AUGUST 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the WEBENCH Tools, go to http://www.ti.com/lsds/ti/analog/webench/overview.page
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• PowerPAD™ Made Easy (SLMA004)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP2, Eco-Mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS54328
Page 19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status
TPS54328DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-2-260C-1 YEAR -40 to 85 54328
TPS54328DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 85 54328
TPS54328DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54328
TPS54328DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 54328
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Samples
Addendum-Page 1
Page 20
PACKAGE OPTION ADDENDUM
www.ti.com
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Page 21
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
TPS54328DDAR SO
Power
TPS54328DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS54328DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Type
PAD
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
Page 22
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54328DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0
TPS54328DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS54328DRCT VSON DRC 10 250 210.0 185.0 35.0
Pack Materials-Page 2
Page 23
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54328DDA DDA HSOIC 8 75 517 7.87 635 4.25
Pack Materials-Page 3
Page 24
GENERIC PACKAGE VIEW
DDA 8 PowerPAD
TM
SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
Page 25
Page 26
Page 27
Page 28
GENERIC PACKAGE VIEW
VSON - 1 mm max heightDRC 10
3 x 3, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
PLASTIC SMALL OUTLINE - NO LEAD
Refer to the product data sheet for package details.
www.ti.com
4226193/A
Page 29
PACKAGE OUTLINE
PIN 1 INDEX AREA
1.0
0.8
0.05
0.00
EXPOSED
THERMAL PAD
SCALE 4.000
A
3.1
2.9
1.65 0.1
2X (0.5)
4X (0.25)
B
3.1
2.9
C
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
SEATING PLANE
0.08 C
(0.2) TYP
2X
2
8X 0.5
(OPTIONAL)
5
1
PIN 1 ID
11
SYMM
10X
0.5
0.3
6
10
SYMM
10X
2.4 0.1
0.30
0.18
0.1 C A B
0.05
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
Page 30
10X (0.6)
10X (0.24)
SYMM
8X (0.5)
(R0.05) TYP
EXAMPLE BOARD LAYOUT
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
1
10
11
(2.4)
(3.4)
(0.95)
5
6
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
Page 31
10X (0.24)
SYMM
10X (0.6)
1
11
EXAMPLE STENCIL DESIGN
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
10
(1.53)
2X
(1.06)
(0.63)
8X (0.5)
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
6
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SCALE:25X
4218878/B 07/2018
www.ti.com
Page 32
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