Datasheet TPS5210PWPR, TPS5210PWP, TPS5210EVM-126, TPS5210EVM-119, TPS5210EVM-116 Datasheet (Texas Instruments)

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TPS5210

PROGRAMMABLE SYNCHRONOUS-BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

±1% Reference Over Full Operating T emperature Range

Synchronous Rectifier Driver for Greater Than 90% Efficiency

Programmable Reference V oltage Range of

1.3 V to 3.5 V

User–Selectable Hysteretic T ype Control

Droop Compensation for Improved Load Transient Regulation

Adjustable Overcurrent Protection

Programmable Softstart

Overvoltage Protection

Active Deadtime Control

Power Good Output

Internal Bootstrap Schottky Diode

Low Supply Current...3-mA Typ

description

The TPS5210 is a synchronous-buck regulator controller which provides an accurate, programmable supply voltage to microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range of 1.3 V to 3.5 V . The output voltage can be set to be equal to the reference voltage or to some multiple of the reference voltage. A hysteretic controller with user-selectable hysteresis and programmable droop compensation is used to dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for the output drivers combine to eliminate destructive faults in the output FET s. The softstart current source is proportional to the reference voltage, thereby eliminating variation of the softstart timing when changes are made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector output low when the output drops 7% below the nominal output voltage. An overvoltage circuit disables the output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing. Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage (5 V or 3.3 V) are within proper operating limits before the controller starts. Single-supply (12 V) operation is easily accomplished using a low-current divider for the required 5-V signals. The output driver circuits include 2-A drivers with internal 8-V gate-voltage regulators. The high-side driver can be configured either as a ground-referenced driver or as a floating bootstrap driver. The TPS5210 is available in a 28-pin SOIC package and a 28-pin TSSOP PowerPAD package. It operates over a junction temperature range of 0°C to 125°C.

AVAILABLE OPTIONS

PACKAGES

SOIC (DW)

TSSOP

(PWP)

0°C to 125°C TPS5210DW TPS5210PWPR

The DW package is available taped and reeled. Add R suffix to device type (e.g., TPS5210DWR).

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

IOUT

DROOP

OCP VHYST VREFB

VSENSE ANAGND SLOWST

BIAS

LODRV

LOHIB

DRVGND

LOWDR

DRV

PWRGD VID0 VID1 VID2 VID3 VID4 INHIBIT IOUTLO LOSENSE HISENSE BOOTLO HIGHDR BOOT V

DW OR PWP PACKAGE

(TOP VIEW)

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SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

11111

Decode

VID0 VID1 VID2 VID3 VID4

Deglitch

100 mV

OVP

1.15 V

ref

PGD

0.93 V

ref

Rising

Edge

Delay

–

PREREG

DRV REG

–

Hysteresis

Setting

–+

VID

MUX

and

Decoder

SLOWST

OCP

INHIBIT

Bandgap Shutdown

VREFB

Shutdown

VSENSE

HIGHIN

HIGHDR

Analog Bias

Slowstart Comp

Hysteresis Comp

CM Filters

VREF

–

28 20 21 1915 7

ANAGND PWRGD LOSENSE IOUTLO HISENSE

2 V

10 V

UVLO

NOCPU

Fault

Shutdown

IOUT

BIAS DRV

BOOT HIGHDR

BOOTLO

LOWDR DRVGND

9 14

16 17

13 12

11 1042523

VID0 VID1 VID2 VID3 VID4

24252627

VREFB DROOP VHYST VSENSE LOHIB LODRV

VREFB

200 kΩ

functional block diagram

Page 3

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ANAGND 7 Analog ground BIAS 9 O Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND. BOOT 16 I Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO. BOOTLO 18 O Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive

configuration. Connect BOOTLO to PGND for ground reference drive configuration.

DROOP 2 I Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load

current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND. DRV 14 O Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DRVGND. DRVGND 12 Drive ground. Ground for FET drivers. Connect to FET PWRGND. HIGHDR 17 O High drive. Output drive to high-side power switching FETs HISENSE 19 I High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for

optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with

high-side FET drain. INHIBIT 22 I Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V

or 5 V). IOUT 1 O Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the

high-side FET s. The voltage on this pin equals 2×R

ds(on)×IOUT . In applications where very accurate current

sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side

FET s. IOUTLO 21 O Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic

capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FET s

are off. Capacitance range should be between 0.033 µF and 0.1 µF. LODRV 10 I Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low. LOHIB 11 I Low side inhibit. Connect to the junction of the high and low side FET s to control the anti-cross-conduction and

eliminate shoot-through current. Disabled when configured in crowbar mode. LOSENSE 20 I Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FET s; for

optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series

with high-side FET drain. LOWDR 13 O Low drive. Output drive to synchronous rectifier FETs OCP 3 I Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. PWRGD 28 O Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.

Open-drain output. SLOWST 8 O Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.

Slowstart current = I

VREFB

15 12-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND.

VHYST 4 I HYSTERESIS set pin. The hysteresis is set with a resistor divider from V

REFB

to ANAGND.

The hysteresis window = 2 × (V

REFB

– V

HYST

) VID0 27 I Voltage Identification input 0 VID1 26 I Voltage Identification input 1 VID2 25 I Voltage Identification input 2 VID3 24 I Voltage Identification input 3 VID4 23 I Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for

setting the output voltage is located in T able 1. Internally pulled up to 5 V with a resistor divider biased from V

VREFB 5 O Buffered reference voltage from VID network VSENSE 6 I Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is

recommended an RC low pass filter be connected at this pin to filter noise.

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TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

REF

The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to V

. The VID codes conform

to the Intel

VRM 8.3 DC-DC Converter Specification

for voltage settings between 1.8 V and 3.5 V , and they are

decremented by 50 mV , down to 1.3 V, for the lower VID settings. V oltages higher than V

REF

can be implemented

using an external divider. Refer to T able 1 for the VID code settings. The output voltage of the VID network, V

REF

is within ±1% of the nominal setting over the VID range of 1.3 V to

.5 V , including a junction temperature range

of 5°C to +125°C, and a V

supply voltage range of 1 1.4 V to 12.6 V . The output of the reference/VID network

is indirectly brought out through a buffer to the V

REFB

pin. The voltage on this pin will be within 2% of V

REF

. It

is not recommended to drive loads with V

REFB

, other than setting the hysteresis of the hysteretic comparator,

because the current drawn from V

REFB

sets the charging current for the slowstart capacitor. Refer to the

slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by 2 external resistors and is centered on V

REF

. The 2 external resistors form a resistor divider from V

REFB

to ANAGND, with the output voltage connecting to the V

HYST

pin. The hysteresis of the comparator will be equal

to twice the voltage

difference

between the V

REFB

and V

HYST

pins. The propagation delay from the comparator

inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.

low-side driver

The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.

high-side driver

The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating bootstrap driver. When configured as a floating driver , the bias voltage to the driver is developed from the DR V regulator. The internal bootstrap diode, connected between the DR V and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or V

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate-drive voltage to the low-side FET s is below 2 V ; the low-side driver is not allowed to turn on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.

current sensing

Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the high-side FET s are on. The sampling network consists of an internal 60- Ω switch and an external ceramic hold capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low . The sampling will occur only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the current sensing circuit.

Page 5

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

droop compensation

The droop compensation network reduces the load transient overshoot/undershoot on V

, relative to V

REF

. V

is programmed to a voltage greater than V

REF

by an external resistor divider from VO to VSENSE to reduce the

undershoot on V

during a low-to-high load transient. The overshoot during a high-to-low load transient is

reduced by subtracting the voltage on DROOP from V

REF

. The voltage on IOUT is divided with an external

resistor divider, and connected to DROOP.

inhibit

INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low , the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart capacitor is released and normal converter operation begins. When the system-logic supply is connected to INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.

undervoltage lockout (UVLO)

The undervoltage lockout circuit disables the controller while the V

supply is below the 10-V start threshold during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is discharged. When V

exceeds the start threshold, the short across the slowstart capacitor is released and normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise immunity.

slowstart

The slowstart circuit controls the rate at which V

powers up. A capacitor is connected between SLOWST and ANAGND and is charged by an internal current source. The current source is proportional to the reference voltage, so that the charging rate of C

slowst

is proportional to the reference voltage. By making the charging

current proportional to V

REF

, the power-up time for VO will be independent of V

REF

. Thus, C

SLOWST

can remain

the same value for all VID settings. The slowstart charging current is determined by the following equation:

slowstart

= I(V

REFB

) / 5 (amps)

Where I(V

REFB

) is the current flowing out of V

REFB

It is recommended that no additional loads be connected to V

REFB

, other than the resistor divider for setting the

hysteresis voltage. The maximum current that can be sourced by the V

REFB

circuit is 500 µA. The equation for

setting the slowstart time is:

SLOWST

= 5 × C

SLOWST

× R

VREFB

(seconds)

Where R

VREFB

is the total external resistance from V

REFB

to ANAGND.

power good

The power-good circuit monitors for an undervoltage condition on V

. If VO is 7% below V

REF

, then the PWRGD

pin is pulled low. PWRGD is an open-drain output.

overvoltage protection

The overvoltage protection (OVP) circuit monitors V

for an overvoltage condition. If VO is 15% above V

REF

then a fault latch is set and both output drivers are turned off. The latch will remain set until V

goes below the undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section for information on how to protect the microprocessor against overvoltages due to a shorted fault across the high-side power FET.

Page 6

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

overcurrent protection

The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage connected to the OCP pin. If the voltage on OCP exceeds 100 mV , then a fault latch is set and the output drivers are turned off. The latch will remain set until V

goes below the undervoltage lockout value. A 3-µs deglitch

timer is included for noise immunity .

The OCP circuit is also designed to protect the high-side power FET against

a short-to-ground fault on the terminal common to both power FETs.

drive regulator

The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V . The minimum short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.

LODRV

The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side power FETs become shorted. External components to sense an overvoltage condition are required to use this feature. When an overvoltage fault occurs, the low-side FET s are used as a crowbar . LODR V is pulled low and the low-side FET will be turned on, overriding all control signals inside the TPS5210 controller. The crowbar action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse in series with V

should be added to disconnect the short-circuit.

Table 1. Voltage Identification Codes

VID TERMINALS

(0 = GND, 1 = floating or pull-up to 5 V)

REF

VID4 VID3 VID2 VID1 VID0 (Vdc)

0 1 1 1 1 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 0 1 0 0 0 1.65 0 0 1 1 1 1.70 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 No CPU 1 1 1 1 0 2.10 1 1 1 0 1 2.20 1 1 1 0 0 2.30 1 1 0 1 1 2.40 1 1 0 1 0 2.50 1 1 0 0 1 2.60

Page 7

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. Voltage Identification Codes (Continued)

VID TERMINALS

(0 = GND, 1 = floating or pull-up to 5 V)

REF

VID4 VID3 VID2 VID1 VID0 (Vdc)

1 1 0 0 0 2.70 1 0 1 1 1 2.80 1 0 1 1 0 2.90 1 0 1 0 1 3.00 1 0 1 0 0 3.10 1 0 0 1 1 3.20 1 0 0 1 0 3.30 1 0 0 0 1 3.40 1 0 0 0 0 3.50

absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)

†

Supply voltage range, V

(see Note1) –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range: BOOT to DRVGND (High-side Driver ON) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to HIGHDRV –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to BOOTLO –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INHIBIT, VIDx, LODRV –0.3 V to 7.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWRGD, OCP, DROOP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOHIB, LOSENSE, IOUTLO, HISENSE –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . .

VSENSE –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage difference between ANAGND and DRVGND ±0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, V

REFB

0.5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short circuit duration, DRV Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DW 1200 mW 12 mW/°C 660 mW 480 mW

PWP 1150 mW 11.5 mW/°C 630 mW 460 mW

Page 8

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

11.4 13 V

Input voltage, BOOT to DRVGND 0 28 V

Input voltage, BOOT to BOOTLO 0 13 V Input voltage, INHIBIT, VIDx, LODRV, PWRGD, OCP, DROOP 0 6 V Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE 0 13 V Input voltage, VSENSE 0 4.5 V Voltage dif ference between ANAGND and DRVGND 0 ±0.2 V Output current, V

REFB

†

0 0.4 mA

†

Not recommended to load V

REFB

other than to set hystersis since I

VREFB

sets slowstart time.

electrical characteristics over recommended operating virtual junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted)

reference/voltage identification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC = 11.4 to 12.6 V, 1.3 V ≤ V

REF

≤ 2.5 V –0.01 0.01 V/V

VCC = 11.4 to 12.6 V, V

REF

= 2.6 V –0.0104 0.0104 V/V

VCC = 11.4 to 12.6 V, V

REF

= 2.7 V –0.0108 0.0108 V/V

VCC = 11.4 to 12.6 V, V

REF

= 2.8 V –0.0112 0.0112 V/V

VCC = 11.4 to 12.6 V, V

REF

= 2.9 V –0.0116 0.0116 V/V

Reference voltage accuracy, (Includes

offset of droop compensation net-

VCC = 11.4 to 12.6 V, V

REF

= 3 V –0.0120 0.0120 V/V

work)

VCC = 11.4 to 12.6 V, V

REF

= 3.1 V –0.0124 0.0124 V/V

VCC = 11.4 to 12.6 V, V

REF

= 3.2 V –0.0128 0.0128 V/V

VCC = 11.4 to 12.6 V, V

REF

= 3.3 V –0.0132 0.0132 V/V

REF

VCC = 11.4 to 12.6 V, V

REF

= 3.4 V –0.0136 0.0136 V/V

VCC = 11.4 to 12.6 V, V

REF

= 3.5 V –0.0140 0.0140 V/V

REF

= 1.3 V, Hysteresis window = 30 mV –0.011 0.011

REF

=1.3 V , Hysteresis,

TJ = 60°C window = 30 mV (see Note 3)

–0.008 0.008

Cumulative reference accurac

(see Note 2)

REF

= 1.9 Vv, Hysteresis,

TJ = 60°C window = 30 mV (see Note 3)

–0.0090 0.0090

V/V

REF

= 3.5 V, Hysteresis,

TJ = 60°C window = 30 mV (see Note 3)

–0.0115 0.0115

VIDx High-level input voltage 2.25 V VIDx Low-level input voltage 1 V

Output voltage I

VREFB

= 50 µA V

REF

–2% V

REFVREF

+2% V

REFB

Output regulation 10 µA ≤ IO ≤ 500 µA 2 mV Input resistance VIDx = 0 V 36 73 95 kΩ

VID

Input pull-up voltage divider 4.8 4.9 5 V

NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic

comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.

3. This parameter is ensured by design and is not production tested.

Page 9

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

power good

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Undervoltage trip threshold 90 93 95 %V

REF

Low-level output voltage IO = 5 mA 0.5 0.75 V

High-level input current V

PWRGD

= 6 V 1 µA

hys

Hysteresis voltage 1.3 2.9 4.5 %V

REF

slowstart

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge current

SLOWST

= 0.5 V,

VREFB

= 65 µA

VREFB

= 1.3 V,

10.4 13 15.6 µA

Discharge current V

SLOWST

= 1 V 3 mA Comparator input offset voltage 10 mV Comparator input bias current See Note 3 10 100 nA Comparator hysteresis –7.5 7.5 mV

NOTE 3: This parameter is ensured by design and is not production tested.

hysteretic comparator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input offset voltage V

DROOP

= 0 V (see Note 3) –2.5 2.5 mV Input bias current See Note 3 500 nA Hysteresis accuracy V

REFB

– V

HYST

= 15 mV

(Hysteresis window = 30 mV)

–3.5 3.5 mV

Maximum hysteresis setting V

REFB

– V

HYST

= 30 mV 60 mV

NOTE 3: This parameter is ensured by design and is not production tested.

Page 10

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

high-side VDS sensing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Gain 2 V/V Initial accuracy

HISENSE

= 12 V, V

LOSENSE

= 11.9 V,

Differential input to Vds sensing amp = 100 mV

194 206 mV

IOUTLO Sink current 5 V ≤ V

IOUTLO

≤ 13 V 250 nA

IOUT Source current

IOUT

= 0.5 V, V

HISENSE

= 12 V,

IOUTLO

= 11.5 V

500 µA

IOUT Sink current

IOUT

= 0.05 V , V

HISENSE

= 12 V ,

IOUTLO

= 12 V

50 µA

HISENSE

= 11 V, R

IOUT

= 10 kΩ 0 2 V

Output voltage swing

HISENSE

= 4.5 V, R

IOUT

= 10 kΩ 0 1.5 V

HISENSE

= 3 V, R

IOUT

= 10 kΩ 0 0.75 V

High-level input voltage

2.85 V

LOSENSE

Low-level input voltage

HISENSE

4.5 V (see Note 3)

2.4 V

11.4 V ≤ V

HISENSE

≤ 12.6 V, LOSENSE connected to HISENSE, V

HISENSE

– V

IOUTLO

= 0.15 V

50 60 80

Sample/hold resistance

4.5 V ≤ V

HISENSE

≤ 5.5 V, LOSENSE connected to HISENSE, V

HISENSE

– V

IOUTLO

= 0.15 V

62 85 123

Ω

3 V ≤ V

HISENSE

≤ 3.6 V, LOSENSE connected to HISENSE, V

HISENSE

– V

IOUTLO

= 0.15 V

67 95 144

CMRR

HISENSE

= 12.6 V to 3 V,

HISENSE

– V

OUTLO

= 100 mV

69 75 dB

NOTE 3. This parameter is ensured by design and is not production tested.

inhibit

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start threshold 1.9 2.1 2.35 V Hysteresis 0.08 0.1 0.12 V Stop threshold 1.85 V

overvoltage protection

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Overvoltage trip threshold 112 115 120 %V

REF

Hysteresis See Note 3 10 mV

NOTE 3: This parameter is ensured by design and is not production tested.

overcurrent protection

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OCP trip threshold 90 100 110 mV Input bias current 100 nA

Page 11

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

deadtime

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage 2.4

LOHIB

Low-level input voltage 1.4

High-level input voltage See Note 3 3

LOWDR

Low-level input voltage See Note 3 1.7

NOTE 3: This parameter is ensured by design and is not production tested.

LODRV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage 1.85

LODRV

Low-level input voltage 0.95

droop compensation

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Initial accuracy V

DROOP

= 50 mV 46 54 mV

drive regulator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage 11.4 V ≤ VCC ≤ 12.6 V, I

DRV

= 50 mA 7 9 V

Output regulation 1 mA ≤ I

DRV

≤ 50 mA 100 mV

Short-circuit current 100 mA

bias regulator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage 11.4 V ≤ VCC ≤ 12.6 V, See Note 4 6 V

NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5210 controller. External loads should not be driven by the bias

regulator.

input undervoltage lockout

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start threshold 9.25 10 10.75 V Hysteresis 1.9 2 2.2 V Stop threshold 7.5 V

Page 12

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

output drivers

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-side sink

Duty cycle < 2%, TJ = 125°C,

tpw < 100 µs, V

BOOT

– V

BOOTLO

= 6.5 V,

Peak output

High-side source

HIGHDR

= 1.5 V (source) or 6 V (sink),

See Note 3

curren

(see Note 5)

Low-side sink

Duty Cycle < 2%, TJ = 125°C,

tpw < 100 µs, V

DRV

= 6.5 V,

Low-side source

LOWDR

= 1.5 V (source) or 5 V (sink),

See Note 3

High-side sink

= 125°C, V

– V

= 6.5 V,

Output

High-side source

BOOT BOOTLO

HIGHDR

= 6 V (source) or 0.5 V (sink)

resistance (

see Note 5

)

Low-side sink

TJ = 125°C, V

DRV

= 6.5 V,

5.7

Ω

(see Note 5)

Low-side source

J DRV

LOWDR

= 6 V (source) or 0.5 V (sink)

NOTES: 3. This parameter is ensured by design and is not production tested.

5. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R

ds(on)

of the MOSFET transistor when

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

supply current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage range

11.4 12 13 V

INHIBIT

= 5 V,

VCC > 10.75 V at startup,

VID code ≠ 11111, V

BOOTLO

= 0 V

3 10

Quiescent current

INHIBIT

= 5 V, VCC > 10.75 V at startup, C

HIGHDR

= 50 pF,

SWX

= 200 kHz,

VID code ≠ 11111, V

BOOTLO

= 0 V,

LOWDR

= 50 pF,

See Note 3

High-side

INHIBIT

= 0 V or VID code = 11111 or VCC < 9.25 V at startup, V

BOOT

= 13 V, V

BOOTLO

= 0 V

80 µA

driver

quiescent current

INHIBIT

= 5 V, V

BOOT

= 13 V,

HIGHDR

= 50 pF,

VID code ≠ 11111, VCC > 10.75 V at startup, V

BOOTLO

= 0 V,

SWX

= 200 kHz (see Note 3)

2 mA

NOTE 3: This parameter is ensured by design and is not production tested.

Page 13

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating virtual-junction temperature range, V

= 12 V, I

DRV

= 0 A (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VSENSE to HIGHDR or LOWDR (excluding deadtime)

1.3 V ≤ V

VREF

≤ 3.5 V, 10 mV overdrive

(see Note 3)

150 250 ns

OCP comparator 1

Pro agation delay

OVP comparator

See Note 3

µs PWRGD comparator 1 SLOWST comparator Overdrive = 10 mV (see Note 3) 560 900 ns

HIGHDR output

CL = 9 nF, V

BOOT

= 6.5 V,

BOOTLO

= 0 V, TJ = 125°C

Rise time

LOWDR output

CL = 9 nF, V

DRV

= 6.5 V,

TJ = 125°C

HIGHDR output

CL = 9 nF, V

BOOT

= 6.5 V,

BOOTLO

= 0 V, TJ = 125°C

Fall time

LOWDR output

CL = 9 nF, V

DRV

= 6.5 V,

TJ = 125°C

Deglitch time (Includes

OCP

2 5 comparator propagation delay)

OVP

See Note 3

2 5

HISENSE

= 12 V,

IOUTLO

pulsed from 12 V to 11.9 V,

100 ns rise/fall times (see Note 3)

Response time High-side VDS sensing

HISENSE

= 4.5 V,

IOUTLO

pulsed from 4.5 V to 4.4 V ,

100 ns rise/fall times (see Note 3)

µs

HISENSE

= 3 V,

IOUTLO

pulsed from 3 V to 2.9 V ,

100 ns rise/fall times (see Note 3)

Short-circuit protection rising-edge delay

SCP LOSENSE = 0 V (see Note 3) 300 500 ns

Turn-on/turn-off delay

VDS sensing sample/hold switch

3 V ≤ V

HISENSE

≤ 11 V,

LOSENSE

= V

HISENSE

(see Note 3)

30 100 ns

Crossover delay time

LOWDR to HIGHDRV, and LOHIB to LOWDR

See Note 3 30 100 ns

Prefilter pole frequency Hysteretic comparator See Note 3 5 MHz Propagation delay LODRV See Note 3 400 ns

NOTE 3: This parameter is ensured by design and is not production tested.

Page 14

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 1

SLOWSTART TIME

SLOWSTART CAPACITANCE

0.0001 0.0010

Slowstart Capacitance – µF

100

0.1

Slowstart Time – ms

(VREFB)

= 2 V

(VREFB)

= 100 µA

TJ = 25°C

0.0100 0.1000 1

Figure 2

SLOWSTART TIME

SUPPLY CURRENT (VREFB)

110

– Supply Current (VREFB) – µA

1000

Slowstart Time – ms

(VREFB)

= 2 V CS = 0.1 µF TJ = 25°C

100 1000

100

Figure 3

DRIVER

OUTPUT RISE TIME

LOAD CAPACITANCE

0.1 1 CL – Load Capacitance – nF

100

– Rise Time – ns

TJ = 25°C

10 100

High Side

Low Side

Figure 4

CL – Load Capacitance – nF

0.1 1

1000

10 100

100

– Fall Time – nst

DRIVER

OUTPUT FALL TIME

LOAD CAPACITANCE

TJ = 25°C

High Side

Low Side

Page 15

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 5

TJ – Junction Temperature – °C

OVP THRESHOLD

JUNCTION TEMPERATURE

117

114

112

25 75

116

115

113

50 100 125

118

OVP Threshold – %

Figure 6

TJ – Junction Temperature – °C

OCP THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

25 75

103

101

50 100 125

105

OCP Threshold V oltage – mV

Figure 7

TJ – Junction Temperature – °C

INHIBIT START THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

1.9 25 75

2.05

1.95

50 100 125

2.1

Inhibit Start Threshold Voltage – V

Figure 8

TJ – Junction Temperature – °C

INHIBIT HYSTERESIS VOLTAGE

JUNCTION TEMPERATURE

100

25 75

125

50 100 125

150

Inhibit Hysteresis Voltage – mV

Page 16

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 9

TJ – Junction Temperature – °C

UVLO START THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

25 75

9.5

50 100 125

10.5

UVLO Start Threshold Voltage – V

VI = 12 V

Figure 10

TJ – Junction Temperature – °C

UVLO HYSTERESIS

JUNCTION TEMPERATURE

1.9

1.5 25 75

2.3

2.1

1.7

50 100 125

2.5

UVLO Hysteresis – V

VI = 12 V

Figure 11

TJ – Junction Temperature – °C

QUIESCENT CURRENT

JUNCTION TEMPERATURE

25 75

50 100 125

Quiescent Current – mA

VI = 12 V

Figure 12

TJ – Junction Temperature – °C

POWERGOOD THRESHOLD

JUNCTION TEMPERATURE

25 75

50 100 125

Powergood Threshold – %

Page 17

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 13

TJ – Junction Temperature – °C

SLOW START CHARGE CURRENT

JUNCTION TEMPERATURE

25 75

50 100 125

Slow Start Charge Current – Aµ

(VREFB)

= 1.3 V

(VREFB)

= 20 kΩ

Figure 14

TJ – Junction Temperature – °C

DRIVER

REGULATOR VOLTAGE

JUNCTION TEMPERATURE

7.5 25 75

8.25

7.75

50 100 125

8.5

Regulator Voltage – V

Figure 15

TJ – Junction Temperature – °C

DRIVER

HIGH-SIDE OUTPUT RESISTANCE

JUNCTION TEMPERATURE

25 75

50 100 125

– High-Side Output Resistance – R

Ω

Figure 16

TJ – Junction Temperature – °C

DRIVER

LOW-SIDE OUTPUT RESISTANCE

JUNCTION TEMPERATURE

25 75

50 100 125

– Low-Side Output Resistance – R

Ω

Page 18

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

TJ – Junction Temperature – °C

SENSING SAMPLE/HOLD RESISTANCE

JUNCTION TEMPERATURE

25 75

50 100 125

100

– Sensing Sample/Hold Resistance – R

Ω

(HISENSE)

= 12 V

Figure 17

Page 19

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The following figure is a typical application schematic. The circuit can be divided into the power-stage section and the control-circuit section. The power stage must be tailored to the input/output requirements of the application. The control circuit is basically the same for all applications with some minor tweaking of specific values. Table 2 shows the values of the power stage components for various output-current options.

LODRV

LOHIB

DRVGND

LOWDR

DRV

BOOT

HIGHDR

BOOTLO

HISENSE

VCC

VID4

VID3

VID2

VID1

VID0

INHIBIT

PWRGD

IOUT

BIAS

OCP

VHYST

VSENSE

VREFB

ANAGND

SLOWST

DROOP

LOSENSE

IOUTLO

TPS5210

0.033 uF

1 uF

2.55 k 1%

ENABLE

2200 pF

3.40 k

1 uF

R101

GND

Control Section

Power Stage

12V

Q101

L101

C103C102

C101

Q102

C105

C106

L102

R102

C104

RTN

R10

1.00 k

4.32 k

1.00 k

3.92 k

20.0 k

100

10.0 kR3

1000 pF

0.1 uF

1 uF

150

1 uF

12V

HIGHDRV

HISENSE

LOSENSE

BOOTLO

DRVGND

LOHIB

LODRV

VSENSE

RTN

Figure 18. Standard Application Schematic

Page 20

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 2. Power Stage Components

Ref

12-V–Input Power Stage Components

Des

Function

4–A Out 8–A Out 12–A Out 20–A Out 40–A Out

C101

Input Bulk Capacitor

Sanyo, 16SV100M, 100–uF, 16–V, 20%

Sanyo, 16SA470M, 2 x 470–uF , 16–V, 20%

Sanyo, 16SA470M, 3 x 470–uF , 16–V, 20%

Sanyo, 16SA470M, 4 x 470–uF , 16–V, 20%

C102

Input Mid–Freq Capacitor

muRata, GRM42–6Y5V105Z025A

1.0–uF, 25–V, +80%–20%, Y5V

muRata, GRM42–6Y5V225Z016A

2.2–uF, 16–V, +80%–20%, Y5V

muRata, GRM42–6Y5V225Z016A

2.2–uF, 16–V, +80%–20%, Y5V

muRata, GRM42–6Y5V105Z025A 3 x 1.0–uF , 25–V, +80%–20%, Y5V

muRata, GRM42–6Y5V105Z025A 4 x 1.0–uF , 25–V, +80%–20%, Y5V

C103

Input Hi–Freq Bypass Capacitor

muRata, GRM39X7R104K016A

0.1–uF, 16–V, X7R

muRata, GRM39X7R104K016A,

0.1–uF, 16–V, X7R

muRata, GRM39X7R104K016A, 2 x 0.1–uF , 16–V, X7R

muRata, GRM39X7R104K016A, 3 x 0.1–uF , 16–V, X7R

muRata, GRM39X7R104K016A, 4 x 0.1–uF , 16–V, X7R

C104

Snubber Capacitor

muRata, GRM39X7R102K050A, 1000–pF, 50–V, X7R

muRata, GRM39X7R102K050A, 2 x 1000–pF , 50–V, X7R

muRata, GRM39X7R102K050A, 3 x 1000–pF , 50–V, X7R

muRata, GRM39X7R102K050A, 4 x 1000–pF , 50–V, X7R

C105

Output Bulk Capacitor

Sanyo, 6TPB150M, 3 x 150–uF , 6.3–V, 20%

Sanyo, 4SP820M, 820–uF, 4–V, 20%

Sanyo, 4SP820M, 2 x 820–uF , 4–V, 20%

Sanyo, 4SP820M, 3 x 820–uF , 4–V, 20%

Sanyo, 4SP820M, 4 x 820–uF , 4–V, 20%

C106

Output Hi–Freq Bypass Capacitor

muRata, GRM39X7R104K016A,

0.1–uF, 16–V, X7R

muRata, GRM39X7R104K016A,

0.1–uF, 16–V, X7R

muRata, GRM39X7R104K016A, 2 x 0.1–uF , 16–V, X7R

muRata, GRM39X7R104K016A, 3 x 0.1–uF , 16–V, X7R

muRata, GRM39X7R104K016A, 4 x 0.1–uF , 16–V, X7R

L101

Input Filter Inductor

CoilCraft, DO1608C–332,

3.3–uH, 2.0–A

Coiltronics, UP2B–2R2,

2.2–uH, 7.2–A

Coiltronics, UP2B–2R2,

2.2–uH, 7.2–A

Coiltronics, UP3B–1R0, 1–uH, 12.5–A

L102

Output Filter Inductor

CoilCraft, DO3316P–332,

3.3–uH, 6.1–A

Coiltronics, UP3B–2R2,

2.2–uH, 9.2–A

Coiltronics, UP4B–1R5,

1.5–uH, 13.4–A

MicroMetals, T68–8/90 Core w/7T #16, 1.0–uH, 25–A

Pulse Engineering, P1605,

1.0–uH, 50–A

R101

Lo–Side Gate Resistor

3.3–Ohm, 1/16–W, 5%

2 x 3.3–Ohm, 1/16–W, 5%

3 x 3.3–Ohm, 1/16–W, 5%

4 x 3.3–Ohm, 1/16–W, 5%

R102

Snubber Resistor

2.7–Ohm, 1/10–W, 5%

2 x 2.7–Ohm, 1/10–W, 5%

3 x 2.7–Ohm, 1/10–W, 5%

4 x 2.7–Ohm, 1/10–W, 5%

Q101

Power Switch

Siliconix, Si4410, NMOS, 13–mOhm

Siliconix, 2 x Si4410, NMOS, 13–mOhm

IR, 2 x IRF7811, NMOS, 11–mOhm

Q102

Synchronous Switch

Siliconix, Si4410, NMOS, 13–mOhm

Siliconix, 2 x Si4410, NMOS, 13–mOhm

Siliconix, 3 x Si4410, NMOS, 13–mOhm

IR, 4 x IRF7811, NMOS, 11–mOhm

Nominal Frequency†220 KHz 330 KHz 240 KHz 140 KHz 168 KHz Hysteresis Window 20 mV 20 mV 20 mV 20 mV 10 mV

†

Nominal frequency measured with Vo set to 2 V.

The values listed above are recommendations based on actual test circuits. Many variations of the above are possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not more, dependent upon the layout than on the specific components, as long as the device parameters are not exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the operating frequencies of typical power supplies are relatively low compared to today’s microprocessor circuits, the power levels and edge rates can cause severe problems both in the supply and the load. The power stage, having the highest current levels and greatest dv/dt rates, should be given the greatest attention.

Page 21

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

frequency calculation

A detailed derivation of frequency calculation is shown in the application report, “

Designing Fast Response

Synchronous Buck Regulators Using the TPS5210

”, TI Literature number SL VA044. When less accurate results

are acceptable, the simplified equation shown below can be used:

≅

VO ƪVI*

ESR

VI L

Hysteresis Window

Control Section

Below are the equations needed to select the various components within the control section. Details and the derivations of the equations used in this section are available in the application report “

Designing Fast Response

Synchronous Buck Regulators Using the TPS5210

”, TI Literature number SLVA044.

output voltage selection

Of course the most important function of the power supply is to regulate the output voltage to a specific value. V alues between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above the maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage within its range and selecting values for R2 and R3 to give the correct output. Select R3:

R3 << than V

REF/IBIAS(VSENSE)

; a recommended value is 10 kΩ

Then, calculate R2 using:

REF

)

R2 R3

VO*

REF

R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range and/or to adjust for load-current active droop compensation. If there is no need to adjust the output voltage, R3 can be eliminated. R2, R3 (if used), and C7 are used as a noise filter; calculate using:

150 ns

R2øR3

slowstart timing

Slowstart reduces the startup stresses on the power-stage components and reduces the input current surge. Slowstart timing is a function of the reference-voltage current (determined by R6) and is independent of the reference voltage. The first step in setting slowstart timing will be to determine R6:

R6 should be between 7 kΩ and 300 kΩ, a recommended value is 20 kΩ.

Set the slowstart timing using the formula:

5 R

VREFB

≅

(

5 R6

)

Where C5 = Slowstart capacitance in µF

= Slowstart timing in µs

VREFB

= Resistance from VREFB to GND in ohms (≈ R6)

Page 22

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

hysteresis voltage

A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the output which the input comparator uses for sensing. Once selected, the TPS5210 hysteresis is proportional to the reference voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same percentage of Vref. The actual output ripple voltage is the combination of the hysteresis voltage, overshoot caused by internal delays, and the output capacitor characteristics. Figure 20 shows the hysteresis window voltage (V

to VLO)

and the output voltage ripple (V

MAX

to V

MIN

). Since the output current from VREFB should be less than 500 µA, the total divider resistance (R5 + R6) should be greater than 7 KΩ. The hysteresis voltage should be no greater than 60 mV so R6 will dominate the divider.

VHSYT

VREFB

Hysteresis Window = 2 × V

Figure 19. Hysteresis Divider Circuit

MAX

MIN

REF

Figure 20. Output Ripple

The upper divider resistor, R5, is calculated using:

()

1002

WindowHysteresisVREFB

WindowHysteresis

HYST

≅×

–×

Where Hysteresis Window = the desired peak-to-peak hysteresis voltage.

VREFB = selected reference voltage. V

HYST

(%) = [(Hysteresis Window)/VREFB] * 100 < V

O(Ripple)(P–P)

(%)

Page 23

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

current limit

Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. Select R8:

()

Ω≤

≤<<

OCPBias

OCP

10 k

100100

1.0

)(

(A recommended value is 1 kΩ)

The IOUT signal is used to drive the current limit and droop-circuit dividers. The voltage at IOUT at the output current trip point will be:

()

NumFETs

TripO

ONDS

TripIOUT

)(

××

Where NumFETS = Number of upper FETS in Parallel.

TF = R

DS(ON)

temperature correction factor.

O(Trip)

= Desired output current trip level (A).

Calculate R7 using:

IOUT(Trip)

0.1 V

1Ǔ

Note that since R

DS(ON)

of MOSFET s can vary from lot to lot and with temperature, tight current-limit control (less

than 1.5 x I

) using this method is not practical. If tight control is required, an external current-sense resistor in series with the drain of the upper FET can be used with HISENSE and LOSENSE connected across the resistor.

droop compensation

Droop compensation is used to reduce the output voltage range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. This allows the output voltage to swing a greater amount and still remain within the tolerance window. The maximum droop voltage is set with R9 and R10. Select R10:

()

Ω≤

≤<<

MaxDROOPBias

MinDROOP

1 k

100100

01.0

),(

)(

(Again, a value of 1 kΩ is recommended)

The voltage at IOUT during normal operation (0 to 100% load) will vary from 0 V up to:

()

NumFETs

MaxO

ONDS

MaxIOUT

)(

××

Where I

O(Max)

= Maximum output load current (A).

Page 24

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

droop compensation (continued)

Then, calculate R9:

IOUT(Max)

DROOP

1Ǔ

R10

Where V

DROOP

= Desired droop voltage

At full load, the output voltage will be:

REF

ǒ1

)

R2 R3

DROOP

using the TPS5210 when both 12 V and 5 V are available

When both 12 V and 5 V are available, several components can be removed from the basic schematic shown above. R1, R4, and C9 are no longer required if 5 V is brought in directly to INHIBIT and LODRV. However, if undervoltage lockout for the 5-V input is desired, R1 and R4 can be used to set the startup setpoint. The INHIBIT pin trip level is 2.1 V. Select R4:

()

Ω≤

≤<<

MaxINH

INH

210

100100

1.2

)(

Then, set the 5-V UVLO trip level with R1:

()

Trip

–

INHIBIT

LODRV

Figure 21. 5-V Input with UVLO

using the TPS5210 when only 5 V is available

The TPS5210 controller requires 12 V for internal control of the device. If an external source for 12 V is not available, a small on-board source must be included in the design. Total 12-V current is very small, typically about 20 mA, so even a small charge pump can be used to generate the supply voltage. The power stage is not voltage dependent, but component values must be selected for 5-V inputs and the frequency of operation is dependent upon the power stage input voltage.

Page 25

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

11.0 k

10.0 k

ENABLE

12-V Boost Circuit

LODRV

LOHIB

DRVGND

LOWDR

DRV

BOOT

HIGHDR

BOOTLO

HISENSE

VCC

VID4

VID3

VID2

VID1

VID0

INHIBIT

PWRGD

IOUT

BIAS

OCP

VHYST

VSENSE

VREFB

ANAGND

SLOWST

DROOP

LOSENSE

IOUTLO

TPS5210

0.033 uF

0.1 uF

1 uF

2200 pF

12 V

GND

Control Section

Power Stage

R101

Q101

L101

C103C102

C101

Q102

RTN

C105

C106

L102

R102

C104

R10

1.00 k

4.32 k

1.00 k

3.92 k

20.0 k

100

10.0 kR3

1000 pF

0.1 uF

1 uF

150

1 uF

HIGHDRV

HISENSE

LOSENSE

BOOTLO

DRVGND

LOHIB

LODRV

VSENSE

RTN

Figure 22. Typical 5-V-Only Application Circuit

application examples

Various application and layout examples using the TPS5210 are available from Texas Instruments. This information can be downloaded from

http://www.ti.com/sc/docs/products/msp/pwrsply/default.htm

or received

from your TI representative.

Page 26

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

layout guidelines

Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB design. The general design should proceed from the switching node to the output, then back to the driver section, and, finally, place the low-level components. Below are several specific points to consider

before

layout of a TPS5210 design begins.

1. All sensitive analog components should be referenced to ANAGND. These include components connected to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB.

2. Analog ground and drive ground should be isolated as much as possible. Ideally , analog ground will connect to the ground side of the bulk storage capacitors on V

, and drive ground will connect to the main ground

plane close to the source of the low-side FET.

3. Connections from the drivers to the gate of the power FETs, should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used.

4. The bypass capacitor for the DRV regulator should be placed close to the TPS5210 and be connected to DRVGND.

5. The bypass capacitor for V

should be placed close to the TPS5210 and be connected to DRVGND.

6. When configuring the high-side driver as a floating driver , the connection from BOOTLO to the power FET s should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB and LOSENSE, should have a separate connection to the FETS since BOOTLO will have large peak currents flowing through it.

7. When configuring the high-side driver as a floating driver , the bootstrap capacitor (connected from BOOT to BOOTLO) should be placed close to the TPS5210.

8. When configuring the high-side driver as a ground-referenced driver, BOOTLO should be connected to DRVGND.

9. The bulk storage capacitors across V

should be placed close to the power FETS. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and to the source of the low-side FET.

10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on V

11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.

Page 27

TPS5210

PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

4040000/C 07/96

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

Page 28

TPS5210 PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER

SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

4073225/E 03/97

0,50

0,75

0,25

0,15 NOM

Thermal Pad (See Note D)

Gage Plane

2824

7,70

7,90

6,40

6,60

9,60

9,80

6,60 6,20

0,19

4,50 4,30

0,15

0,30

1,20 MAX

1614

5,10

4,90

PINS **

4,90

5,10

DIM

A MIN

A MAX

0,05

Seating Plane

0,65

0,10

0°–8°

20-PIN SHOWN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments Incorporated.

Page 29

IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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