Datasheet tps51275 Datasheet (Texas Instruments)

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Page 1

TPS51275, TPS51275B, TPS51275C

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SLUSB45B –JUNE 2012–REVISED MARCH 2013

Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs

FEATURES

• Input Voltage Range: 5 V to 24 V

• Output Voltages: 5 V and 3.3 V (Adjustable • Tablet Computers Range ±10%)

• Built-in, 100-mA, 5-V and 3.3-V LDOs

• Clock Output for Charge-Pump

• ±1% Reference Accuracy

• Adaptive On-Time D-CAP™ Mode Control Architecture with 300-kHz and 355-kHz Frequency Setting

• Auto-skip Light Load Operation (TPS51275, and TPS51275C)

• OOA Light Load Operation (TPS51275B)

• Internal 0.8-ms Voltage Servo Soft-Start

• Low-Side R

• Built-In Output Discharge Function

• Separate Enable Input for Switchers

• Dedicated OC Setting Terminals

• Power Good Indicator

• OVP, UVP and OCP Protection

• Non-Latch UVLO and OTP Protection

• 20-Pin, 3 mm x 3 mm, QFN (RUK)

ORDERABLE ENABLE

DEVICE NUMBER FUNCTION

TPS51275RUKR Tape and Reel 3000 TPS51275RUKT Mini reel 250

TPS51275BRUKR Tape and Reel 3000 TPS51275BRUKT Mini reel 250

TPS51275CRUKR Tape and Reel 3000

TPS51275CRUKT Mini reel 250

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Current Sensing Scheme

DS(on)

EN1 and EN2 OOA

NEED SOME SPACE

ORDERING INFORMATION

SKIP MODE ALWAYS On-LDO PACKAGE QUANTITY

Auto-skip VREG3

VREG3 and VREG5

Auto-skip

APPLICATIONS

• Notebook Computers

DESCRIPTION

The TPS51275, TPS51275B and TPS51275C are cost-effective, dual-synchronous buck controllers targeted for notebook system-power supply solutions. It provides 5-V and 3.3-V LDOs and requires few external components. The 260-kHz VCLK output can be used to drive an external charge pump, generating gate drive voltage for the load switches without reducing the main converter efficiency. The TPS51275, TPS51275B and TPS51275C supports high efficiency, fast transient response and provides a combined power-good signal. Adaptive on-time, DCAP™ control provides convenient and efficient operation. The device operates with supply input voltage ranging from 5 V to 24 V and supports output voltages of 5.0 V and 3.3 V. The TPS51275, TPS51275B and TPS51275C are available in a 20pin, 3 mm x 3 mm, QFN package and is specified from –40°C to 85°C.

(1)

OUTPUT SUPPLY

PLASTIC Quad

Flat Pack

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Page 2

VIN

VBST1

TPS51275B/C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN-5V

VCLK

VREG5

OUT

5 V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-12091

1 mF

5 V Always ON

1 mF

VIN

VBST1

TPS51275

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN-5V

VCLK

VREG5

OUT

5 V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-12090

1 mF

5 V

1 mF

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

TYPICAL APPLICATION DIAGRAM (TPS51275)

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TYPICAL APPLICATION DIAGRAM (TPS51275B and TPS51275C)

Page 3

TPS51275, TPS51275B, TPS51275C

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ABSOLUTE MAXIMUM RATINGS

(1)

SLUSB45B –JUNE 2012–REVISED MARCH 2013

over operating free-air temperature range (unless otherwise noted)

VALUE

MIN MAX

VBST1, VBST2 –0.3 32 VBST1, VBST2

(3)

–0.3 6

SW1, SW2 –6.0 26

Input voltage

(2)

VIN –0.3 26 V EN1, EN2 –0.3 6 VFB1, VFB2 –0.3 3.6 VO1 –0.3 6 DRVH1, DRVH2 –6.0 32

(3) (3)

(pulse width < 20 ns) –2.5 6

–0.3 6

Output voltage

DRVH1, DRVH2 DRVH1, DRVH2

(2)

DRVL1, DRVL2 –0.3 6 V DRVL1, DRVL2 (pulse width < 20 ns) –2.5 6 PGOOD, VCLK, VREG5 –0.3 6 VREG3, CS1, CS2 –0.3 3.6

Electrostatic discharge kV

Junction temperature, T Storage temperature, T

HBM QSS 009-105 (JESD22-A114A) 2 CDM QSS 009-147 (JESD22-C101B.01) 1

150 °C –55 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted (3) Voltage values are with respect to SW terminals.

UNIT

THERMAL INFORMATION

TPS51275

(1)

JA JCtop JB

JT JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 94.1 Junction-to-case (top) thermal resistance 58.1 Junction-to-board thermal resistance 64.3 Junction-to-top characterization parameter 31.8 Junction-to-board characterization parameter 58.0 Junction-to-case (bottom) thermal resistance 5.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS51275B TPS51275C

20-PIN RUK

UNITS

°C/W

Page 4

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Supply voltage VIN 5 24

VBST1, VBST2 –0.1 30 VBST1, VBST2 SW1, SW2 –5.5 24 V

Input voltage

(1)

EN1, EN2 –0.1 5.5 VFB1, VFB2 –0.1 3.5 VO1 –0.1 5.5 DRVH1, DRVH2 –5.5 30 DRVH1, DRVH2

Output voltage

(1)

DRVL1, DRVL2 –0.1 5.5 V PGOOD, VCLK, VREG5 –0.1 5.5 VREG3, CS1, CS2 –0.1 3.5

Operating free-air temperature, T

(1) All voltage values are with respect to the network ground terminal unless otherwise noted. (2) Voltage values are with respect to the SW terminal.

(2)

–0.1 5.5

–40 85 °C

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Page 5

TPS51275, TPS51275B, TPS51275C

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENT

VIN1

VIN2

VO1

VIN(STBY)

INTERNAL REFERENCE

FBx

VREG5 OUTPUT

VREG5

V5SW

VREG3 OUTPUT

VREG3

DUTY CYCLE and FREQUENCY CONTROL

sw1

SW2

OFF(MIN)

MOSFET DRIVERS

DRVH

DRVL

INTERNAL BOOT STRAP SWITCH

VBST (ON)

VBSTLK

CLOCK OUTPUT

VCLK (PU)

VCLK (PD)

CLK

(1) Ensured by design. Not production tested.

VIN supply current-1 TA= 25°C, No load, V VIN supply current-2 TA= 25°C, No load 30 μA VO1 supply current TA= 25°C, No load, V VIN stand-by current TPS51275 TA= 25°C, No load, V

VIN stand-by current 180 μA

VFB regulation voltage

VREG5 output voltage V

VREG5 current limit V 5-V switch resistance TA= 25°C, V

VREG3 output voltage V

VREG3 current limit V

CH1 frequency CH2 frequency

(1) (1)

Minimum off-time TA= 25°C 200 300 500 ns

DRVH resistance Ω

DRVL resistance Ω

Dead time ns

Boost switch on-resistance TA= 25°C, I VBST leakage current TA= 25°C 1 µA

VCLK on-resistance (pull-up) TA= 25°C 10 VCLK on-resistance (pull-down) TA= 25°C 10 Clock frequency TA= 25°C 260 kHz

SLUSB45B –JUNE 2012–REVISED MARCH 2013

= 12 V, V

VIN

TA= 25°C, No load, V TPS51275B/C)

= 5 V, V

VO1

= V

VFB1

=0 V 860 μA

VO1

= V

VFB1

= 0 V, V

VO1

=0 V, V

VO1

= 2 V, V

VFB2

=2.05 V 900 μA

VFB2

= V

EN1

EN2

=0V (

EN1=VEN2

= V

EN1

= 3.3 V (unless otherwise

EN2

= 0 V 95 μA

TA= 25°C 1.99 2.00 2.01 V

1.98 2.00 2.02 V

TA= 25°C, No load, V V

> 7 V , V

VIN

VIN VO1

No load, V V

VIN

5.5 V < V

VO1

> 5.5 V , V > 5 V, V

VO1

= 0 V, V

VREG5 VO1

= 0 V, TA= 25°C 3.267 3.300 3.333

VO1

> 7 V , V

VO1

, V

VIN

0°C ≤ TA≤ 85°C, V I

< 35 mA

VREG3

0°C ≤ TA≤ 85°C, V I

< 35 mA

VREG3

> 5 V, V

VIN VO1

TA= 25°C, V TA= 25°C, V

Source, (V Sink, (V Source, (V Sink, V

VO1

= 0 V, V

VREG3

VIN VIN

VBST

– VSW) = 0.25 V, (V

DRVH

VREG5

= 0.25 V, V

DRVL

= 0 V 4.9 5.0 5.1

VO1

= 0 V, I

VO1

= 0 V, I

= 4.5 V, V

= 5 V, I

= 0 V, I

VO1

VIN

= 0 V, I

= 3.0 V, V

< 100 mA 4.85 5.00 5.10

VREG5

< 35 mA 4.85 5.00 5.10

VREG5

< 20 mA 4.50 4.75 5.10

VREG5

= 7 V 100 150 mA

VIN

= 50 mA 1.8 Ω

VREG5

< 100 mA 3.217 3.300 3.383

VREG3

< 35 mA 3.234 3.300 3.366

VREG3

> 5.5 V, V

VREG3

= 0 V,

VO1

= 5 V,

3.267 3.300 3.333

< 35 mA 3.217 3.300 3.366

= 7 V 100 150 mA

VIN

= 20 V 240 300 360 kHz = 20 V 280 355 430 kHz

– V

DRVH

DRVL

) = 0.25 V, (V

) = 0.25 V, V

= 5 V 0.9

VREG5

– VSW) = 5 V 3.0

VBST

– VSW) = 5 V 1.9

VBST

= 5 V 3.0

VREG5

DRVH-off to DRVL-on 12 DRVL-off to DRVH-on 20

= 10 mA 13 Ω

VBST

Page 6

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

OUTPUT DISCHARGE

DIS1

DIS2

SOFT START OPERATION

SSRAMP

POWER GOOD

PGTH

PGMAX

PGLK

PGDEL

CURRENT SENSING

LOGIC THRESHOLD

ENX(ON)

ENX(OFF)

OUTPUT OVERVOLTAGE PROTECTION

OVP

OVPDLY

OUTPUT UNDERVOLTAGE PROTECTION

UVP

UVPDLY

UVPENDLY

UVLO

UVL0VIN

UVLO5

UVLO3

OVER TEMPERATURE PROTECTION

OTP

CH1 discharge resistance 35 Ω CH2 discharge resistance TPS51275 TA= 25°C, V CH2 discharge resistance 70 Ω

Soft-start time From ENx="Hi" and V Soft-start time (ramp-up) V

PG threshold

PG sink current V PG leak current V PG delay From PG lower threshold (95%=typ) to PG flag high 0.7 ms

CS source current TA= 25°C, VCS= 0.4 V 9 10 11 μA CS current temperature coefficient

(1)

CS Current limit setting range 0.2 2 V Zero cross detection offset TA= 25°C –1 1 3 mV

EN threshold high-level SMPS on level 1.6 V EN threshold low-level SMPS off level 0.3 V EN input current V

OVP trip threshold 112.5% 115.0% 117.5% OVP propagation delay TA= 25°C 0.5 µs

UVP trip Threshold 55% 60% 65% UVP prop delay 250 µs UVP enable delay From ENx ="Hi", V

VIN UVLO Threshold

VREG5 UVLO Threshold

VREG3 UVLO Threshold

OTP threshold

(1)

= 12 V, V

VIN

TA= 25°C, V V

EN1

TA= 25°C, V (TPS51275B/C)

OUT

= 5 V, V

VO1

= V

EN2

= 0% to V

VO1

= 0 V

SW2 SW2

OUT

VFB1

= 0.5 V

= 0.5 V, V = 0.5 V, V

VREG5

= 95%, V

= V

= 2 V, V

VFB2

= V

EN1 EN1

> V

= 0 V 75 Ω

EN2

= V

= 0 V

EN2

to V

UVLO5

VREG5

OUT

= 5 V 0.78 ms

= V

EN1

= 3.3 V (unless otherwise

EN2

= 95% 0.91 ms

Lower (rising edge of PG-in) 92.5% 95.0% 97.5% Hysteresis 5% Upper (rising edge of PG-out) 107.5% 110.0% 112.5% Hysteresis 5%

= 0.5 V 6.5 mA

PGOOD

= 5.5 V 1 µA

PGOOD

On the basis of 25°C 4500 ppm/°C

= 3.3 V –1 1 µA

ENx

= 5 V 1.35 ms

VREG5

Wake up 4.58 V Hysteresis 0.5 V Wake up 4.38 4.50 V Hysteresis 0.4 V Wake up 3.15 V Hysteresis 0.15 V

Shutdown temperature 155 Hysteresis 10

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°C

(1) Ensured by design. Not production tested.

Page 7

8 9

1819

TPS51275

TPS51275B

Thermal Pad

TPS51275C

CS1

VFB1

VREG3

VFB2

CS2

EN2

SW2

VBST2

DRVH2

DRVL2

VIN

VREG5

VO1

DRVL1

DRVH1

VBST1

SW1

VCLK

EN1

TPS51275, TPS51275B, TPS51275C

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SLUSB45B –JUNE 2012–REVISED MARCH 2013

DEVICE INFORMATION

RUK PACKAGE

20 PINS

(TOP VIEW)

PIN FUNCTIONS

PIN NO.

TPS51275 TPS51275B TPS51275C

Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal.

Voltage feedback Input

Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of channel 1 and channel 2.

NAME I/O DESCRIPTION

CS1 1 O Sets the channel 1 OCL trip level. CS2 5 O Sets the channel 2OCL trip level. DRVH1 16 O High-side driver output DRVH2 10 O High-side driver output DRVL1 15 O Low-side driver output DRVL2 11 O Low-side driver output EN1 20 I Channel 1 enable. EN2 6 I Channel 2 enable. PGOOD 7 O Power good output flag. Open drain output. Pull up to external rail via a resistor SW1 18 O Switch-node connection. SW2 8 O Switch-node connection. VBST1 17 I VBST2 9 I VCLK 19 O Clock output for charge pump. VFB1 2 I VFB2 4 I

VIN 12 I VO1 14 I Output voltage input, 5-V input for switch-over.

VREG3 3 O 3.3-V LDO output. VREG5 13 O 5-V LDO output. Thermal pad GND terminal, solder to the ground plane

Page 8

VIN

VBST1

TPS51275 TPS51275 B TPS51275 C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1

VCLK

VREG5

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

UDG-12092

+ +

155°C/145°C

4.5 V/4.0 V

VO_OK

FAULT

REF

PGOOD

DCHG

VIN VDDVDRV

GNDPGND

Switcher

Controller

(CH1)

FAULT

REF

PGOOD

DCHG

VINVDD VDRV

GND PGND

Switcher

Controller

(CH2)

2 V

Osc

GND

(Thermal Pad)

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

FUNCTIONAL BLOCK DIAGRAM (TPS51275/B/C)

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Page 9

DCHG

TPS51275 TPS51275 B

NOC

XCON

VO_OK

DRVL

PWM

Control Logic

UDG-12093

REF

+15%

SKIP

REF

–40%

VIN

GND

REF

One-Shot

Discharge

10 µA

VBST

DRVH

FAULT

PGOOD

VFB

SS Ramp Comp

REF

+5%/10 %

REF

–5%/10%

VDD

VDRV

PGND

PGOOD

TPS51275 C

TPS51275, TPS51275B, TPS51275C

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SWITCHER CONTROLLER BLOCK DIAGRAM

SLUSB45B –JUNE 2012–REVISED MARCH 2013

Page 10

( )

- ´

= ´

´ ´

IN OUT OUT

OUT LL

SW IN

V V V

2 L f V

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

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DETAILED DESCRIPTION

PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external conpensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This MOSFET is turned off, or enters the ‘OFF state, after the internal, one-shot timer expires. The MOSFET is turned on again when the feedback point voltage, V

, decreased to match the internal 2-V reference. The inductor

VFB

current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side (rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss. The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation during light-load conditions so that high efficiency is maintained over a broad range of load current.

Adaptive On-Time/ PWM Frequency Control

Because the TPS51275/B/C does not have a dedicated oscillator for control loop on board, switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching frequency is varied according to the input voltage to achieve higher duty operation for lower input voltage application. The switching frequency of CH1 (5-V output) is 300 kHz during continuous conduction mode (CCM) operation when VIN= 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VIN= 20 V. (See Figure 27 and Figure 28).

To improve load transient performance and load regulation in lower input voltage conditions, TPS51275/B/C can extend the on-time. The maximum on-time extension of CH1 is 4 times for CH2 is 3 times. To maintain a reasonable inductor ripple current during on-time extension, the inductor ripple current should be set to less than half of the OCL (valley) threshold. (See Step 2. Choose the Inductor). The on-time extension function provides high duty cycle operation and shows better DC (static) performance. AC performance is determined mostly by the output LC filter and resistive factor in the loop.

Light Load Condition in Auto-Skip Operation (TPS51275/C)

The TPS51275/C automatically reduces switching frequency during light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A more detailed description of this operation is as follows. As the output current decreases from heavy-load condition, the inductor current is also reduced and eventually approaches valley zero current, which is the boundary between continuous conduction mode and discontinuous conduction mode. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires the next ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse, when the output current increase from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation I

OUT(LL)

as shown in Equation 1.

where

• fSWis the PWM switching frequency (1)

Switching frequency versus output current during light-load conditions is a function of inductance (L), input voltage (VIN) and output voltage (V I

OUT(LL)

(i.e. the threshold between continuous and discontinuous conduction mode) can be calculated

), but it decreases almost proportional to the output current from the

OUT

Page 11

= £

p ´ ´

OUT

2 ESR C 4

Voltage

Divider

VFB

VREF

PWM

Control

Logic

and

Divider

ESR

OUT

LOAD

IND

OUT

UDG-1211 1

Switching Modulator

Output

Capacitor

OUT

TPS51275 TPS51275B TPS51275C

DRVH

DRVL

TPS51275, TPS51275B, TPS51275C

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SLUSB45B –JUNE 2012–REVISED MARCH 2013

Light-Load Condition in Out-of-Audio™ Operation (TPS51275B)

Out-of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward a virtual no-load condition. During Out-of-Audio™ operation, the OOA control circuit monitors the states of both high-side and low-side MOSFETs and forces them switching if both MOSFETs are off for more than 40 µs. When both high-side and low-side MOSFETs are off for 40 µs during a light-load condition, the operation mode is changed to FCCM. This mode change initiates one cycle of the lowside MOSFET and the high-side MOSFET turning on. Then, both MOSFETs stay turned off waiting for another 40 µs.

Table 1. SKIP Mode Operation (TPS51275/B/C)

SKIP MODE OPERATION

TPS51275 Auto-skip TPS51275B OOA TPS51275C Auto-skip

D-CAP™ Mode

From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 1.

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each ON cycle substantially constant. For the loop stability, the 0dB frequency, ƒ0, defined in Equation 2 must be lower than 1/4 of the switching frequency.

As ƒ0is determined solely by the output capacitor characteristics, the loop stability during D-CAP™ mode is determined by the capacitor chemistry. For example, specialty polymer capacitors have output capacitance in the order of several hundred micro-Farads and ESR in range of 10 milli-ohms. These yield an f0value on the order of 100 kHz or less and the loop is stable. However, ceramic capacitors have ƒ0at more than 700 kHz, which is not suitable for this operational mode.

Figure 1. Simplifying the Modulator

(2)

Page 12

VIN-UVLO_threshold

EN_threshold

95% of V

OUT

95% of Vout

EN_threshold

VIN

VREG3

EN1

VREG5

5-V V

OUT

PGOOD

EN2

Soft-Start Time (tSS)

Soft-Start Time

SS(ramp)

)

Soft-Start Time (tSS)

Soft-Start Time

SS(ramp)

)

PGOOD

Delay t

PGDEL

3.3-V V

OUT

UDG-12013

VREG5-UVLO_threshold

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

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Enable and Powergood

VREG3 is an always-on regulator (TPS51275), VREG3/VREG5 are always-on regulators (TPS51275B/C), when the input voltage is beyond the UVLO threshold it turns ON. VREG5 is turned ON when either EN1 or EN2 enters the ON state (TPS51275). The VCLK signal initiates when EN1 enters the ON state (TPS51275/B/C). Enable states are shown in Table 2 through Table 3.

Table 2. Enabling/PGOOD State (TPS51275)

EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD

OFF OFF OFF ON OFF OFF OFF Low

ON OFF ON ON ON OFF ON Low

OFF ON ON ON OFF ON OFF Low

ON ON ON ON ON ON ON High

Table 3. Enabling/PGOOD State (TPS51275B/C)

EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD

OFF OFF ON ON OFF OFF OFF Low

ON OFF ON ON ON OFF ON Low

OFF ON ON ON OFF ON OFF Low

ON ON ON ON ON ON ON High

Figure 2. TPS51275 Timing

Page 13

VIN-UVLO_threshold

95% of V

OUT

95% of Vout

EN_threshold

VIN

VREG3

VREG5

5-V V

OUT

PGOOD

EN2

Soft-Start Time (tSS)

Soft-Start Time

SS(ramp)

)

Soft-Start Time (tSS)

Soft-Start Time

SS(ramp)

)

PGOOD

Delay t

PGDEL

3.3-V V

OUT

UDG-12015

EN_threshold

EN1

2.4 V

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

Figure 3. TPS51275B/C Timing

Page 14

( )

( )IND ripple

IN OUT OUT

TRIP TRIP

OCP

SW IN

DS on DS on

V V V

V V

R 2 R 2 L f V

- ´

= + = + ´

´ ´

CS CS

TRIP

R I

V 1 mV

= +

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

www.ti.com

Soft-Start and Discharge

The TPS51275/B/C operates an internal, 0.8-ms, voltage servo soft-start for each channel. When the ENx pin becomes higher than the enable threshold voltage, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start-up. When ENx becomes lower than the lower level of threshold voltage, TPS51275/B/C discharges outputs using internal MOSFETs through VO1 (CH1) and SW2 (CH2).

VREG5/VREG3 Linear Regulators

There are two sets of 100-mA standby linear regulators which output 5 V and 3.3 V, respectively. The VREG5 pin provides the current for the gate drivers. The VREG3 pin functions as the main power supply for the analog circuitry of the device. VREG3 is an Always ON LDO and TPS51275B/C has Always ON VREG5. (See Table 2 and Table 3)

Add ceramic capacitors with a value of 1 µF or larger (X5R grade or better) placed close to the VREG5 and VREG3 pins to stabilize LDOs.

The VREG5 pin switchover function is asserted when three conditions are present:

• CH1 internal PGOOD is high

• CH1 is not in OCL condition

• VO1 voltage is higher than VREG5-1V In this switchover condition three things occur:

• the internal 5-V LDO regulator is shut off

• the VREG5 output is connected to VO1 by internal switchover MOSFET

• VREG3 input pass is changed from VIN to VO1

VCLK for Charge Pump

The 260-kHz VCLK signal can be used in the charge pump circuit. The VCLK signal becomes available when EN1 is on state. The VCLK driver is driven by VO1 voltage. In a design that does not require VCLK output, leave the VCLK pin open.

Overcurrent Protection

TPS51275/B/C has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS51275/B/C supports temperature compensated MOSFET R setting resistor, RCS. The CSx pin sources CS current (ICS) which is 10 µA typically at room temperature, and the CSx terminal voltage (VCS= RCS× ICS) should be in the range of 0.2 V to 2 V over all operation temperatures. 　The trip level is set to the OCL trip voltage (V

The inductor current is monitored by the voltage between GND pin and SWx pin so that SWx pin should be connected to the drain terminal of the low-side MOSFET properly.The CS pin current has a 4500 ppm/°C temperature slope to compensate the temperature dependency of the R current sensing node so that GND should be connected to the source terminal of the low-side MOSFET.

As the comparison is done during the OFF state, V current at the overcurrent threshold, I

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the undervoltage protection threshold and shutdown both channels.

sensing. The CSx pin should be connected to GND through the CS voltage

DS(on)

) as shown in Equation 3.

TRIP

. GND is used as the positive

DS(on)

sets the valley level of the inductor current. Thus, the load

, can be calculated as shown in Equation 4.

OCP

TRIP

(3)

(4)

Page 15

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

Output Overvoltage/Undervoltage Protection

TPS51275/B/C asserts the overvoltage protection (OVP) when VFBx voltage reaches OVP trip threshold level. When an OVP event is detected, the controller changes the output target voltage to 0 V. This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on. After the on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the output node undershoot due to LC resonance. When the VFBx reaches 0V, the driver output is latched as DRVH off, DRVL on. The undervoltage protection (UVP) latch is set when the VFBx voltage remains lower than UVP trip threshold voltage for 250 µs or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the outputs. UVP detection function is enabled after 1.35 ms of SMPS operation to ensure startup.

Undervoltage Lockout (UVLO) Protection

TPS51275/B/C has undervoltage lock out protection at VIN, VREG5 and VREG3. When each voltage is lower than their UVLO threshold voltage, both SMPS are shut-off. They are non-latch protections.

Over-Temperature Protection

TPS51275/B/C features an internal temperature monitor. If the temperature exceeds the threshold value (typically 155°C), TPS51275/B/C is shut off including LDOs. This is non-latch protection.

Page 16

VOUT

REF

(2)

OFF

Slope (2)

Jitter

20 mV

Slope (1)

Jitter

UDG-12012

REF

+Noise

(1)

( )

OUT SW

IND ripple

V 20 mV (1 D) 20mV L f

ESR

2 V I 2 V

´ ´ - ´ ´

= =

( )

(

)

( )

IN OUT OUT

max

TRIP

IND peak

SW IN

DS on max

V V V

R L f V

- ´

= + ´

( )

(

)

( ) ( )

( )

(

)

- ´ - ´

= ´ = ´

´ ´

IN OUT OUT IN OUT OUT

max max

SW IN OUT SW IN(max)

IND ripple max max

V V V V V V

1 3

I f V I f V

( )

OUT RIPPLE

V 0.5 V 2.0

R1 R2

2.0

- ´ -

= ´

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

www.ti.com

External Components Selection

The external components selection is relatively simple for a design using D-CAP™ mode.

Step 1. Determine the Value of R1 and R2

The recommended R2 value is between 10 kΩ and 20 kΩ. Determine R1 using Equation 5.

(5)

Step 2. Choose the Inductor

The inductance value should be determined to give the ripple current of approximately 1/3 of maximum output current and less than half of OCL (valley) threshold. Larger ripple current increases output ripple voltage, improves signal/noise ratio, and helps ensure stable operation.

(6)

The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as shown in Equation 7.

(7)

Step 3. Choose Output Capacitor(s)

Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage. A quick approximation is as shown in Equation 8.

where

• D as the duty-cycle factor

• the required output ripple voltage slope is approximately 20 mV per tSW(switching period) in terms of VFB terminal (8)

Figure 4. Ripple Voltage Slope and Jitter Performance

Page 17

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

Layout Considerations

Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.

Placement

• Place voltage setting resistors close to the device pins.

• Place bypass capacitors for VREG5 and VREG3 close to the device pins.

Routing (Sensitive analog portion)

• Use small copper space for VFBx. There are short and narrow traces to avoid noise coupling.

• Connect VFB resistor trace to the positive node of the output capacitor. Routing inner layer away from power traces is recommended.

• Use short and wide trace from VFB resistor to vias to GND (internal GND plane).

Routing (Power portion)

• Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.

• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive in a same layer or on adjoin layers, and keep them away from DRVL.

• Use wider/ shorter traces between the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET

• Thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter connected from the thermal pad to the internal GND plane should be used to have strong GND connection and help heat dissipation.

Page 18

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

CS Source Current (µA)

G005

210

220

230

240

250

260

270

280

290

300

310

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

VCLK Frequency (kHz)

G006

100

125

150

175

200

225

250

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

VIN Stand−By Current (µA)

TPS51275 TPS51275B/C

G004

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

VO1 Supply Current 1 (mA)

G003

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

VIN Supply Current 1 (mA)

G001

−40 −25 −10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C)

VIN Supply Current 2 (µA)

G002

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS

Figure 5. VIN Supply Current 1 vs. Junction Temperature Figure 6. VIN Supply Current 2 vs. Junction Temperature

www.ti.com

Figure 7. VO1 Supply Current 1 vs. Junction Temperature Figure 8. VIN Stand-By Current vs. Junction Temperature

Figure 9. CS Source Current vs. Junction Temperature Figure 10. Clock Frequency vs. Junction Temperature

Page 19

100

0.001 0.01 0.1 1 10

Efficiency (%)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 14.8 V

V = 20 V

C002

Out-of-Audio V

VOUT2

= 3.3 V

100

0.001 0.01 0.1 1 10 Output Current (A)

Efficiency (%)

VIN

= 7.4 V

VIN

= 11.1 V

VIN

= 14.8 V

VIN

= 20 V

VOUT2

= 3.3 V

G000

Auto-Skip

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0.001 0.01 0.1 1 10

Output Voltage (V)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 14.8 V

V = 20 V

C003

Out-of-Audio V

VOUT1

= 5 V

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0.001 0.01 0.1 1 10 Output Current (A)

Output Volage (V)

VIN

= 7.4 V

VIN

= 11.1 V

VIN

= 14.8 V

VIN

= 20 V

VOUT1

= 5 V

G014

Auto-Skip

100

0.001 0.01 0.1 1 10

Efficiency (%)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 14.8 V

V = 20 V

Out-of-Audio V

VOUT1

= 5 V

C001

100

0.001 0.01 0.1 1 10 Output Current (A)

Efficiency (%)

VIN

= 7.4 V

VIN

= 11.1 V

VIN

= 14.8 V

VIN

= 20 V

VOUT1

= 5 V

G000

Auto-Skip

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS (continued)

Figure 11. Efficiency vs. Output Current Figure 12. Efficiency vs. Output Current

Figure 13. Load Regulation Figure 14. Load Regulation

Figure 15. Efficiency vs. Output Current Figure 16. Efficiency vs. Output Current

Page 20

100

150

200

250

300

350

400

450

500

0.001 0.01 0.1 1 10

Switching Frequency (kHz)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 20 V

C006

Out-of-Audio V

OUT2

= 3.3 V

100

150

200

250

300

350

400

450

0.001 0.01 0.1 1 10 Output Current (A)

Switching Frequency (kHz)

VIN

= 7.4 V

VIN

= 12.6 V

VIN

= 20 V

VOUT2

= 3.3 V

G000

Auto-Skip

100

150

200

250

300

350

400

450

500

0.001 0.01 0.1 1 10

Switching Frequency (kHz)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 20 V

C005

Out-of-Audio V

OUT1

= 5 V

100

150

200

250

300

350

0.001 0.01 0.1 1 10 Output Current (A)

Switching Frequency (kHz)

VIN

= 7.4 V

VIN

= 12.6 V

VIN

= 20 V

VOUT1

= 5 V

G000

Auto-Skip

3.20

3.25

3.30

3.35

3.40

0.001 0.01 0.1 1 10

Output Voltage (V)

Output Current (A)

V = 7.4 V

V = 11.1 V

V = 14.8 V

V = 20 V

C004

Out-of-Audio V

VOUT2

= 3.3 V

3.20

3.25

3.30

3.35

3.40

0.001 0.01 0.1 1 10 Output Current (A)

Output Volage (V)

VIN

= 7.4 V

VIN

= 11.1 V

VIN

= 14.8 V

VIN

= 20 V

VOUT2

= 3.3 V

G014

Auto-Skip

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS (continued)

Figure 17. Load Regulation Figure 18. Load Regulation

www.ti.com

Figure 19. Switching Frequency vs. Output Current Figure 20. Switching Frequency vs. Output Current

Figure 21. Switching Frequency vs. Output Current Figure 22. Switching Frequency vs. Output Current

Page 21

100

150

200

250

300

350

400

450

500

5 10 15 20 25

Input Voltage (V)

Switching Frequency (kHz)

OUT1

= 5 V

OUT1

= 6 A

G000

100

150

200

250

300

350

400

450

500

5 10 15 20 25

Input Voltage (V)

Switching Frequency (kHz)

OUT2

= 3.3 V

OUT2

= 6 A

G000

OUT1

(100 mV/div)

SW1 (10 V/div )

OUT2

( 100 mV/div )

Time (100 µs /div)

IND1

(5 A/div)

OUT1:

0 A ßà 3 A

OUT2

= 0 A

VIN

= 7 .4 V

Time (100 µs /div)

OUT1

(100 mV/div)

SW 2 (10 V /div)

OUT2

(100 mV/div)

IND2

(5 A/div)

OUT1

= 0 A

OUT2

: 0 A ßà 3 A

VIN

= 7 .4 V

OUT1

(2 V/div)

PGOOD (5 V/div)

OUT2

(2 V/div)

Time (400 µs/div)

EN1 = EN2 (5 V/div)

OUT1

(2 V/div)

EN1 = EN2 (5 V/div)

OUT2

(2 V/div)

PGOOD (5 V/div)

Time (10 ms/div)

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS (continued)

Figure 23. Start-Up Figure 24. Output Discharge

Figure 25. 5-V Load Transient Figure 26. 3.3-V Load Transient

Figure 27. Switching Frequency vs. Input Voltage Figure 28. Switching Frequency vs. Input Voltage

Page 22

VIN

VBST1

TPS51275

TPS51275 B

TPS51275 C

DRVH1

SW1

0.1 µF

15 kW

DRVL115

VO114

VFB12

CS11

EN1

30.9 k W

10 kW

EN 5V

0.1 µF

VCLK19

VREG513

10 µF x 2

OUT

5 V to 6 A

Charge-pump Output

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2 5

EN2

PGOOD

VREG3

10 µF x 2

0.1 µF

13 kW

33.2 kW

20 kW

EN 3.3 V

1 µF

OUT

3.3 V to 7A

PGOOD

VREG (3.3-V LDO)

UDG-12094

0.1 µF

GND

0.1 µF

VREG5 (5-V LDO)

1 µF

6.8 W 8.2 W

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

APPLICATION DIAGRAM (TPS51275/TPS51275B/TPS51275C)

www.ti.com

Table 4. Key External Components (APPLICATION DIAGRAM (TPS51275/TPS51275B/TPS51275C))

REFERENCE

DESIGNATOR

L1 Output Inductor (5-V L2 Output Inductor (3.3-V C1 Output Capacitor (5-V

C2 Output Capacitor (3.3-V Q1 MOSFET (5-V Q2 MOSFET (3.3-V

FUNCTION MANUFACTURER PART NUMBER

) Alps GLMC3R303A

OUT

) Alps GLMC2R203A

OUT

) SANYO 6TPE220MAZB x 2

OUT

) SANYO 6TPE220MAZB x 2

OUT

) TI CSD87330Q3D

OUT

) TI CSD87330Q3D

OUT

Page 23

TPS51275, TPS51275B, TPS51275C

www.ti.com

SLUSB45B –JUNE 2012–REVISED MARCH 2013

REVISION HISTORY

Changes from Original (JUNE 2011) to Revision A Page

• Changed typographical error in V

• Added V

specification in ELECTRICAL CHARACTERISTICS table ............................................................................ 5

VREG3

• Changed updated inductor values in APPLICATION DIAGRAM (TPS51275/TPS51275B/TPS51275C) and Table 4 ...... 22

Changes from Revision A (September 2012) to Revision B Page

• Changed revision date From A Septemer 2012 to B March 2013. Also added device TPS51275B to Part number .......... 1

• Added (TPS151275/B/C) to Auto-skip ListItem in the FEATURES ...................................................................................... 1

• Added new OOA ListItem to FEATURES ............................................................................................................................. 1

• Changed TPS51275/C TO TPS51275/B/C globally ............................................................................................................. 1

• Changed the ORDERING INFORMATION table. ................................................................................................................. 1

• Changed the device number from TPS51275C TO TPS51275B/C in the elec chara table 2 places .................................. 5

• Added TPS51275B to the PIN NO. column .......................................................................................................................... 7

• Added OOA section after the Auto-Skip section ................................................................................................................. 11

• Changed the APPLICATION DIAGRAM. ............................................................................................................................ 22

condition in ELECTRICAL CHARACTERISTICS table .......................................... 5

VREG3

Page 24

PACKAGE OPTION ADDENDUM

www.ti.com

15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status

HPA02239RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS

TPS51275BRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS

TPS51275BRUKT ACTIVE WQFN RUK 20 250 Green (RoHS

TPS51275CRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS

TPS51275CRUKT ACTIVE WQFN RUK 20 250 Green (RoHS

TPS51275RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS

TPS51275RUKT ACTIVE WQFN RUK 20 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51275

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1275B

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1275C

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51275

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Samples

Addendum-Page 1

Page 25

PACKAGE OPTION ADDENDUM

www.ti.com

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

15-Apr-2017

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

Page 26

PACKAGE MATERIALS INFORMATION

www.ti.com 19-May-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS51275BRUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS51275BRUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51275CRUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51275CRUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS51275RUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS51275RUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 27

PACKAGE MATERIALS INFORMATION

www.ti.com 19-May-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51275BRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51275BRUKT WQFN RUK 20 250 210.0 185.0 35.0 TPS51275CRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51275CRUKT WQFN RUK 20 250 210.0 185.0 35.0

TPS51275RUKR WQFN RUK 20 3000 367.0 367.0 35.0

TPS51275RUKT WQFN RUK 20 250 210.0 185.0 35.0

Pack Materials-Page 2

Page 28

Page 29

Page 30

Page 31

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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Datasheet tps51275 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION DIAGRAM (TPS51275)

TYPICAL APPLICATION DIAGRAM (TPS51275B and TPS51275C)

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM (TPS51275/B/C)

SWITCHER CONTROLLER BLOCK DIAGRAM

DETAILED DESCRIPTION

PWM Operations

Adaptive On-Time/ PWM Frequency Control

Light Load Condition in Auto-Skip Operation (TPS51275/C)

Light-Load Condition in Out-of-Audio™ Operation (TPS51275B)

D-CAP™ Mode

Enable and Powergood

Soft-Start and Discharge

VREG5/VREG3 Linear Regulators

VCLK for Charge Pump

Overcurrent Protection

Output Overvoltage/Undervoltage Protection

Undervoltage Lockout (UVLO) Protection

Over-Temperature Protection

External Components Selection

Step 1. Determine the Value of R1 and R2

Step 2. Choose the Inductor

Step 3. Choose Output Capacitor(s)

Layout Considerations

Placement

Routing (Sensitive analog portion)

Routing (Power portion)

TYPICAL CHARACTERISTICS

APPLICATION DIAGRAM (TPS51275/TPS51275B/TPS51275C)

REVISION HISTORY