Datasheet TPS51125A Datasheet (Texas Instruments)

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Page 1

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Dual-Synchronous, Step-Down Controller with Out-of-Audio™ Operation

and 100-mA LDOs for Notebook System Power

Check for Samples: TPS51125A

FEATURES

• Wide Input Voltage Range: 5.5 V to 28 V

• Output Voltage Range: 2 V to 5.5 V • I/O Supplies

• Built-in 100-mA 5-V/3.3-V LDO with Switches • System Power Supplies

• Built-in 1% 2-V Reference Output

• With/Without Out-of-Audio™ Mode Selectable Light Load and PWM only Operation

• Internal 1.6-ms Voltage Servo Softstart

• Adaptive On-Time Control Architecture with Four Selectable Frequency Setting

• 4500 ppm/°C R

• Built-In Output Discharge

• Power Good Output

• Built-in OVP/UVP/OCP

• Thermal Shutdown (Non-latch)

• QFN24 (RGE)

Current Sensing

DS(on)

APPLICATIONS

• Notebook Computers

DESCRIPTION

The TPS51125A is a cost effective, dual-synchronous buck controller targeted for notebook system power supply solutions. It provides 5-V and 3.3-V LDOs and requires few external components. The 270-kHz VCLK output can be used to drive an external charge pump, generating gate drive voltage for the load switches without reducing the main converter’s efficiency. The TPS51125A supports high efficiency, fast transient response and provides a combined power-good signal. Out-of-Audio™ mode light-load operation enables low acoustic noise at much higher efficiency than conventional forced PWM operation. Adaptive on-time D-CAP™ control provides convenient and efficient operation. The part operates with supply input voltages ranging from 5.5 V to 28 V and supports output voltages from 2 V to 5.5 V. The TPS51125A is available in a 24-pin QFN package and is specified from -40°C to 85°C ambient temperature range.

Table 1. Differences between the TPS51125 and TPS51125A

LDO Output Capacitance Requirement

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Out-of-Audio, D-CAP are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1 µF acceptable at no load) (1 µF acceptable at no load)

TPS51125 TPS51125A

VREG5: at least 33 µF VREG5: 10 µF or larger (X5R or X7R) VREG3: at most 10 µF VREG3: 10 µF or larger (X5R or X7R)

VREF: 0.22 µF to 1 µF VREF: 0.22 µF to 1 µF (X5R or X7R)

Page 2

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

ORDERING INFORMATION

-40°C to 85°C 24

PACKAGE DEVICE NUMBER PINS OUTPUT SUPPLY ECO PLAN

Plastic Quad Flat Green (RoHS and no

Pack (QFN) Sb/Br)

TPS51125ARGET 250

TPS51125ARGER 3000

(1)(2)

MINIMUM

QUANTITY

Tape and reel

(small)

Tape and reel

(large)

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(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER UNIT

VBST1, VBST2 –0.3 36 VIN –0.3 30 LL1, LL2 -2.0 30

Input voltage range

(1)

LL1, LL2, pulse width < 20 ns -5.0 30 VBST1, VBST2

(2)

EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL –0.3 6 DRVH1, DRVH2 -1.0 36

Output voltage range

(1)

DRVH1, DRVH2

(2)

PGOOD, VCLK, VREG3, VREG5, VREF, DRVL1, DRVL2 –0.3 6

Electrostatic discharge kV

stg

Human body model (HBM) QSS 009-105 (JESD22-A114A) 2 Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) 1.5 Junction temperature range –40 125 Storage temperature –55 150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage values are with respect to the corresponding LLx terminal.

VALUE

MIN MAX

–0.3 6 V

–0.3 6

°C

DISSIPATION RATINGS

2-oz. trace and copper pad with solder.

PACKAGE TA< 25°C POWER RATING TA= 85°C POWER RATING

24 pin RGE

(1)

1.85 W 18.5 mW/°C 0.74 W

DERATING FACTOR ABOVE T

= 25°C

(1) Enhanced thermal conductance by 3x3 thermal vias beneath thermal pad.

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TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

Supply voltage VIN 5.5 28

VBST1, VBST2 -0.1 34

Input voltage range

Output voltage range LL1, LL2 -1.8 28

VBST1, VBST2 (wrt LLx) -0.1 5.5 EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2,

TONSEL, SKIPSEL DRVH1, DRVH2 -0.8 34 DRVH1, DRVH2 (wrt LLx) -0.1 5.5

VREF, VREG3, VREG5 -0.1 5.5 PGOOD, VCLK, DRVL1, DRVL2 -0.1 5.5 Operating free-air temperature -40 85 °C

-0.1 5.5 V

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TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

VIN1

VIN2

VO1

VO2

VINSTBY

VINSDN

VIN supply current1 = 0 V, EN0=open, ENTRIPx = 5 V, 0.55 1 mA

VIN supply current2 3.3 V, EN0=open, ENTRIPx = 5 V, 4 6.5 μA

VO1 current = 3.3 V, EN0=open, ENTRIPx = 5 V, 0.8 1.5 mA

VO2 current = 3.3 V, EN0=open, ENTRIPx = 5 V, 12 100

VIN standby current 95 150

VIN shutdown current 10 25

VREF OUTPUT

VREF

VREF output voltage V

VREG5 OUTPUT

VREG5

TH5VSW

5VSW

VREG5 output voltage VO1 = 0 V, I

VREG5 output current VO1 = 0 V, VREG5 = 4.5 V 100 175 250 mA

Switch over threshold V

5 V SW R

VREG3 OUTPUT

VREG3

TH3VSW

3VSW

VREG3 output voltage VO2 = 0 V, I

VREG3 output current VO2 = 0 V, VREG3 = 3 V 100 175 250 mA

Switch over threshold V

3 V SW R

INTERNAL REFERENCE VOLTAGE

IREF

VFB

Internal reference voltage I

VFB regulation voltage FB voltage, I

VFB input current VFBx = 2.0 V, TA= 25°C -20 20 nA

(1) Ensured by design. Not production tested.

VIN current, TA= 25°C, no load, VO1 = 0 V, VO2 VFB1 = VFB2 = 2.05 V

VIN current, TA= 25°C, no load, VO1 = 5 V, VO2 = VFB1 = VFB2 = 2.05 V

VO1 current, TA= 25°C, no load, VO1 = 5 V, VO2 VFB1 = VFB2 = 2.05 V

VO2 current, TA= 25°C, no load, VO1 = 5 V, VO2 VFB1 = VFB2 = 2.05 V

VIN current, TA= 25°C, no load, μA EN0 = 1.2 V, ENTRIPx = 0 V

VIN current, TA= 25°C, no load, EN0 = ENTRIPx = 0 V

= 0 A 1.98 2.00 2.02

VREF

-5 μA < I

VO1 = 0 V, I

< 100 μA 1.97 2.00 2.03

VREF

< 100 mA, TA= 25°C 4.8 5 5.2

VREG5

< 100 mA, 6.5 V < VIN < 28 V 4.75 5 5.25 V

VREG5

< 50 mA, 5.5 V < VIN < 28 V 4. 75 5 5.25

VREG5

Turns on 4.55 4.7 4.85 Hysteresis 0.15 0.25 0.3 VO1 = 5 V, I

VO2 = 0 V, I

= 100 mA 1 3 Ω

VREG5

< 100 mA, TA= 25°C 3.2 3.33 3.46

VREG3

< 100 mA, 6.5 V < VIN < 28 V 3.13 3.33 3.5 V

VREG3

< 50 mA, 5.5 V < VIN < 28 V 3.13 3.33 3.5

VREG3

Turns on 3.05 3.15 3.25 Hysteresis 0.1 0.2 0.25 VO2 = 3.3 V, I

= 0 A, beginning of ON state 1.95 1.98 2.01

VREF

FB voltage, I

= 100 mA 1.5 4 Ω

VREG3

= 0 A, skip mode 1.98 2.01 2.04

VREF

= 0 A, OOA mode

VREF

= 0 A, continuous conduction

VREF

(1)

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2.00 2.035 2.07

(1)

2.00

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TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

DISCHARGE

OUT

Dischg

OUTPUT DRIVERS

DRVH

DRVL

CLOCK OUTPUT

CLKH

CLKL

CLK

INTERNAL BST DIODE

FBST

VBSTLK

DUTY AND FREQUENCY CONTROL

ON11

ON12

ON13

ON14

ON21

ON22

ON23

ON24

ON(min)

OFF(min)

SOFT-START

POWERGOOD

THPG

PGMAX

PGDEL

VOUT discharge current ENTRIPx = 0 V, VOx = 0.5 V 10 60 mA

DRVH resistance

DRVL resistance

Dead time ns

High level voltage I Low level voltage I

Source, V Sink, V Source, V Sink, V DRVHx-off to DRVLx-on 10 DRVLx-off to DRVHx-on 30

VCLK VCLK

BSTx - DRVHx

DRVHx - LLx

VREG5 - DRVLx

= 100 mV 1.5 4

DRVLx

= -10 mA, VO1 = 5 V, TA= 25 °C 4.84 4.92 = 10 mA, VO1 = 5 V, TA= 25 °C 0.06 0.12

= 100 mV 4 8

= 100 mV 1.5 4

= 100 mV 4 8

Clock frequency TA= 25 °C 175 270 325 kHz

Forward voltage V

VREG5-VBSTx

, IF= 10 mA, TA= 25 °C 0.7 0.8 0.9 V

VBST leakage current VBSTx = 34 V, LLx = 28 V, TA= 25 °C 0.1 1 μA

CH1 on time 1 VIN= 12 V, VO1 = 5 V, 200 kHz setting 2080 CH1 on time 2 VIN= 12 V, VO1 = 5 V, 245 kHz setting 1700 CH1 on time 3 VIN= 12 V, VO1 = 5 V, 300 kHz setting 1390 CH1 on time 4 VIN= 12 V, VO1 = 5 V, 365 kHz setting 1140 CH2 on time 1 VIN= 12 V, VO2 = 3.3 V, 250 kHz setting 1100 CH2 on time 2 VIN= 12 V, VO2 = 3.3 V, 305 kHz setting 900 CH2 on time 3 VIN= 12 V, VO2 = 3.3 V, 375 kHz setting 730 CH2 on time 4 VIN= 12 V, VO2 = 3.3 V, 460 kHz setting 600 Minimum on time TA= 25 °C 80 Minimum off time TA= 25 °C 300

Internal SS time Internal soft start 1.1 1.6 2.1 ms

PG in from lower 92.50% 95% 97.50%

PG threshold PG in from higher 105%

PG hysteresis 2.50% 5% 7.50% PG sink current PGOOD = 0.5 V 5 12 mA PG delay Delay for PG in 350 510 670 μs

Ω

102.50 107.50 % %

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TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

LOGIC THRESHOLD AND SETTING CONDITIONS

Shutdown 0.4

EN0

TONSEL

SKIPSEL

PROTECTION: CURRENT SENSE

ENTRIP

IENTRIP

OCLoff

OCL(max)

ENTRIP

PROTECTION: UVP AND OVP

OVP

OVPDEL

UVP

UVPDEL

UVPEN

UVLO

UVVREG5

UVVREG3

THERMAL SHUTDOWN

SDN

(2) Ensured by design. Not production tested.

EN0 setting voltage Enable, VCLK = off 0.8 1.6 V

Enable, VCLK = on 2.4 V

= 0.2 V 2 3.5 5

EN0 current μA

ENTRIP1, ENTRIP2 threshold

EN0

= 1.5 V 1 1.75 2.5

EN0

Shutdown 350 400 450 Hysteresis 10 30 60 200 kHz/250 kHz 1.5

TONSEL setting voltage

245 kHz/305 kHz 1.9 2.1 300 kHz/375 kHz 2.7 3.6 365 kHz/460 kHz 4.7 V PWM only 1.5

SKIPSEL setting voltage Auto skip 1.9 2.1

OOA auto skip 2.7

ENTRIPx source current V ENTRIPx current temperature

coefficient OCP comparator offset -8 0 8

On the basis of 25°C ((V

V Maximum OCL setting V Zero cross detection

comparator offset

V Current limit threshold V

= 920 mV, TA= 25°C 9.4 10 10.6 μA

ENTRIPx

(2)

ENTRIPx-GND

ENTRIPx-GND ENTRIPx

GND-LLx

ENTRIPx-GND

/9)-24 mV -V

= 920 mV

= 5 V 185 205 225 mV voltage -5 0 5

voltage,

(2)

GND-LLx

) voltage,

OVP trip threshold OVP detect 110% 115% 120% OVP prop delay 2 μs

Output UVP trip threshold

UVP detect 55% 60% 65%

Hysteresis 10% Output UVP prop delay 20 32 40 μs Output UVP enable delay 1.4 2 2.6 ms

VREG5 UVLO threshold

VREG3 UVLO threshold Shutdown

Thermal shutdown threshold °C

Wake up 4.1 4.2 4.3

Hysteresis 0.38 0.43 0.48 V

(2)

Shutdown temperature

Hysteresis

(2)

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4500 ppm/°C

0.515 2 V

VO2-1

150

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TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

DEVICE INFORMATION

Table 2. TERMINAL FUNCTIONS TABLE

TERMINAL

NAME NO.

VIN 16 I High voltage power supply input for 5-V/3.3-V LDO. GND 15 - Ground.

VREG3 8 O

VREG5 17 O

VREF 3 O

EN0 13 I/O

ENTRIP1 1 Channel 1 and Channel 2 enable and OCL trip setting pins.Connect resistor from this pin to GND to ENTRIP2 6 VO1 24 Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge VO2 7 VFB1 2 SMPS feedback inputs. Connect with feedback resistor divider. VFB2 5 PGOOD 23 O Power Good window comparator output for channel 1 and 2. (Logical AND)

SKIPSEL 14 I

TONSEL 4 I 300 kHz/375 kHz setting : connect to VREG3

DRVL1 19 Low-side N-channel MOSFET driver outputs. GND referenced drivers. DRVL2 12 VBST1 22 Supply input for high-side N-channel MOSFET driver (boost terminal). VBST2 9 DRVH1 21 High-side N-channel MOSFET driver outputs. LL referenced drivers. DRVH2 10 LL1 20 Switch node connections for high-side drivers, current limit and control circuitry. LL2 11 VCLK 18 O 270-kHz clock output for 15-V charge pump.

I/O DESCRIPTION

3.3-V power supply output. Connect 10-μF or larger, high-quality X5R or X7R ceramic capacitor to Power GND near the device. A 1-μF ceramic capacitor is acceptable when not loaded.

5-V power supply output. Connect 10-μF or larger, high-quality X5R or X7R ceramic capacitor to Power GND near the device.

2-V reference voltage output. Connect 220-nF to 1-μF, high-quality X5R or X7R ceramic capacitor to Signal GND near the device.

Master enable input. Open : LDOs on, and ready to turn on VCLK and switcher channels. 620 kΩ to GND : enable both LDOs, VCLK off and ready to turn on switcher channels. Power

consumption is almost the same as the case of VCLK = ON. GND : disable all circuit

I/O

set threshold for synchronous R

inputs. VO1 and VO2 also work as 5 V and 3.3 V switch over return power input respectively.

Selection pin for operation mode: OOA auto skip : Connect to VREG3 or VREG5 Auto skip : Connect to VREF PWM only : Connect to GND On-time adjustment pin. 365 kHz/460 kHz setting : connect to VREG5

245 kHz/305 kHz setting : connect to VREF 200 kHz/250 kHz setting : connect to GND

sense. Short to ground to shutdown a switcher channel.

DS(on)

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Page 8

VO1

PGOOD

VBST1

DRVH1

VO2

VREG3

VBST2

DRVH2

TPS51125ARGE

LL1

DRVL1

LL2

DRVL2

13 14 15 16 17 18

EN0

SKIPSEL

GND

VIN

VREG5

VCLK

6 5 4 3 2 1

ENTRIP2

VFB2

TONSEL

VREF

VFB1

ENTRIP1

PowerPAD

220 nF

20 kW 20 kW 30 kW

100 kW

VREG5

10 mF

5.1 W

0.1 mF

130 kW130 kW

3.3 mF

330 mF

VO1

5 V

VIN

VREG5

VIN

10 mF x 2

VIN

5.5 V to

28 V

EN0

5.1 W

0.1 mF

3.3 mF

330 mF

VO2

3.3 V

10 mF x 2

10 mF

13 kW

VIN

100 nF 1 mF

15 V

100 nF

620 kW

VO1VREF

TPS51125ARGE

VO1

PGOOD

VO2

VREG3

VBST1

DRVL1

LL1

DRVH1

VBST2

DRVH2

LL2

DRVL2

EN0

ENTRIP2

VFB2

VREF

TONSEL

VFB1

ENTRIP1

SKIPSEL

GND

VIN

VCLK

VREG5

7 8

9 10

24 23

22 21

20 19

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

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QFN PACKAGE

24 PINS

(TOP VIEW)

Typical Application Diagram

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TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Functional Block Diagram

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Page 10

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Switcher Controller Block

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Page 11

VIN SUPPLY CURRENT2

JUNCTION TEMPERATURE

-50 0 50 100 150

TJ- Junction Temperature - °C

VIN2

- VIN Supply Current2 - mA

VIN SUPPLY CURRENT2

INPUT VOLTAGE

5 10 15 20 25

VIN- Input Voltage - V

VIN2

- VIN Supply Current2 - mA

VIN SUPPLY CURRENT1

INPUT VOLTAGE

100

200

300

400

500

600

700

800

5 10 15 20 25

VIN- Input Voltage - V

VIN1

- VIN Supply Current1 - mA

VIN SUPPLY CURRENT1

JUNCTION TEMPERATURE

100

200

300

400

500

600

700

800

-50 0 50 100 150

TJ- Junction Temperature - °C

VIN1

- VIN Supply Current1 - m A

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS

Figure 1. Figure 2.

Figure 3. Figure 4.

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Page 12

VIN SHUTDOWN CURRENT

INPUT VOLTAGE

5 10 15 20 25

VIN- Input Voltage - V

VINSDN

- VIN Shutdown Current - mA

VIN SHUTDOWN CURRENT

JUNCTION TEMPERATURE

-50 0 50 100 150

TJ- Junction Temperature - °C

VINS DN

- VIN Shutdown Current - mA

VIN STANDBY CURRENT

JUNCTION TEMPERATURE

100

150

200

250

0 50 100 150

TJ- Junction Temperature - °C

VINST BY

- VIN Standby Cu rrent - mA

VINSTANDBY CURRENT

INPUTVOLTAGE

100

150

200

250

5 10 15 20 25

VIN-InputVoltage-V

I – VINStandbyCurrent – A

VINSTBY

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

Figure 5. Figure 6.

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Figure 7. Figure 8.

Product Folder Links: TPS51125A

Page 13

SWITCHINGFREQUENCY

INPUTVOLTAGE

100

200

300

400

500

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

- Swithching Frequency - kHz

TONSEL =GND

CH1

CH2

SWITCHINGFREQUENCY

INPUTVOLTAGE

100

200

300

400

500

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

- Swithching Frequency - kHz

TONSEL =2V

CH1

CH2

CURRENT SENSE CURRENT

JUNCTION TEMPERATURE

-50 0 50 100 150

TJ- Junction Temperature - °C

ENT RIP

- Current Sense Cu rrent - mA

VCLK FREQUENCY

JUNCTION TEMPERATURE

175

200

225

250

275

300

325

-50 0 50 100 150

TJ- Junction Temperature - °C

CL K

- VCLK Frequency - kHz

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

Figure 9. Figure 10.

Figure 11. Figure 12.

Product Folder Links: TPS51125A

Page 14

SWITCHINGFREQUENCY

OUTPUTCURRENT

100

200

300

400

500

0.001 0.01 0.1 1 10

OUT

-OutputCurrent- A

- Swithching Frequency - kHz

TONSEL =2V

CH2 Auto-skip

CH2OOA

CH2PWMOnly

CH1PWMOnly

CH1 Auto-skip

CH1OOA

SWITCHINGFREQUENCY

OUTPUTCURRENT

100

200

300

400

500

0.001 0.01 0.1 1 10

OUT

-OutputCurrent- A

- Swithching Frequency - kHz

TONSEL =GND

CH2 Auto-skip

CH2OOA

CH2PWMOnly

CH1PWMOnly

CH1 Auto-skip

CH1OOA

SWITCHINGFREQUENCY

INPUTVOLTAGE

100

200

300

400

500

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

- Swithching Frequency - kHz

TONSEL =3.3V

CH1

CH2

SWITCHINGFREQUENCY

INPUTVOLTAGE

100

200

300

400

500

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

- Swithching Frequency - kHz

TONSEL =5V

CH1

CH2

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

Figure 13. Figure 14.

www.ti.com

Figure 15. Figure 16.

Product Folder Links: TPS51125A

Page 15

VREG5 OUTPUT VOLTAGE

OUTPUT CURRENT

4.90

4.95

5.00

5.05

0 20 40 60 80 100

VREG5

- VREG5 Output Curr ent - m A

VREG5

- VREG5 Outp ut Voltage - V

OVP/UVP THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

100

110

120

130

140

150

-50 0 50 100 150

TJ- Junction Temperature - °C

OVP/VUV P

- OVP/UVP Threshold - %

SWITCHINGFREQUENCY

OUTPUTCURRENT

100

200

300

400

500

0.001 0.01 0.1 1 10

OUT

-OutputCurrent- A

- Swithching Frequency - kHz

TONSEL =5V

CH2 Auto-skip

CH2OOA

CH2PWMOnly

CH1PWMOnly

CH1 Auto-skip

CH1OOA

SWITCHINGFREQUENCY

OUTPUTCURRENT

100

200

300

400

500

0.001 0.01 0.1 1 10

OUT

-OutputCurrent- A

- Swithching Frequency - kHz

TONSEL =3.3V

CH2 Auto-skip

CH2OOA

CH2PWMOnly

CH1PWMOnly

CH1 Auto-skip

CH1OOA

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

Figure 17. Figure 18.

Figure 19. Figure 20.

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Page 16

3.3-VOUTPUTVOLTAGE vs

OUTPUTCURRENT

3.240

3.270

3.300

3.330

3.360

0.001 0.01 0.1 1 10

OUT2

-3.3-VOutputCurrent- A

OUT2

- 3.3-V Outp ut Voltage - V

PWMOnly

Auto-skip

OOA

5-VOUTPUTVOLTAGE

OUTPUTCURRENT

4.950

4.975

5.000

5.025

5.050

5.075

0.001 0.01 0.1 1 10

OUT1

-5-VOutputCurrent- A

OUT1

- 5-V Out put Voltag e - V

PWMOnly

Auto-skip

OOA

VREG3 OUTPUT VOLTAGE

OUTPUT CURRENT

3.2

3.25

3.3

3.35

0 20 40 60 80 100

VREG3

- VREG3 Output Curr ent - m A

VVR EG3 - VREG3 Output Voltage - V

VREF OUTPUT VOLTAGE

OUTPUT CURRENT

1.980

1.985

1.990

1.995

2.000

2.005

2.010

2.015

2.020

0 20 40 60 80 100

VREF

- VREF Output Current - mA

VREF

- VREF Output Voltage - V

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

www.ti.com

Figure 21. Figure 22.

Figure 23. Figure 24.

Product Folder Links: TPS51125A

Page 17

5-V EFFICIENCY

OUTPUT CURRENT

100

0.001 0.01 0.1 1 10

OUT1

- 5-V Output Current - A

h - Efficiency - %

Auto-skip

PWM Only

OOA

VIN=8V

VIN=12V

VIN=20V

3.3-V EFFICIENCY vs

OUTPUT CURRENT

100

0.001 0.01 0.1 1 10

OUT2

- 3.3-V Output Current - A

h - Efficiency - %

Auto-skip

PWM Only

OOA

5-V Switcher ON

VIN=8V

VIN=12V

VIN=20V

3.3-VOUTPUTVOLTAGE vs

INPUTVOLTAGE

3.240

3.270

3.300

3.330

3.360

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

OUT2

- 3.3-V Outp ut Voltage - V

IO=0A

IO=6A

5-VOUTPUTVOLTAGE

INPUTVOLTAGE

4.950

4.975

5.000

5.025

5.050

5.075

6 8 10 12 14 16 18 20 22 24 26

VIN-InputVoltage-V

OUT1

- 5-V Out put Voltag e - V

IO=0A

IO=6A

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

Figure 25. Figure 26.

Figure 27. Figure 28.

Product Folder Links: TPS51125A

Page 18

ENTRIP1 (2V/div)

OUT1

(2V/div)

PGOOD (5V/div)

ENTRIP2 (2V/div)

OUT2

(2V/div)

PGOOD (5V/div)

OUT1

(100mV/div)

IND

(5A/div)

OUT1

(5A/div)

OUT2

(100mV/div)

IND

(5A/div)

OUT2

(5A/div)

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

5-V Load Transient Response 3.3-V Load Transient Response

Figure 29. Figure 30.

5-V Startup Waveforms 3.3-V Startup Waveforms

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Figure 31. Figure 32.

Product Folder Links: TPS51125A

Page 19

ENTRIP1 (5V/div)

OUT1

(2V/div)

PGOOD (5V/div)

DRVL1 (5V/div)

ENTRIP2 (5V/div)

OUT2

(2V/div)

PGOOD (5V/div)

DRVL2 (5V/div)

OUT1

(200mV/div)

VREG5 (200mV/div)

OUT2

(200mV/div)

VREG3 (200mV/div)

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

TYPICAL CHARACTERISTICS (continued)

5-V Switchover Waveforms 3.3-V Switchover Waveforms

Figure 33. Figure 34.

5-V Soft-stop Waveforms 3.3-V Soft-stop Waveforms

Figure 35. Figure 36.

Product Folder Links: TPS51125A

Page 20

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

www.ti.com

APPLICATION INFORMATION

PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external compensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ‘ON’ state. This MOSFET is turned off, or becomes ‘OFF’ state, after internal one shot timer expires. This one shot is determined by VINand V

to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time

OUT

control. The MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal 2-V reference. The inductor current information is also monitored and should be below the over current threshold to initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the “rectifying” MOSFET is turned on at the beginning of each ‘OFF’ state to keep the conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current.

Adaptive On-Time Control and PWM Frequency

TPS51125A does not have a dedicated oscillator on board. However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal connection as Table 3.

TONSEL CONNECTION

GND 200 kHz 250 kHz

VREF 245 kHz 305 kHz VREG3 300 kHz 375 kHz VREG5 365 kHz 460 kHz

Table 3. TONSEL Connection and Switching Frequency

SWITCHING FREQUENCY

CH1 CH2

Product Folder Links: TPS51125A

Page 21

2 ESR C 4

= £

p ´ ´

ESR

Control

logic

Driver

VIN

VFB

DRVH

DRVL

PWM

Switching ModulatorVoltage Divider

IoIc

Output Capacitor

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Loop Compensation

From small-signal loop analysis, a buck converter using D-CAPTMmode can be simplified as below.

Figure 37. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the 0dB frequency, f0, defined below need to be lower than 1/4 of the switching frequency.

As f0is determined solely by the output capacitor's characteristics, loop stability of D-CAPTMmode is determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100 μF and ESR in range of 10 mΩ. These will make f0in the order of 100 kHz or less and the loop will be stable. However, ceramic capacitors have f0at more than 700 kHz, which is not suitable for this operational mode.

Ramp Signal

The TPS51125A adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with -20mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in steady state. By using this scheme, the TPS51125A improve jitter performance without sacrificing the reference accuracy.

(1)

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Page 22

( )

IN OUT OUT

OUT(LL)

2 L

V V V

´ ´

- ´

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

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Light Load Condition in Auto-Skip Operation

The TPS51125A automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of V described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ‘ON’ cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation I threshold between continuous and discontinuous conduction mode) can be calculated as follows;

where f is the PWM switching frequency. Switching frequency versus output current in the light load condition is a function of L, VINand V

decreases almost proportional to the output current from the I at I

/5 if the frequency setting is 300 kHz.

OUT(LL)

given above. For example, it will be 60 kHz

ripple. Detail operation is

OUT

OUT(LL)

(i.e. the

, but it

OUT

(2)

Product Folder Links: TPS51125A

Page 23

TPS51125A

www.ti.com

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Out-of-Audio™ Light-Load Operation

Out-of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion efficiency. When the Out-of-Audio™ operation is selected, OOA control circuit monitors the states of both MOSFET and force to change into the ‘ON’ state if both of MOSFETs are off for more than 32 μs. This means that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output capacitor is tends to be overcharged.

The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation.

Enable and Soft Start

EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those three regulators and minimize the shutdown supply current to 10 μA. Pulling this node up to 3.3 V or 5 V will turn the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become ready to enable at this standby mode. The TPS51125A has an internal, 1.6 ms, voltage servo softstart for each channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As TPS51125A shares one DAC with both channels, if ENTRIPx pin becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable threshold voltage at a same time (within 60 μs), both channels start up at same time.

Table 4. Enabling State

EN0 ENTRIP1 ENTRIP2 VREF VREG5 VREG3 CH1 CH2 VCLK

GND Don’t Care Don’t Care Off Off Off Off Off Off R to GND Off Off On On On Off Off Off R to GND On Off On On On On Off Off R to GND Off On On On On Off On Off R to GND On On On On On On On Off

Open Off Off On On On Off Off Off Open On Off On On On On Off On Open Off On On On On Off On Off Open On On On On On On On On

VREG5/VREG3 Linear Regulators

There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5 serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers. The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.

Add high-quality X5R or X7R ceramic capacitor with a value of 10 μF or larger placed close to the VREG5 and VREG3 pins to stabilize LDOs. For VREG3, a 1-μF ceramic capacitor is acceptable when not loaded.

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Page 24

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

www.ti.com

VREG5 Switch Over

When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal 5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The 510-μs powergood delay helps a switch over without glitch.

VREG3 Switch Over

When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated, internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over MOSFET. The 510-μs powergood delay helps a switch over without glitch.

Powergood

The TPS51125A has one powergood output that indicates 'high' when both switcher outputs are within the targets (AND gated). The powergood function is activated with 2-ms internal delay after ENTRIPx goes high. If the output voltage becomes within +/-5% of the target value, internal comparators detect power good state and the powergood signal becomes high after 510-μs internal delay. Therefore PGOOD goes high around 2.5 ms after ENTRIPx goes high. If the output voltage goes outside of +/-10% of the target value, the powergood signal becomes low after 2-μs internal delay. The powergood output is an open drain output and is needed to be pulled up outside.

Also note that, in the case of Auto-skip or Out-of-Audio™ mode, if the output voltage goes +10% above the target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-Audio™ mode.

Output Discharge Control

When ENTRIPx is low, the TPS51125A discharges outputs using internal MOSFET which is connected to VOx and GND. The current capability of these MOSFETs is limited to discharge slowly.

Low-Side Driver

The low-side driver is designed to drive high current low R represented by its internal resistance, which are 4 Ω for VREG5 to DRVLx and 1.5 Ω for DRVLx to GND. A dead time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the highside gate drive current times 5 V makes the driving power which need to be dissipated from TPS51125A package.

N-channel MOSFET(s). The drive capability is

DS(on)

High-Side Driver

The high-side driver is designed to drive high current, low R floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are 4 Ω for VBSTx to DRVHx and 1.5Ω for DRVHx to LLx.

N-channel MOSFET(s). When configured as a

DS(on)

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Page 25

1uF

100nF

PGND PGND PGND

- 15V/10mA

D0 D1

100nF

VO1(5V)

VCLK

Control

Input

3.3V

TPS51125ATPS51125A

EN0

GNDGND

EN0

Control

Input

(a) Control by MOSFET Switch (b) Control by Logic

TPS51125A

www.ti.com

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

VCLK for Charge Pump

270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock signal becomes available when EN0 becomes higher than 2.4 V or open state. Example of control circuit is shown in Figure 38. Note that the clock driver uses VO1 as its power supply. Regardless of enable or disable of VCLK, power consumption of the TPS51125A is almost the same. Therefore even if VCLK is not used, one can let EN0 pin open or supply logic ‘high’, as shown in Figure 38, and let VCLK pin open. This approach further reduces the external part count.

Figure 38. Control Example of EN0 Master Enable

Figure 39. 15-V / 10-mA Charge Pump Configuration

Product Folder Links: TPS51125A

Page 26

( ) ( )

( )

IN OUT OUT

TRIP RIPPLE TRIP

OCP

DS on DS on

V V V

V I V

R 2 R 2 L V

- ´

= + = + ´

´ ´

( )

( ) ( )

( )

TRIP TRIP

TRIP

R k I A

V mV 24 mV

W ´ m

= -

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

www.ti.com

Current Protection

TPS51125A has cycle-by-cycle over current limiting control. The inductor current is monitored during the ‘OFF’ state and the controller keeps the ‘OFF’ state during the inductor current is larger than the over current trip level. In order to provide both good accuracy and cost effective solution, TPS51125A supports temperature compensated MOSFET R setting resistor, R

. ENTRIPx terminal sources I

TRIP

the trip level is set to the OCL trip voltage V internally.

External leakage current to ENTRIPx pin should be minimized to obtain accurate OCL trip voltage. The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be

connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/°C temperature slope to compensate the temperature dependency of the R that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom MOSFET.

As the comparison is done during the ‘OFF’ state, V current at over current threshold, I

sensing. ENTRIPx pin should be connected to GND through the trip voltage

DS(on)

TRIP

, can be calculated in Equation 4.

OCP

current, which is 10 μA typically at room temperature, and

TRIP

as below. Note that the V

. GND is used as the positive current sensing node so

DS(on)

sets valley level of the inductor current. Thus, the load

TRIP

is limited up to about 205 mV

TRIP

(3)

(4)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and shutdown both channels.

Over/Under Voltage Protection

TPS51125A monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

Also, TPS51125A monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51125A turns off the top MOSFET driver.

When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 μs, TPS51125A latches OFF both top and bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after 2 ms following ENTRIPx has become high.

Product Folder Links: TPS51125A

Page 27

( ) ( )

( )

OUT

RIPPLE

V 20 mV 1 D 20 mV L

ESR

2 V I 2 V

´ ´ - ´ ´

= =

( )

(

)

( )

OUT OUT

IN m ax

TRIP

IND peak

DS on IN m ax

R L

V V V

V´

- ´

= + ´

( )

(

)

( )

(

)

( )

f f

OUT OUT OUT OUT

IN max IN max

IND ripple IN max OUT max IN max

1 3

I I

V V V V V V

V V

´ ´

- ´ - ´

= = ´

( )

OUT

V 2.0

R1 R2

2.0

= ´

TPS51125A

www.ti.com

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

UVLO Protection

TPS51125A has VREG5 under voltage lock out protection (UVLO). When the VREG5 voltage is lower than UVLO threshold voltage both switch mode power supplies are shut off. This is non-latch protection. When the VREG3 voltage is lower than (VO2 - 1 V), both switch mode power supplies are also shut off.

Thermal Shutdown

TPS51125A monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C), TPS51125A is shut off including LDOs. This is non-latch protection.

External Parts Selection

The external components selection is much simple in D-CAP™ Mode.

1. Determine Output Voltage

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is connected between VFBx pin and the output, and R2 is connected betwen the VFBx pin and GND. Recommended R2 value is from 10 kΩ to 20 kΩ. Determine R1 using equation as below.

(5)

2. Choose the Inductor

The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable operation.

(6)

The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows.

(7)

3. Choose the Output Capacitor(s)

Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage. A quick approximation is as shown in Equation 8.

where

• D is the duty cycle

• the required output ripple slope is approximately 20 mV per TSW(switching period) in terms of VFB terminal voltage (8)

4. Choose the Low-Side MOSFET

It is highly recommended that the low-side MOSFET should have an integrated Schottky barrier diode, or an external Schottky barrier diode in parallel to achieve stable operation.

Product Folder Links: TPS51125A

Page 28

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

www.ti.com

Layout Considerations

Certain points must be considered before starting a layout work using the TPS51125A.

• TPS51125A has only one GND pin and special care of GND trace design makes operation stable, especially when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF capacitor as close as possible, connect them to an inner GND plane with PowerPad, overcurrent setting resistor and EN0 pull-down resistor as shown in the thin GND line of Figure 40. This trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as possible, and connect them to another GND plane with GND pin of the device, GND terminal of VREG3 and VREG5 capacitors and 15-V charge-pump circuit as shown in the bold GND line of

Figure 40. This trace is named Power Ground (PGND). SGND should be connected to PGND at the middle

point between ground terminal of VOUT capacitors.

• Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Power components of each channel should be at the same distance from the TPS51125A. Other small signal parts should be placed on another side (component side). Inner GND planes above should shield and isolate the small signal traces from noisy power lines.

• PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible.

• High-quality X5R or X7R ceramic bypass capacitor of following capacitance value should be placed close to the device and traces should be no longer than 10 mm.

– VREG5: 10 μF or larger – VREG3: 10 μF or larger (1 μF is acceptable when not loaded.) – VREF: 220 nF to 1 μF

• Connect the overcurrent setting resistors from ENTRIPx to SGND and close to the device, right next to the device if possible.

• The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3 is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the device. Place on the component side and avoid vias between this resistor and the device.

• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace.

• All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, ENTRIPx, PGOOD, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, DRVHx and VCLK nodes to avoid coupling.

• Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel interference.

• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. This thermal land underneath the package should be connected to SGND, and should NOT be connected to PGND.

Product Folder Links: TPS51125A

Page 29

Driver and switch node traces are shown for CH1 only.

Cin

Vout1

HS-MOSFET

LS-MOSFET

HS-MOSFET

Vout2

Cout

To CH1 Vout divider

To CH2 Vout divider

To VO2

To VO1

LS-MOSFET

Bottom Layer

VIN

GND

Connection to GND island

Connection to GND

Connection of Vout

Top Layer

TPS51125A

VREF

CH1 Vout divider

VREG5

DRVH1*

LL1*

DRVL1*

Through hole

CH2 Vout divider

Connection to GND island

GND

Inner Layer

VREG3

Cout

GND island

TPS51125A

DRVL1DRVL2

PowerPAD

VFB1VFB2 VREF

GND

VREG5

VREG3

220 nF

SGND

5 3 2

12 19

10 mF

817

10 mF

OUT1

OUT2

PGND PGND

Charge

Pump

VCLK

15 V OUT

TPS51125A

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SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Figure 40. GND system of DC/DC converter using the TPS51125A

Figure 41. PCB Layout Design

Product Folder Links: TPS51125A

Page 30

VO1

PGOOD

VO2

VREG3

TPS51125ARGE

(QFN24)

13 14 15 16

VBST1

DRVL1

LL1

DRVH1

VBST2

DRVH2

LL2

DRVL2

2 1

VO1 5V/8A

3.3mH

IRF7821

VO1_GND

PGND

10mF

0.1mF

VIN

VO2

3.3V/8A

3.3mH

IRF7821

VO2_GND

0.1mF

VIN

PowerPAD

C11

10mF

C10

POSCAP

330mF

PGND

5.1W

VIN

5.5 ~ 28V

5.1W

10mF

PGND

POSCAP

330mF

5V/100mA

PGND

30kW

20kW

13kW

SGND

VREG5

100kW

PGND

20kW

0.22mF

PGND

SGND

130kW

SGND

130kW

C16 1uF

C13 100nF

C14 100nF

C15 100nF

PGND

15V/10mA

C12 100nF

10mF

PGND

3.3V/100mA

10mF

VREF

VO1

EN0

PGNDPGND

SGND

VREF

R10 620kW

SGND

FDS6690AS

TPS51125A

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

Application Circuit

www.ti.com

Figure 42. 5-V/8-A, 3.3-V/8-A Application Circuit (245-kHz/305-kHz Setting)

Table 5. List of Materials for 5-V/8-A, 3.3-V/8-A Application Circuit

SYMBOL SPECIFICATION MANUFACTURER PART NUMBER

3.3 μH, 15.6 A, 5.92 mΩ

30 V, 12 mΩ Fairchild FDS6690AS

C1, C2, C8, C9 10 μ F, 25 V Taiyo Yuden TMK325BJ106MM C3, C11 10 μF, 6.3 V TDK C2012X5R0J106K C5, C10 330 μF, 6.3 V, 25 mΩ Sanyo 6TPE330ML

L1, L2 TOKO FDA1055-3R3M Q1, Q3 30 V, 9.5 mΩ IR IRF7821

(1) Please use MOSFET with integrated Schottky barrier diode (SBD) for low side, or add SBD in parallel

(1)

Q2, Q4

with normal MOSFET.

Product Folder Links: TPS51125A

Page 31

TPS51125A

www.ti.com

SLUS976F –SEPTEMBER 2009–REVISED SEPTEMBER 2012

REVISION HISTORY

Changes from Revision B (September, 2009) to Revision A Page

• Added Table 1 ...................................................................................................................................................................... 1

• Added Figure 41 ................................................................................................................................................................. 29

Changes from Revision A (January 2010) to Revision B Page

• Changed LDO Output Capacitance Requirement table from "at least" to "at most" ............................................................ 1

• Changed VIN standby current value from 250 µA to 150 µA. .............................................................................................. 4

Changes from Revision B (September 2009) to Revision C Page

• Added note to table ............................................................................................................................................................... 6

• Added an updated Switcher Controller Block diagram. ...................................................................................................... 10

Changes from Revision C (April 2011) to Revision D Page

• Added an updated Switcher Controller Block diagram. ...................................................................................................... 10

• Changed bulletted duty cycle description. .......................................................................................................................... 27

Changes from Revision D (June 2011) to Revision E Page

• Added Input voltage range parameter LL1, LL2, pulse width < 20 ns with a value of -5.0 V to 30 V in ABSOLUTE

MAXIMUM RATINGS table ................................................................................................................................................... 2

Changes from Revision E (MARCH 2012) to Revision F Page

• Added Electrostatic discharge ratings in ABSOLUTE MAXIMUM RATINGS table .............................................................. 2

Product Folder Links: TPS51125A

Page 32

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

TPS51125ARGER ACTIVE VQFN RGE 24 3000 Green (RoHS

TPS51125ARGET ACTIVE VQFN RGE 24 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51125A

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

9-Sep-2014

Samples

Addendum-Page 1

Page 33

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

9-Sep-2014

Addendum-Page 2

Page 34

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS51125ARGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TPS51125ARGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 35

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51125ARGER VQFN RGE 24 3000 367.0 367.0 35.0

TPS51125ARGET VQFN RGE 24 250 210.0 185.0 35.0

Pack Materials-Page 2

Page 36

Page 37

Page 38

Page 39

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet TPS51125A Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

PWM Operations

Adaptive On-Time Control and PWM Frequency

Loop Compensation

Ramp Signal

Light Load Condition in Auto-Skip Operation

Out-of-Audio™ Light-Load Operation

Enable and Soft Start

VREG5/VREG3 Linear Regulators

VREG5 Switch Over

VREG3 Switch Over

Powergood

Output Discharge Control

Low-Side Driver

High-Side Driver

VCLK for Charge Pump

Current Protection

Over/Under Voltage Protection

UVLO Protection

Thermal Shutdown

External Parts Selection

1. Determine Output Voltage

2. Choose the Inductor

3. Choose the Output Capacitor(s)

4. Choose the Low-Side MOSFET

Layout Considerations

Application Circuit

REVISION HISTORY