Datasheet TPS3851 Datasheet (Texas Instruments)

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Page 1

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.5

-0.3

-0.1

0.1

0.3

0.5 Unit 1 Unit 2

Unit 3 Unit 4

Unit 5 Average

RESET

VDD

GND

TPS3851

1.8 V

Microcontroller

SET1

RESET

GND

WDO

NMI

CWD

WDI GPIO

Product Folder

Sample & Buy

Technical Documents

Tools & Software

Support & Community

SBVS300 –NOVEMBER 2016

TPS3851 Precision Voltage Supervisor with Integrated Watchdog Timer

TPS3851

1 Features

• 0.8% Voltage Threshold Accuracy

• Precision Undervoltage Monitoring: – Supports Common Rails from 1.8 V to 5.0 V – 4% and 7% Undervoltage Thresholds

Available

– 0.5% Hysteresis

• Factory-Programmed Precision Watchdog and Reset Timers:

– ±15% Accurate WDT and RST Delays

• Watchdog Disable Feature

• User-Programmable Watchdog Timeout

• Input Voltage Range: VDD= 1.6 V to 6.5 V

• Low Quiescent Current: IDD= 10 µA (typ)

• Open-Drain Outputs

• Manual Reset Input (MR)

• Available in a Small 3-mm × 3-mm, 8-Pin VSON Package

• Junction Operating Temperature Range: –40°C to +125°C

2 Applications

• Safety-Critical Applications

• Telematics Control Units

• FPGAs and ASICs

• Microcontrollers and DSPs

3 Description

The TPS3851 combines a precision voltage supervisor with a programmable watchdog timer. The TPS3851 comparator achieves a 0.8% accuracy (–40°C to +125°C) for the undervoltage (V threshold. The TPS3851 also includes accurate hysteresis on the undervoltage threshold making the device ideal for use with tight tolerance systems. The supervisor RESET delay features a 15% accuracy, high-precision delay timing.

The TPS3851 includes a programmable watchdog timer for a wide variety of applications. The dedicated watchdog output (WDO) enables increased resolution to help determine the nature of fault conditions. The watchdog timeouts can be programmed either by an external capacitor, or by factory-programmed default delay settings. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3851 is available in a small 3.00-mm ×

3.00-mm, 8-pin VSON package.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS3851 VSON (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

(1)

ITN

)

Fully Integrated Microcontroller Supervisory

Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Undervoltage Threshold (V

Temperature

) Accuracy vs

ITN

Page 2

TPS3851

SBVS300 –NOVEMBER 2016

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Device Functional Modes........................................ 14

4 Revision History

DATE REVISION NOTES

November 2016 * Initial release.

8 Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application ................................................. 18

9 Power Supply Recommendations...................... 21

10 Layout................................................................... 21

10.1 Layout Guidelines ................................................. 21

10.2 Layout Example .................................................... 21

11 Device and Documentation Support ................. 22

11.1 Device Support .................................................... 22

11.2 Documentation Support ........................................ 22

11.3 Receiving Notification of Documentation Updates 22

11.4 Community Resources.......................................... 22

11.5 Trademarks........................................................... 22

11.6 Electrostatic Discharge Caution............................ 22

11.7 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information........................................................... 23

Product Folder Links: TPS3851

Page 3

1VDD 8 RESET

2CWD 7 WDO

3MR 6 WDI

4GND 5 SET1

Not to scale

Thermal

Pad

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SBVS300 –NOVEMBER 2016

5 Pin Configuration and Functions

DRB Package: TPS3851

3-mm × 3-mm VSON-8

Top View

Pin Functions

NAME NO. I/O DESCRIPTION

Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and

CWD 2 I

GND 4 — Ground pin MR 3 I

RESET 8 O

SET1 5 I VDD 1 I Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.

WDI 6 I

WDO 7 O

Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

ground. Connecting via a 10-kΩ resistor to VDDor leaving unconnected further enables the selection of the preset watchdog timeouts; see the CWD Functionality section. The TPS3851 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or extended timing, respectively.

Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains low for a fixed reset delay (t

Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). RESET goes low when VDDgoes below the undervoltage threshold (V RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (V monitored voltage is within the correct operating range (above V

Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see the SET1 section.

Watchdog input. A falling edge must occur at WDI before the timeout (tWD) expires. When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when RESET or WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left unconnected and must be driven to either VDD or GND.

Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (t impedance state.

) time after MR is deasserted (high).

RST

ITN

). Above POR, RESET goes low and remains low until the

POR

). When VDDis within the normal operating range, the

ITN+VHYST

) and the RESET timeout is complete.

). When RESET goes low, WDO is in a high-

RST

TPS3851

Product Folder Links: TPS3851

Page 4

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SBVS300 –NOVEMBER 2016

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage range VDD –0.3 7 V Output voltage range RESET, WDO –0.3 7 V

Voltage ranges

Output pin current RESET, WDO ±20 mA Input current (all pins) ±20 mA Continuous total power dissipation See Thermal Information

Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VDD+ 0.3 V or 7.0 V, whichever is smaller. (3) Assume that TJ= TAas a result of the low dissipated power in this device.

SET1, WDI, MR –0.3 7 CWD –0.3 VDD+ 0.3

Operating junction, T

Storage, T

stg

(1)

MIN MAX UNIT

(2)

(3)

–40 150 –40 150

°COperating free-air, T

–65 150

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

±1000

(2)

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

SET1

CWD

CWD Pullup resistor to VDD 9 10 11 kΩ R

RESET

WDO

(1) Using standard timing with a C (2) Using extended timing with a C

Supply pin voltage 1.6 6.5 V SET1 pin voltage 0 6.5 V Watchdog timing capacitor 0.1

(1)(2)

1000

(1)(2)

Pullup resistor, RESET and WDO 1 10 100 kΩ RESET pin current 10 mA Watchdog output current 10 mA Junction temperature –40 125 °C

capacitor of 0.1 nF or 1000 nF gives a t

CWD

capacitor of 0.1 nF or 1000 nF gives a t

CWD

of 0.704 ms or 3.23 seconds, respectively.

WD(typ)

of 62.74 ms or 77.45 seconds, respectively.

WD(typ)

Product Folder Links: TPS3851

Page 5

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SBVS300 –NOVEMBER 2016

6.4 Thermal Information

TPS3851

THERMAL METRIC

(1)

8 PINS

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 50.7 °C/W Junction-to-case (top) thermal resistance 51.6 °C/W Junction-to-board thermal resistance 25.8 °C/W Junction-to-top characterization parameter 1.3 °C/W Junction-to-board characterization parameter 25.8 °C/W Junction-to-case (bottom) thermal resistance 7.1 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at V

+ V

ITN

open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ= 25°C

GENERAL CHARACTERISTICS

(1)(2) (3)

RESET FUNCTION

(2)

POR

(1)

UVLO

ITN

HYST

WATCHDOG FUNCTION

CWD

IL(WDI)

IH(WDI)

(1) When VDDfalls below V (2) When VDDfalls below V (3) During power-on, VDDmust be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD.

≤ VDD≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ≤ 125°C (unless otherwise noted); the

HYST

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage 1.6 6.5 V Supply current 10 19 µA

Power-on reset voltage I

RESET

= 15 µA, V

= 0.25 V 0.8 V

OL(MAX)

Undervoltage lockout voltage 1.35 V Undervoltage threshold accuracy,

entering RESET

VDDfalling V

– 0.8% V

ITN

+ 0.8%

Hysteresis voltage VDDrising 0.2% 0.5% 0.8% MR pin internal pullup current VMR= 0 V 500 620 700 nA

CWD pin charge current CWD = 0.5 V 337 375 413 nA CWD pin threshold voltage 1.192 1.21 1.228 V RESET, WDO output low VDD = 5 V, I RESET, WDO output leakage current,

open-drain

VDD = V V

RESET

= V

= 3 mA 0.4 V

SINK

+ V

WDO

HYST

= 6.5 V

ITN

Low-level input voltage (MR, SET1) 0.25 V High-level input voltage (MR, SET1) 0.8 V Low-level input voltage (WDI) 0.3 × V High-level input voltage (WDI) 0.8 × V

, RESET is driven low.

UVLO

, RESET and WDO are undefined.

POR

TPS3851

UNITDRB (VSON)

1 µA

V V

Product Folder Links: TPS3851

Page 6

VDD

RESET

WDI

WDO

RST

POR

ITN

t < t

t = t

(1)

ITN

+ V

HYST

ITN

RST-DEL

t < t

TPS3851

SBVS300 –NOVEMBER 2016

6.6 Timing Requirements

at V

+ V

ITN

open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ= 25°C

GENERAL

INIT

RESET FUNCTION

RST

RST-DELVDD

MR-DEL

WATCHDOG FUNCTION

WD-

setup

WD-del

(1) During power-on, VDDmust be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD. (2) The fixed watchdog timing covers both standard and extended versions. (3) SET1 = 0 means V

≤ VDD≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ≤ 125°C (unless otherwise noted); the

HYST

MIN NOM MAX UNIT

CWD pin evaluation period 381 µs Minimum MR, SET1 pin pulse duration 1 µs Startup delay

(1)

Reset timeout period 170 200 230 ms

to RESET delay

VDD= V VDD= V

+ V

ITN

– 2.5% 17

ITN

+ 2.5% 35

HYST

MR to RESET delay 200 ns

(3) (3)

Watchdog disabled

1360 1600 1840 ms

Watchdog disabled

170 200 230 ms

Watchdog timeout

CWD = NC, SET1 = 0 CWD = NC, SET1 = 1

(2)

CWD = 10 kΩ to VDD, SET1 = 0

CWD = 10 kΩ to VDD, SET1 = 1

(3)

Setup time required for device to respond to changes on WDI after being enabled

Minimum WDI pulse duration 50 ns WDI to WDO delay 50 ns

< VIL; SET1 = 1 means V

SET1

> VIH.

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300 µs

µs

150 µs

(1) See Figure 2 for WDI timing requirements.

Figure 1. Timing Diagram

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Page 7

Timing

WDI

WD(MIN)

WD(TYP)

WD(MAX)

WDO

= Tolerance Window

Correct

Operation

WDO

Late Fault

WDI

Valid

Region

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TPS3851

SBVS300 –NOVEMBER 2016

Figure 2. Watchdog Timing Diagram

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Page 8

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.5

-0.3

-0.1

0.1

0.3

0.5 Unit 1 Unit 2

Unit 3 Unit 4

Unit 5 Average

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.5

-0.3

-0.1

0.1

0.3

0.5 Unit 1 Unit 2

Unit 3 Unit 4

Unit 5 Average

Temperature (qC)

CWD Charging Current (nA)

-50 -25 0 25 50 75 100 125

364

368

372

376

380

1.6 V

6.5 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.5

-0.3

-0.1

0.1

0.3

0.5 Unit 1 Unit 2

Unit 3 Unit 4

Unit 5 Average

VDD (V)

Supply Current (PA)

0 1 2 3 4 5 6 7

-40qC 0qC 25qC 105qC 125qC

Temperature (qC)

Manual Reset Threshold (V)

-50 -25 0 25 50 75 100 125

0.3

0.4

0.5

0.6

0.7

TPS3851

SBVS300 –NOVEMBER 2016

6.7 Typical Characteristics

all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)

VDD = 1.6 V

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Figure 3. Supply Current vs V

Figure 5. CWD Charging Current vs Temperature

Figure 4. MR Threshold vs Temperature

TPS3851G18, V

Figure 6. V

ITN

+ V

HYST

= 1.728 V

ITN

Accuracy vs Temperature

Figure 7. V

TPS3851G18, V

Accuracy vs Temperature

ITN

= 1.728 V

Figure 8. V

Product Folder Links: TPS3851

TPS3851G50, V

+ V

ITN

Accuracy vs Temperature

HYST

ITN

= 4.8 V

Page 9

RESET

(mA)

(V)

0 1 2 3 4 5 6

0.2

0.4

0.6

0.8

1.2

1.4

1.6

-40qC 0qC 25qC 105qC 125qC

RESET

(mA)

(V)

0 1 2 3 4 5 6

0.2

0.4

0.6

0.8

1.2

1.4

1.6

-40qC 0qC 25qC 105qC 125qC

ITN

Accuracy (%)

Frequency (%)

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Hysteresis (%)

Frequency (%)

0.2 0.35 0.5 0.8

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.5

-0.3

-0.1

0.1

0.3

0.5 Unit 1 Unit 2

Unit 3 Unit 4

Unit 5 Average

ITN

+ V

HYST

Accuracy (%)

Frequency (%)

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

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Typical Characteristics (continued)

all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)

TPS3851

SBVS300 –NOVEMBER 2016

TPS3851G50, V

Figure 9. V

Accuracy vs Temperature

ITN

= 4.8 V

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

Figure 11. V

Accuracy Histogram

ITN

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

Figure 10. V

ITN

+ V

Accuracy Histogram

HYST

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

Figure 12. Hysteresis Histogram

VDD = 1.6 V

Figure 13. Low-Level RESET Voltage vs RESET Current

Figure 14. Low-Level RESET Voltage vs RESET Current

Product Folder Links: TPS3851

VDD = 6.5 V

Page 10

Temperature (qC)

Glitch Immunity (Ps)

-50 -25 0 25 50 75 100 125

Overdrive = 3% Overdrive = 5% Overdrive = 7%

Overdrive = 9% Overdrive = 10%

Temperature (qC)

Glitch Immunity (Ps)

-50 -25 0 25 50 75 100 125

Overdrive = 3% Overdrive = 5% Overdrive = 7%

Overdrive = 9% Overdrive = 10%

Overdrive (%)

Propagation Delay (ms)

0 2 4 6 8 10

190

195

200

205

210

-40qC 0qC

25qC 105qC

125qC

Overdrive (%)

Propagation Delay (ms)

0 2 4 6 8 10

190

195

200

205

210

-40qC 0qC

25qC 105qC

125qC

Overdrive (%)

Propagation Delay (Ps)

0 2 4 6 8 10

100

-40qC 0qC

25qC 105qC

125qC

Overdrive (%)

Propagation Delay (Ps)

0 2 4 6 8 10

-40qC 0qC

25qC 105qC

125qC

TPS3851

SBVS300 –NOVEMBER 2016

Typical Characteristics (continued)

all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)

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TPS3851G18 entering undervoltage

Figure 15. Propagation Delay vs Overdrive

TPS3851G18 exiting undervoltage

Figure 17. Propagation Delay (t

) vs Overdrive

RST

TPS3851G50 entering undervoltage

Figure 16. Propagation Delay vs Overdrive

TPS3851G50 exiting undervoltage

Figure 18. Propagation Delay (t

) vs Overdrive

RST

ITN

= 1.728 V

Figure 19. High-to-Low Glitch Immunity vs Temperature

Figure 20. High-to-Low Glitch Immunity vs Temperature

Product Folder Links: TPS3851

ITN

= 4.8 V

Page 11

VDD

Precision

Clock

State

Machine

Cap

Control

CWD

GND

VDD

WDI

MR SET1

WDO

RESET

Reference

TPS3851

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SBVS300 –NOVEMBER 2016

7 Detailed Description

7.1 Overview

The TPS3851 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3851 includes accurate hysteresis on the threshold, making the device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached. There are two options for the watchdog timing standard and extended timing. To get standard timing use the TPS3851Xyy(y)S, for extended timing use the TPS3851Xyy(y)E.

7.2 Functional Block Diagram

(1) Note: R1+ R2= 4.5 MΩ.

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Undervoltage Limit

VDD

ITN

+ V

HYST

RESET

RST-DEL

RST

RST-DEL

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SBVS300 –NOVEMBER 2016

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Functional Block Diagram (continued)

7.2.1 Feature Description

7.2.1.1 RESET

Connect RESET to VPUthrough a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when VDDis greater than the negative threshold voltage (V asserted, driving the RESET pin to low impedance. When VDDrises above V enabled that holds RESET low for a specified reset delay period (t RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic low voltage (VOL), capacitive loading, leakage current (ID), and the current through the RESET pin I

RESET

7.2.1.2 Manual Reset MR

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and VDDis above V after the reset delay time (t

). If MR is not controlled externally, then MR can either be connected to VDDor left

RST

floating because the MR pin is internally pulled up.

7.2.1.3 UV Fault Detection

The TPS3851 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is monitored on the input rail of the device. If VDDdrops below V V

ITN

+ V

, RESET deasserts after t

HYST

, as shown in Figure 21. The internal comparator has built-in hysteresis

RST

that provides some noise immunity and ensures stable operation. Although not required in most cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to the VDD pin to reduce sensitivity to transient voltages on the monitored signal.

). If VDDfalls below the negative threshold (V

ITN

). When the reset delay has elapsed, the

RST

ITN

, then RESET is asserted (driven low). When VDDis above

ITN

+ V

HYST

), then RESET is

ITN

, a delay circuit is

HYST

, RESET is deasserted

7.2.1.4 Watchdog Mode

This section provides information for the watchdog mode of operation.

7.2.1.4.1 CWD

The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing options and user-programmable watchdog timing. The TPS3851 features three options for setting the watchdog timer: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time VDDenters the valid region (V is connected to the CWD pin. The sequence of events typically takes 381 μs (t left unconnected, pulled-up through a resistor, or connected to a capacitor. If the CWD pin is being pulled up to VDD, a 10-kΩ resistor is required.

Figure 21. Undervoltage Detection

+ V

ITN

< VDD). The pin evaluation is controlled by an internal state machine that determines which option

HYST

Product Folder Links: TPS3851

) to determine if the CWD pin is

INIT

Page 13

Timing

WDI

WD(MIN)

WD(TYP)

WD(MAX)

WDO

= Tolerance Window

Correct

Operation

WDO

Late Fault

WDI

Valid

Region

TPS3851

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SBVS300 –NOVEMBER 2016

Functional Block Diagram (continued)

7.2.1.4.2 Watchdog Input WDI

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before t If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.

The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in IDD, drive the WDI pin to either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND. Figure 22 shows the valid region for a WDI pulse to be issued to prevent WDO from being triggered and pulled low.

WD(min)

Figure 22. Watchdog Timing Diagram

7.2.1.4.3 Watchdog Output WDO

The TPS3851 features a watchdog timer with an independent watchdog output (WDO). The independent watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an entire system reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO remains low for t When RESET is unasserted, the watchdog timer resumes normal operation.

. When the RESET signal is asserted (low), the WDO pin goes to a high-impedance state.

RST

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Page 14

SET1

VDD

RESET

Watchdog

Enabled/Disabled

Disabled

Enabled

150 µs

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SBVS300 –NOVEMBER 2016

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Functional Block Diagram (continued)

7.2.1.4.4 SET1

The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled and WDI is ignored. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that there is no increase in IDD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be changed dynamically; however, if the watchdog is going from disabled to enabled there is a 150-µs setup time where the watchdog does not respond to changes on WDI, as shown in Figure 23.

Figure 23. Enabling and Disabling the Watchdog

7.3 Device Functional Modes

Table 1 summarises the functional modes of the TPS3851.

Table 1. Device Functional Modes

VDD< V

POR

≤ VDD< V

DD(min)

POR

≤ VDD≤ V

VDD> V VDD> V

ITN ITN

ITN

DD(min)

+ V

(2) (2)

HYST

(1)

(1) Only valid before VDDhas gone above V (2) Only valid after VDDhas gone above V (3) Where t

7.3.1 VDDis Below V

When VDDis less than V

is the time between the falling edges on WDI.

pulse

( VDD< V

POR

, RESET is undefined and can be either high or low. The state of RESET largely

POR

depends on the load that the RESET pin is experiencing.

7.3.2 Above Power-On-Reset, But Less Than V

When the voltage on VDDis less than V (logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the WDI signal that is input to the device.

WDI WDO RESET

--- --- Undefined Ignored High Low Ignored High Low

PULSE

< t > t

ITN

POR

WD(min) WD(min)

+ V

)

(3) (3)

HYST

DD(min)(VPOR

, and greater than or equal to V

DD(min)

≤ VDD< V

High High

Low High

)

DD(min)

, the RESET signal is asserted

POR

7.3.3 Normal Operation (VDD≥ V

When VDDis greater than or equal to V

DD(min)

)

, the RESET signal is determined by VDD. When RESET is asserted,

WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.

Product Folder Links: TPS3851

Page 15

VDD

CWD

Cap

Control

375 nA

CWD

VDD

CWD

10 k

CWD

User Programmable

Capacitor to GND

10 NŸ5HVLVWRU

to VDD

CWD

Unconnected

TPS3851 TPS3851

TPS3851

VDD

Cap

Control

375 nA

VDD

Cap

Control

375 nA

VDD

TPS3851

www.ti.com

SBVS300 –NOVEMBER 2016

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application requirements.

8.1.1 CWD Functionality

The TPS3851 features three options for setting the watchdog timer: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. Figure 24 shows a schematic drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected (high impedance), then the factory-programmed watchdog timeouts are enabled; see the Factory-Programmed

Timing Options section. Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD

pin to ground.

8.1.1.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in Table 2), the CWD pin must either be unconnected or pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, 15% accurate watchdog timing.

Figure 24. CWD Charging Circuit

CWD SET1 MIN TYP MAX

NC 0 Watchdog disabled

NC 1 1360 1600 1840 ms 10 kΩ to VDD 0 Watchdog disabled 10 kΩ to VDD 1 170 200 230 ms

INPUT STANDARD AND EXTENDED TIMING WDT (tWD)

Table 2. Factory Programmed Watchdog Timing

Product Folder Links: TPS3851

UNIT

Page 16

TPS3851

SBVS300 –NOVEMBER 2016

www.ti.com

Application Information (continued)

8.1.1.2 Adjustable Capacitor Timing

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to CWD, then a 375-nA, constant-current source charges C tWDusing Equation 1 and Equation 2 and the SET1 pin. The TPS3851 determines the watchdog timeout with the formulas given in Equation 1 and Equation 2, where C

WD(standard)

WD(extended)

The TPS3851 is designed and tested using C

(ms) = 3.23 x C

(ms) = 77.4 x C

(nF) + 0.381 (ms) (1)

CWD

(nF) + 55 (ms) (2)

CWD

capacitors between 100 pF and 1 µF. Note that Equation 1 and

Equation 2 are for ideal capacitors, capacitor tolerances vary the actual device timing. For the most accurate

timing, use ceramic capacitors with COG dielectric material. If a C to set tWDfor standard timing. Use Equation 2 to calculate tWDfor extended timing. Table 4 shows the minimum and maximum calculated tWDvalues using an ideal capacitor for both the standard and extended timing.

Table 3. Programmable CWD Timing

INPUT STANDARD TIMING WDT (tWD) EXTENDED TIMING WDT (tWD)

CWD SET1 MIN TYP MAX MIN TYP MAX

CWD

(1) Calculated from Equation 1 using an ideal capacitor. (2) Calculated from Equation 2 using an ideal capacitor.

0 Watchdog disabled Watchdog disabled 1 t

× 0.85 t

WD(std)

(1)

WD(std)

CWD

until V

= 1.21 V. Table 3 shows how to calculate

CWD

is in nanofarads and tWDis in milliseconds.

capacitor is used, Equation 1 can be used

CWD

× 1.15 t

× 0.85 t

WD(ext)

(2)

WD(ext)

UNIT

× 1.15 ms

Table 4. tWDValues for Common Ideal Capacitor Values

CWD

100 pF 0.598 0.704 0.809 53.33 62.74 72.15 ms

1 nF 3.069 3.611 4.153 112.5 132.4 152.3 ms

10 nF 27.78 32.68 37.58 704.7 829 953.4 ms

100 nF 274.9 323.4 371.9 6626 7795 8964 ms

1 μF 2746 3230 3715 65837 77455 89073 ms

(1) The minimum and maximum values are calculated using an ideal capacitor.

STANDARD TIMING WDT (tWD) EXTENDED TIMING WDT (tWD)

MIN

(1)

TYP MAX

(1)

MIN

(1)

TYP MAX

(1)

UNIT

Product Folder Links: TPS3851

Page 17

Time

Input Voltage

ITN

ûV1

ûV2

ITN

+ V

HYST

TPS3851

www.ti.com

SBVS300 –NOVEMBER 2016

8.1.2 Overdrive Voltage

Forcing a RESET is dependent on two conditions: the amplitude VDDis beyond the trip point (ΔV1and ΔV2), and the length of time that the voltage is beyond the trip point (t1and t2). If the voltage is just under the trip point for a long period of time, RESET asserts and the output is pulled low. However, if VDDis just under the trip point for a few nanoseconds, RESET does not assert and the output remains high. The length of time required for RESET to assert can be changed by increasing the amount VDDgoes under the trip point. If VDDis under the trip point by 10%, the amount of time required for the comparator to respond is much faster and causes RESET to assert much quicker than when barely under the trip point voltage. Equation 3 shows how to calculate the percentage overdrive.

Overdrive = |( VDD/ V

In Equation 3, V is used. V

is used when VDDis falling below the negative threshold. In Figure 25, t1and t2correspond to the

ITN

amount of time that VDDis over the threshold; the propagation delay versus overdrive for V

– 1) × 100% | (3)

ITX

corresponds to the threshold trip point. If VDDis exceeding the positive threshold, V

ITX

and V

ITN

+ V

HYST

illustrated in Figure 16 and Figure 18, respectively. The TPS3851 is relatively immune to short positive and negative transients on VDD because of the overdrive

voltage curve.

Figure 25. Overdrive Voltage

Product Folder Links: TPS3851

Page 18

RESET

VDD

GND

TPS3851

Microcontroller

SET1

CORE

RESET

GND

WDO

NMI

CWD

WDI GPIORESET

VDD

GND

TPS3890

SENSE MR CT

100 k

2.7 nF

4.7 µF

TPS3851

SBVS300 –NOVEMBER 2016

8.2 Typical Application

Figure 26. Monitoring the Supply Voltage and Watchdog Supervision of a Microcontroller

8.2.1 Design Requirements

PARAMETER DESIGN REQUIREMENT DESIGN RESULT

Watchdog disable for initialization period

Output logic voltage 1.8-V CMOS 1.8V CMOS Monitored rail 1.8 V with a 5% threshold Worst-case V

Watchdog timeout 10 ms typical Maximum device current

consumption

(1) Only includes the TPS3851G18S current consumption.

Watchdog must remain disabled for 5 seconds until logic enables the watchdog timer

50 µA 37 µA when RESET or WDO is asserted

5.02 seconds (typ)

= 7.3 ms, t

WD(min)

= 1.714 V – 4.7%

ITN

WD(TYP)

= 9.1 ms, t

www.ti.com

WD(max)

(1)

= 11

8.2.2 Detailed Design Procedure

8.2.2.1 Monitoring the 1.8-V Rail

The undervoltage comparator allows for precise voltage supervision of common rails between 1.8 V and 5.0 V. This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure this requirement is met, the TPS3851G18S was chosen for its –4% threshold. To calculate the worst-case for V

, the accuracy must also be taken into account. The worst-case for V

ITN

ITN(Worst Case)

= V

x 0.992 = 1.8 x 0.96 x 0.992 = 1.714 V (4)

ITN(typ)

Product Folder Links: TPS3851

can be calculated by Equation 4:

ITN

Page 19

RESET

CONTROL

TPS3851

www.ti.com

SBVS300 –NOVEMBER 2016

8.2.2.2 Calculating RESET and WDO Pullup Resistor

The TPS3851 uses an open-drain configuration for the RESET circuit, as shown in Figure 27. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOLis below the maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (I

RESET

and VOL. The maximum VOLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.4 V with I resistor must be chosen to keep I

below 50 μA because this value is the maximum consumption current

RESET

kept below 10 mA. For this example, with a VPUof 1.8 V, a

RESET

allowed. To ensure this specification is met, a pullup resistor value of 100 kΩ was selected, which sinks a maximum of 18 μA when RESET or WDO is asserted. As illustrated in Figure 13, the RESET current is at 18 μA and the low-level output voltage is approximately zero.

Figure 27. RESET Open-Drain Configuration

8.2.2.3 Setting the Watchdog

As illustrated in Figure 24 there are three options for setting the watchdog timer. The design specifications in this application require the programmable timing option (external capacitor connected to CWD). When a capacitor is connected to the CWD pin, the watchdog timer is governed by Equation 1 for the standard timing version. Note that only the standard version is capable of meeting this timing requirement. Equation 1 is only valid for ideal capacitors, any temperature or voltage derating must be accounted for separately.

(nF) = (tWD(ms) – 0.0381) / 3.23 = (10 – 0.381) / 3.23 = 2.97 nF (5)

CWD

The nearest standard capacitor value to 2.9 nF is 2.7 nF. Selecting 2.7 nF for the C

capacitor gives the

CWD

following minimum timing parameters:

= 0.85 x t

WD(MIN)

WD(MAX)

= 1.15 x t

Capacitor tolerance also influences t

= 0.85 x (3.23 x 2.7 + 0.381) = 7.73 ms (6)

WD(TYP)

= 1.15 x (3.23 x 2.7 + 0.381) = 10.46 ms (7)

WD(TYP)

WD(MIN)

and t

WD(MAX)

. Select a ceramic COG dielectric capacitor for high accuracy. For 2.7 nF, COG capacitors are readily available with 5% tolerances. This selection results in a 5% decrease in t

WD(MIN)

functionality, a falling edge must be issued before t

and a 5% increase in t

WD(MAX)

, giving 7.34 ms and 11 ms, respectively. To ensure proper

. Figure 29 illustrates that a WDI signal with a period of

WD(min)

5 ms keeps WDO from asserting.

Product Folder Links: TPS3851

Page 20

VDD

500mV/div

WDO

2V/div

RESET

2V/div

2µs/div

6µs

VDD

500mV/div

WDO

2V/div

RESET

2V/div

50ms/div

195 ms

RESET

2V/div

WDO

2V/div

WDI

2V/div

VDD

2V/div

2ms/div

5ms

RESET

2V/div

WDO

2V/div

SET1

2V/div

VDD

2V/div

1s/div

6 seconds

TPS3851

SBVS300 –NOVEMBER 2016

www.ti.com

8.2.2.4 Watchdog Disabled During Initialization Period

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3851. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a TPS3890 supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that the RESET on the TPS3890 stays low until VDDrises above V

. When VDD comes up, the delay time can be adjusted

ITN

through the CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7-μF capacitor from CT to GND, the typical delay time is 5 seconds. Figure 28 shows that when the watchdog is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO begins to assert. See the TPS3890 data sheet for detailed information on the TPS3890.

8.2.3 Glitch Immunity

Figure 31 shows the high-to-low glitch immunity for the TPS3851G18S with a 7% overdrive with VDDstarting at

1.8 V. This curve shows that VDDcan go below the threshold for at least 6 µs before RESET asserts.

8.2.4 Application Curves

Unless otherwise stated, application curves were taken at TA= 25°C.

Figure 28. Startup Without a WDI Signal

Figure 30. Typical RESET Delay

Figure 29. Typical WDI Signal

Figure 31. High-to-Low Glitch Immunity

Product Folder Links: TPS3851

Page 21

VDD

CWD

GND

WDO

WDI

SET1

GND Plane

RESET

Vin

PU2

VDD

CWD

Vin

PU1

Vin

Denotes a via

TPS3851

www.ti.com

SBVS300 –NOVEMBER 2016

9 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.

10 Layout

10.1 Layout Guidelines

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

• If a C

the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

• Place the pullup resistors on RESET and WDO as close to the pin as possible.

10.2 Layout Example

capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If

CWD

Figure 32. TPS3851 Recommended Layout

Product Folder Links: TPS3851

Page 22

TPS3851

SBVS300 –NOVEMBER 2016

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 5. Device Nomenclature

DESCRIPTION NOMENCLATURE VALUE

TPS3851

(high-accuracy supervisor with watchdog)

(nominal threshold as a percent of the nominal

monitored voltage)

yy(y)

(nominal monitored voltage option)

(nominal watchdog timeout period)

www.ti.com

— —

G V H V

18 1.8 V 25 2.5 V 30 3.0 V 33 3.3 V 50 5.0 V

S tWD(ms) = 3.23 x CWD(nF) + 0.381 (ms) E tWD(ms) = 77.4 x CWD(nF) + 55.2 (ms)

ITN

= –4% = –7%

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay (SLVSD65)

• TPS3851EVM-780 Evaluation Module (SBVU033)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Product Folder Links: TPS3851

Page 23

TPS3851

www.ti.com

SBVS300 –NOVEMBER 2016

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: TPS3851

Page 24

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

TPS3851G18EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851DD

TPS3851G18EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851DD

TPS3851G18SDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851DC

TPS3851G18SDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851DC

TPS3851G25EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851ED

TPS3851G25EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851ED

TPS3851G30EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851FD

TPS3851G30EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851FD

TPS3851G33EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851GD

TPS3851G33EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851GD

TPS3851G33SDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851GC

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

10-Dec-2020

Samples

(4/5)

TPS3851G33SDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851GC

TPS3851G50EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851HD

TPS3851G50EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851HD

TPS3851G50SDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851HC

TPS3851G50SDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851HC TPS3851H18EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851LD TPS3851H18EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851LD TPS3851H25EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851MD TPS3851H25EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851MD

Addendum-Page 1

Page 25

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TPS3851H30EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851ND TPS3851H30EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851ND TPS3851H33EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851PD TPS3851H33EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851PD TPS3851H50EDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851RD TPS3851H50EDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 851RD

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

10-Dec-2020

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Samples

Addendum-Page 2

Page 26

PACKAGE OPTION ADDENDUM

www.ti.com

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3851 :

Automotive: TPS3851-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

Page 27

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TPS3851G18EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G18EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G18SDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G18SDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G25EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G25EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G30EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G30EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G33EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G33EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G33SDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G33SDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G50EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G50EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G50SDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851G50SDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H18EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H18EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 28

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2018

Device Package

Type

TPS3851H25EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H25EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H30EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H30EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H33EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H33EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H50EDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS3851H50EDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS3851G18EDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G18EDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G18SDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G18SDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G25EDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G25EDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G30EDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G30EDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G33EDRBR SON DRB 8 3000 367.0 367.0 35.0

Pack Materials-Page 2

Page 29

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2018

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS3851G33EDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G33SDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G33SDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G50EDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G50EDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851G50SDRBR SON DRB 8 3000 367.0 367.0 35.0 TPS3851G50SDRBT SON DRB 8 250 210.0 185.0 35.0 TPS3851H18EDRBR SON DRB 8 3000 367.0 367.0 35.0

TPS3851H18EDRBT SON DRB 8 250 210.0 185.0 35.0

TPS3851H25EDRBR SON DRB 8 3000 367.0 367.0 35.0

TPS3851H25EDRBT SON DRB 8 250 210.0 185.0 35.0

TPS3851H30EDRBR SON DRB 8 3000 367.0 367.0 35.0

TPS3851H30EDRBT SON DRB 8 250 210.0 185.0 35.0

TPS3851H33EDRBR SON DRB 8 3000 367.0 367.0 35.0

TPS3851H33EDRBT SON DRB 8 250 210.0 185.0 35.0

TPS3851H50EDRBR SON DRB 8 3000 367.0 367.0 35.0

TPS3851H50EDRBT SON DRB 8 250 210.0 185.0 35.0

Pack Materials-Page 3

Page 30

Page 31

PACKAGE OUTLINE

PIN 1 INDEX AREA

1 MAX

0.05

0.00

EXPOSED

THERMAL PAD

SCALE 4.000

3.1

2.9

1.5 0.1 4X (0.23)

3.1

2.9

VSON - 1 mm max heightDRB0008A

PLASTIC SMALL OUTLINE - NO LEAD

SEATING PLANE

0.08 C

DIM A

OPT 1

(0.1) (0.2)

(DIM A) TYP

OPT 2

1.95

6X 0.65

(OPTIONAL)

PIN 1 ID

(0.65)

1.75 0.1

0.37

0.25

0.5

0.3

0.1 C A B

0.05

4218875/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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Page 32

8X (0.6)

8X (0.31)

EXAMPLE BOARD LAYOUT

VSON - 1 mm max heightDRB0008A

PLASTIC SMALL OUTLINE - NO LEAD

(1.5)

(0.65)

SYMM

(0.825)

6X (0.65)

(R0.05) TYP

( 0.2) VIA TYP

SOLDER MASK OPENING

SYMM

(0.23)

0.07 MAX ALL AROUND

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

(0.5)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

EXPOSED METAL

METAL UNDER

SOLDER MASK

(1.75)

(0.625)

0.07 MIN ALL AROUND

EXPOSED METAL

SOLDER MASK OPENING

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218875/A 01/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

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Page 33

8X (0.6)

EXAMPLE STENCIL DESIGN

VSON - 1 mm max heightDRB0008A

PLASTIC SMALL OUTLINE - NO LEAD

(0.65)

4X (0.23)

SYMM

METAL TYP

(0.725)

8X (0.31)

SYMM

6X (0.65)

(R0.05) TYP

(1.34)

(2.8)

(2.674)

(1.55)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

84% PRINTED SOLDER COVERAGE BY AREA

EXPOSED PAD

SCALE:25X

4218875/A 01/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

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Page 34

IMPORTANT NOTICE AND DISCLAIMER

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet TPS3851 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Timing Requirements

6.7 Typical Characteristics

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.2.1 Feature Description

7.2.1.1 RESET

7.2.1.2 Manual Reset MR

7.2.1.3 UV Fault Detection

7.2.1.4 Watchdog Mode

7.3 Device Functional Modes

8 Application and Implementation

8.1 Application Information

8.1.1 CWD Functionality

8.1.1.1 Factory-Programmed Timing Options

8.1.1.2 Adjustable Capacitor Timing

8.1.2 Overdrive Voltage

8.2 Typical Application

8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 Monitoring the 1.8-V Rail

8.2.2.2 Calculating RESET and WDO Pullup Resistor

8.2.2.3 Setting the Watchdog

8.2.2.4 Watchdog Disabled During Initialization Period

8.2.3 Glitch Immunity

8.2.4 Application Curves

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

11.2 Documentation Support

11.2.1 Related Documentation

11.3 Receiving Notification of Documentation Updates

11.4 Community Resources

11.5 Trademarks

11.6 Electrostatic Discharge Caution

11.7 Glossary

12 Mechanical, Packaging, and Orderable Information