Datasheet TPA3110D2PWPR Specification

LINP

LINN

RINP

RINN

SDSD

FaultFault

PLIMIT

PBTL

PVCC

8to26V

1 Fm

OUTNL

FERRITE

BEAD

FILTER

OUTPL

15W

FERRITE

BEAD

FILTER

FERRITE

BEAD

FILTER

8W

OUTR+

OUTR-

OUTL-

OUTL+

Audio Source

TPA3110D2

GAIN0 GAIN1

OUTNR

FERRITE

BEAD

FILTER

OUTPR

15W

8W

FERRITE

BEAD

FILTER

FERRITE

BEAD

FILTER

www.ti.com

....................................................................................................................................................................................................... SLOS528 – JULY 2009

15-W FILTER-FREE STEREO CLASS-D AUDIO POWER AMPLIFIER with

SPEAKERGUARD™

1

FEATURES APPLICATIONS

2

• 15-W/ch into an 8- Ω Loads at 10% THD+N

From a 16-V Supply

• 10-W/ch into 8- Ω Loads at 10% THD+N From a

13-V Supply

• 30-W into a 4- Ω Mono Load at 10% THD+N

From a 16-V Supply

• 90% Efficient Class-D Operation Eliminates

Need for Heat Sinks

• Wide Supply Voltage Range Allows Operation

from 8 V to 26 V

• Filter-Free Operation

• SpeakerGuard™ Speaker Protection Includes

Adjustable Power Limiter plus DC Protection

• Flow Through Pin Out Facilitates Easy Board

Layout

• Robust Pin-to-Pin Short Circuit Protection and

Thermal Protection with Auto Recovery Option

• Excellent THD+N / Pop-Free Performance

• Four Selectable, Fixed Gain Settings

• Differential Inputs

TPA3110D2

• Televisions

• Consumer Audio Equipment

DESCRIPTION

The TPA3110D2 is a 15-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a " virtual " voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3110D2 can drive stereo speakers as low as 4 Ω . The high efficiency of the TPA3110D2, 90%, eliminates the need for an external heat sink when playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an auto-recovery feature.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SpeakerGuard, PowerPad are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Figure 1. TPA3110D2 Simplified Application Schematic

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

T T T

R

ESD Electrostatic discharge

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) The TPA3110D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

(3) In accordance with JEDEC Standard 22, Test Method A114-B. (4) In accordance with JEDEC Standard 22, Test Method C101-A

Supply voltage AVCC, PVCC – 0.3 V to 30 V

CC

SD, GAIN0, GAIN1, PBTL, FAULT – 0.3 V to V

Interface pin voltage PLIMIT – 0.3 V to GVDD + 0.3 V

I

RINN, RINP, LINN, LINP – 0.3 V to 6.3 V Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range – 40 ° C to 85 ° C

A

Operating junction temperature range

J

Storage temperature range – 65 ° C to 150 ° C

stg

(2)

BTL: PVCC > 15 V 4.8 Minimum Load Resistance BTL: PVCC ≤ 15 V 3.2

L

PBTL 3.2

Human body model

Charged-device model

(3)

(all pins) ± 2 kV

(4)

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

(1)

UNIT

– 40 ° C to 150 ° C

(all pins) ± 500 V

+ 0.3 V

CC

DISSIPATION RATINGS

PACKAGE

28 pin TSSOP (PWP) 4.48 W 27.87 ° C/W 2.33 W 0.72 ° C/W 0.45 ° C/W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(1)

TA≤ 25 ° C DERATING FACTOR ( θJA) TA= 85 ° C θ

JP

Ψ

JT

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

V V V V I I T

Supply voltage PVCC, AVCC 8 26 V

CC

High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V

IH

Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V

IL

Low-level output voltage FAULT, R

OL

High-level input current SD, GAIN0, GAIN1, PBTL, VI= 2V, V

IH

Low-level input current SD, GAIN0, GAIN1, PBTL, VI= 0.8 V, V

IL

Operating free-air temperature – 40 85 ° C

A

=100k, VCC=26V 0.8 V

PULL-UP

= 18 V 50 µ A

CC

= 18 V 5 µ A

CC

Product Folder Link(s) :TPA3110D2

www.ti.com

....................................................................................................................................................................................................... SLOS528 – JULY 2009

DC CHARACTERISTICS

TA= 25 ° C, V

| V

| VI= 0 V, Gain = 36 dB 1.5 15 mV

OS

I

CC

I

CC(SD)

r

DS(on)

G Gain

t

on

t

OFF

GVDD Gate Drive Supply I t

DCDET

= 24 V, RL= 8 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage (measured differentially)

Quiescent supply current SD = 2 V, no load, PV Quiescent supply current in shutdown mode SD = 0.8 V, no load, PV

V

= 12 V, IO= 500 mA,

Drain-source on-state resistance m Ω

CC

TJ= 25 ° C

GAIN1 = 0.8 V dB

GAIN1 = 2 V dB

= 24V 32 50 mA

CC

= 24V 250 400 µ A

CC

High Side 240 Low side 240 GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33

GAIN0 = 2 V 35 36 37 Turn-on time SD = 2 V 14 ms Turn-off time SD = 0.8 V 2 µ s

= 100 µ A 6.4 6.9 7.4 V

GVDD

DC Detect time V

= 6V, VRINP = 0V 420 ms

(RINN)

DC CHARACTERISTICS

TA= 25 ° C, V

| V

| VI= 0 V, Gain = 36 dB 1.5 15 mV

OS

I

CC

I

CC(SD)

r

DS(on)

G Gain

t

ON

t

OFF

GVDD Gate Drive Supply I V

O

= 12 V, RL= 8 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage (measured differentially)

Quiescent supply current SD = 2 V, no load, PV Quiescent supply current in shutdown mode SD = 0.8 V, no load, PV

V

= 12 V, IO= 500 mA,

Drain-source on-state resistance m Ω

CC

TJ= 25 ° C

GAIN1 = 0.8 V dB

GAIN1 = 2 V dB

= 12V 20 35 mA

CC

= 12V 200 µ A

CC

High Side 240

Low side 240

GAIN0 = 0.8 V 19 20 21

GAIN0 = 2 V 25 26 27

GAIN0 = 0.8 V 31 32 33

GAIN0 = 2 V 35 36 37 Turn-on time SD = 2 V 14 ms Turn-off time SD = 0.8 V 2 µ s

= 2mA 6.4 6.9 7.4 V

GVDD

Output Voltage maximum under PLIMIT control

V

= 2 V; VI= 1V rms 6.75 7.90 8.75 V

(PLIMIT)

TPA3110D2

Product Folder Link(s) :TPA3110D2

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

AC CHARACTERISTICS

TA= 25 ° C, V

K

SVR

P

O

THD+N Total harmonic distortion + noise V

V

n

SNR Signal-to-noise ratio 102 dB f

OSC

= 24 V, RL= 8 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power Supply ripple rejection – 70 dB

200 mV Gain = 20 dB, Inputs ac-coupled to AGND

Continuous output power THD+N = 10%, f = 1 kHz, V

CC

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

ripple at 1 kHz,

PP

= 16 V 15 W

CC

= 16 V, f = 1 kHz, PO= 7.5 W (half-power) 0.1 %

65 µ V

– 80 dBV

Crosstalk VO= 1 Vrms, Gain = 20 dB, f = 1 kHz – 100 dB

Maximum output at THD+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted Oscillator frequency 250 310 350 kHz Thermal trip point 150 ° C Thermal hysteresis 15 ° C

AC CHARACTERISTICS

TA= 25 ° C, V

K

SVR

P

O

THD+N Total harmonic distortion + noise RL= 8 Ω , f = 1 kHz, PO= 5 W (half-power) 0.06 %

V

n

SNR Signal-to-noise ratio 102 dB f

OSC

= 12 V, RL= 8 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply ripple rejection – 70 dB

200 mV

Gain = 20 dB, Inputs ac-coupled to AGND Continuous output power THD+N = 10%, f = 1 kHz; V

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

ripple from 20 Hz – 1 kHz,

PP

= 13 V 10 W

CC

65 µ V

– 80 dBV

Crosstalk Po= 1 W, Gain = 20 dB, f = 1 kHz – 100 dB

Maximum output at THD+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted Oscillator frequency 250 310 350 kHz Thermal trip point 150 ° C Thermal hysteresis 15 ° C

www.ti.com

Product Folder Link(s) :TPA3110D2

www.ti.com

....................................................................................................................................................................................................... SLOS528 – JULY 2009

PIN FUNCTIONS

NAME Pin #

SD 1 I

FAULT 2 O

LINP 3 I Positive audio input for left channel. Biased at 3V. LINN 4 I Negative audio input for left channel. Biased at 3V. GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. AVCC 7 P Analog supply AGND 8 P Analog signal ground. Connect to the thermal pad.

GVDD 9 O

PLIMIT 10 I RINN 11 I Negative audio input for right channel. Biased at 3V.

RINP 12 I Positive audio input for right channel. Biased at 3V. NC 13 P Not connected PBTL 14 I Parallel BTL mode switch

PVCCR 15 P

PVCCR 16 P BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.

OUTPR 18 O Class-D H-bridge positive output for right channel. PGND 19 Power ground for the H-bridges. OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high-side FET. BSNL 22 I Bootstrap I/O for left channel, negative high-side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. PGND 24 Power ground for the H-bridges. OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.

PVCCL 27 P

PVCCL 28 P

I/O/P DESCRIPTION

Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.

Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC.

High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for PLIMIT function

Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.

Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.

Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.

TPA3110D2

Product Folder Link(s) :TPA3110D2

PWM Logic

Gate Drive

PVCCL

GVDD

PVCCL

BSPL

PGND

OUTPL

OUTNL

PGND

GVDD

BSNL

PWM

Logic

Gate Drive

PVCCL

GVDD

PVCCL

BSNR

PGND

OUTNR

OUTPR

PGND

GVDD

BSPR

LINP

LINN

RINP

RINN

UVLO/OVLO

SC Detect

DC Detect

Thermal

Detect

Startup Protection

Logic

Biases and References

FAULT

SD

GAIN0

PLIMIT

AGND

AVCC

GAIN1

Gain

Control

TTL

Buffer

Ramp

Generator

AVDD

GVDD

LDO

Regulator

Gain

Control

PLIMIT

Reference

PBTL

Gain

Control

TTL

Buffer

PBTL

Select

PBTL Select

OUTPL FB

OUTNL FB

OUTNN FB

OUTNP FB

OUTPR FB

OUTNR FB

OUTNL FB

OUTPL FB

PLIMIT

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

www.ti.com

Product Folder Link(s) :TPA3110D2

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G001

PO = 0.5 W

PO = 5 W

PO = 2.5 W

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G002

PO = 1 W

PO = 10 W

PO = 5 W

Gain = 20 dB VCC = 18 V ZL = 8 Ω + 66 µH

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G003

PO = 1 W

PO = 10 W

PO = 5 W

Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G004

PO = 0.5 W

PO = 5 W

PO = 2.5 W

Gain = 20 dB VCC = 12 V ZL = 6 Ω + 47 µH

TPA3110D2

www.ti.com

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is

....................................................................................................................................................................................................... SLOS528 – JULY 2009

TYPICAL CHARACTERISTICS

available at ti.com.)

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs vs

FREQUENCY (BTL) FREQUENCY (BTL)

Figure 2. Figure 3.

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs vs

FREQUENCY (BTL) FREQUENCY (BTL)

Figure 4. Figure 5.

Product Folder Link(s) :TPA3110D2

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G005

PO = 10 W

PO = 5 W

Gain = 20 dB VCC = 18 V ZL = 6 Ω + 47 µH

PO = 1 W

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G006

PO = 1 W

PO = 5 W

PO = 10 W

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G007

f = 1 kHz

f = 10 kHz

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH

f = 20 Hz

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G008

f = 1 kHz

Gain = 20 dB VCC = 18 V ZL = 8 Ω + 66 µH

f = 20 Hz

f = 10 kHz

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

www.ti.com

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs vs

FREQUENCY (BTL) FREQUENCY (BTL)

Figure 6. Figure 7.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER (BTL) OUTPUT POWER (BTL)

Figure 8. Figure 9.

Product Folder Link(s) :TPA3110D2

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G009

f = 20 Hz

f = 10 kHz

f = 1 kHz

Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G010

f = 1 kHz

f = 10 kHz

Gain = 20 dB VCC = 12 V ZL = 6 Ω + 47 µH

f = 20 Hz

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G011

f = 1 kHz

Gain = 20 dB VCC = 18 V ZL = 6 Ω + 47 µH

f = 20 Hz

f = 10 kHz

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G012

f = 20 Hz

f = 10 kHz

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH

f = 1 kHz

TPA3110D2

www.ti.com

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

....................................................................................................................................................................................................... SLOS528 – JULY 2009

TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER (BTL) OUTPUT POWER (BTL)

Figure 10. Figure 11.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER (BTL) OUTPUT POWER (BTL)

Figure 12. Figure 13.

Product Folder Link(s) :TPA3110D2

V

PLIMIT

− PLIMIT Voltage − V

0

5

10

15

20

25

30

35

0 1 2 3 4 5 6

P

O

− Output Power − W

G014

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH

V

PLIMIT

− PLIMIT Voltage − V

0

2

4

6

8

10

12

14

16

0.0 0.5 1.0 1.5 2.0 2.5 3.0

P

O(Max)

− Maximum Output Power − W

G013

Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH

f − Frequency − Hz

Phase − °

100

50

0

−300

0

5

10

15

20

25

30

35

40

Gain − dB

−50

−100

−150

20 100 10k 100k

1k

G015

Phase

Gain

−200

−250

CI = 1 µF Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 12 V VI = 0.1 Vrms ZL = 8 Ω + 66 µH

VCC − Supply Voltage − V

0

5

10

15

20

25

30

6 8 10 12 14 16 18 20 22 24 26

P

O

− Output Power − W

G016

THD = 10%

THD = 1%

Gain = 20 dB ZL = 8 Ω + 66 µH

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

www.ti.com

MAXIMUM OUTPUT POWER OUTPUT POWER

vs vs

PLIMIT VOLTAGE (BTL) PLIMIT VOLTAGE (BTL)

Figure 14.

Note: Dashed Lines represent thermally limited regions.

Figure 15.

GAIN/PHASE OUTPUT POWER

FREQUENCY (BTL) SUPPLY VOLTAGE (BTL)

vs vs

Figure 16.

Product Folder Link(s) :TPA3110D2

Note: Dashed Lines represent thermally limited regions.

Figure 17.

VCC − Supply Voltage − V

0

5

10

15

20

25

6 8 10 12 14 16 18

P

O

− Output Power − W

G017

THD = 10%

THD = 1%

Gain = 20 dB ZL = 4 Ω + 33 µH

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25 30 35 40

η − Efficiency − %

G018

VCC = 12 V

VCC = 18 V

VCC = 24 V

Gain = 20 dB ZL = 8 Ω + 66 µH

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25

η − Efficiency − %

G032

VCC = 12 V

VCC = 18 V

VCC = 24 V

Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 8 Ω

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25

η − Efficiency − %

G019

VCC = 12 V

VCC = 18 V

Gain = 20 dB ZL = 6 Ω + 47 µH

TPA3110D2

www.ti.com

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

....................................................................................................................................................................................................... SLOS528 – JULY 2009

TYPICAL CHARACTERISTICS (continued)

OUTPUT POWER EFFICIENCY

vs vs

SUPPLY VOLTAGE (BTL) OUTPUT POWER (BTL)

Note: Dashed Lines represent thermally Note: Dashed Lines represent thermally limited regions. limited regions.

Figure 18. Figure 19.

EFFICIENCY EFFICIENCY

vs vs

OUTPUT POWER (BTL with LC FILTER) OUTPUT POWER (BTL)

Figure 20.

Note: Dashed Lines represent thermally limited regions.

Product Folder Link(s) :TPA3110D2

Figure 21.

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25

η − Efficiency − %

G033

VCC = 12 V

VCC = 18 V

Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 6 Ω

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 3 6 9 12 15 18

η − Efficiency − %

G020

VCC = 12 V

Gain = 20 dB ZL = 4 Ω + 33 µH

P

O(Tot)

− Total Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

0 5 10 15 20 25 30 35 40

I

CC

− Supply Current − A

G021

VCC = 12 V

VCC = 18 V

VCC = 24 V

Gain = 20 dB ZL = 8 Ω + 66 µH

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25

η − Efficiency − %

G034

VCC = 12 V

Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 4 Ω

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

EFFICIENCY EFFICIENCY

vs vs

OUTPUT POWER (BTL with LC FILTER) OUTPUT POWER (BTL)

www.ti.com

OUTPUT POWER (BTL with LC FILTER) TOTAL OUTPUT POWER (BTL)

EFFICIENCY SUPPLY CURRENT

Figure 22. Figure 23.

vs vs

Figure 24.

Note: Dashed Lines represent thermally limited regions.

Figure 25.

Product Folder Link(s) :TPA3110D2

P

O(Tot)

− Total Output Power − W

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

0 5 10 15 20 25 30

I

CC

− Supply Current − A

G022

VCC = 12 V

Gain = 20 dB ZL = 4 Ω + 33 µH

−130

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

f − Frequency − Hz

Crosstalk − dB

20 100 1k 10k 20k

G023

Left to Right

Right to Left

Gain = 20 dB VCC = 12 V VO = 1 Vrms ZL = 8 Ω + 66 µH

−120

−100

−80

−60

−40

−20

0

f − Frequency − Hz

K

SVR

− Supply Ripple Rejection Ratio − dB

20 100 1k 10k 20k

G024

Gain = 20 dB V

ripple

= 200 mV

pp

ZL = 8 Ω + 66 µH

VCC = 12 V

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G025

PO = 0.5 W

PO = 5 W

PO = 2.5 W

Gain = 20 dB VCC = 24 V ZL = 4 Ω + 33 µH

TPA3110D2

www.ti.com

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

....................................................................................................................................................................................................... SLOS528 – JULY 2009

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT CROSSTALK

TOTAL OUTPUT POWER (BTL) FREQUENCY (BTL)

Note: Dashed Lines represent thermally limited regions.

vs vs

Figure 27.

Figure 26.

SUPPLY RIPPLE REJECTION RATIO TOTAL HARMONIC DISTORTION

FREQUENCY (BTL) FREQUENCY (PBTL)

Figure 28. Figure 29.

vs vs

Product Folder Link(s) :TPA3110D2

f − Frequency − Hz

Phase − °

100

50

0

−300

0

5

10

15

20

25

30

35

40

Gain − dB

−50

−100

−150

20 100 10k 100k

1k

G027

Phase

Gain

−200

−250

CI = 1 µF Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 24 V VI = 0.1 Vrms ZL = 8 Ω + 66 µH

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

50

0.01

1

G026

f = 20 Hz

f = 10 kHz

f = 1 kHz

Gain = 20 dB VCC = 24 V ZL = 4 Ω + 33 µH

VCC − Supply Voltage − V

0

5

10

15

20

25

30

35

40

6 8 10 12 14 16 18 20

P

O

− Output Power − W

G028

THD = 10%

THD = 1%

Gain = 20 dB ZL = 4 Ω + 33 µH

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25 30 35 40 45

η − Efficiency − %

G029

Gain = 20 dB ZL = 4 Ω + 33 µH

VCC = 12 V

VCC = 18 V

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

www.ti.com

TOTAL HARMONIC DISTORTION + NOISE GAIN/PHASE

vs vs

OUTPUT POWER (PBTL) FREQUENCY (PBTL)

Figure 30. Figure 31.

OUTPUT POWER EFFICIENCY

vs vs

SUPPLY VOLTAGE (PBTL) OUTPUT POWER (PBTL)

Note: Dashed Lines represent thermally limited regions.

Figure 32.

Product Folder Link(s) :TPA3110D2

Figure 33.

PO − Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

0 5 10 15 20 25 30 35 40 45

I

CC

− Supply Current − A

G030

VCC = 12 V

Gain = 20 dB ZL = 4 Ω + 33 µH

VCC = 18 V

−120

−100

−80

−60

−40

−20

0

f − Frequency − Hz

K

SVR

− Supply Ripple Rejection Ratio − dB

20 100 1k 10k 20k

G031

Gain = 20 dB V

ripple

= 200 mV

pp

ZL = 8 Ω + 66 µH

VCC = 12 V

TPA3110D2

www.ti.com

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is available at ti.com.)

....................................................................................................................................................................................................... SLOS528 – JULY 2009

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT SUPPLY RIPPLE REJECTION RATIO

vs vs

OUTPUT POWER (PBTL) FREQUENCY (PBTL)

Figure 34. Figure 35.

Product Folder Link(s) :TPA3110D2

TPA3110D2PowerLimitFunction

Vin=1.13 Freq=1kHzRLoad=8WV

PP

PLIMIT =1.8VPout=5W

PLIMIT =3VPout=10W

PLIMIT =6.96VPout=11.8W

Vinput

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

DEVICE INFORMATION

Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3110D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside

the amplifier. This causes the input impedance (Z are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ± 20% due to shifts in the actual resistance of the input resistors.

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 7.2 k Ω , which is the absolute minimum input impedance of the TPA3110D2. At the lower gain settings, the input impedance could increase as high as 72 k Ω

GAIN1 GAIN0

0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9

) to be dependent on the gain setting. The actual gain settings

I

Table 1. Gain Setting

AMPLIFIER GAIN (dB)

TYP TYP

INPUT IMPEDANCE

(k Ω )

www.ti.com

SD OPERATION

The TPA3110D2 employs a shutdown mode of operation designed to reduce supply current (I minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage.

) to the absolute

CC

PLIMIT

The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Also add a 1 µ F capacitor from pin 10 to ground.

Figure 36. PLIMIT Circuit Operation

Product Folder Link(s) :TPA3110D2

L

P

L S

OUT

L

2

R

x V

R + 2 x R

P = for unclipped power

2 x R

æ ö

ç ÷

è ø

TPA3110D2

www.ti.com

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a " virtual " voltage rail which is lower than the supply connected to PVCC. This " virtual " rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

Where:

....................................................................................................................................................................................................... SLOS528 – JULY 2009

R

is the total series resistance including R

S

R

is the load resistance.

L

V

is the peak amplitude of the output possible within the supply rail.

P

V

= 4 × PLIMIT voltage if PLIMIT < 4 × V

P

(10%THD) = 1.25 × P

OUT

(unclipped)

OUT

, and any resistance in the output filter.

DS(on)

P

Table 2. PLIMIT Typical Operation

Test Conditions () PLIMIT Voltage Output Power (W)

PVCC=24V, Vin=1Vrms, 6.97 36.1 (thermally limited) 43

RL=8 Ω , Gain=26dB

PVCC=24V, Vin=1Vrms, 2.94 15 25.2

RL=8 Ω , Gain=26dB

PVCC=24V, Vin=1Vrms, 2.34 10 20

RL=8 Ω , Gain=26dB

PVCC=24V, Vin=1Vrms, 1.62 5 14

RL=8 Ω , Gain=26dB

PVCC=24V, Vin=1Vrms, 6.97 12.1 27.7

RL=8 Ω , Gain=20dB

PVCC=24V, Vin=1Vrms, 3.00 10 23

RL=8 Ω , Gain=20dB

PVCC=24V, Vin=1Vrms, 1.86 5 14.8

RL=8 Ω , Gain=20dB

PVCC=12V, Vin=1Vrms, 6.97 10.55 23.5

RL=8 Ω , Gain=20dB

PVCC=12V, Vin=1Vrms, 1.76 5 15

RL=8 Ω , Gain=20dB

Output Voltage

Amplitude (V

P-P

)

(1)

GVDD Supply

The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT voltage divider circuit. Add a 1 µ F capacitor to ground at this pin.

DC Detect

TPA3110D2 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will NOT clear a DC detect fault.

A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example, +57%, -43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.

Product Folder Link(s) :TPA3110D2

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

The minimum differential input voltages required to trigger the DC detect are show in table 2. The inputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.

Table 3. DC Detect Threshold

AV(dB) Vin (mV, differential)

20 112 26 56 32 28 36 17

PBTL Select

TPA3110D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. For an example of the PBTL connection, see the schematic in the APPLICATION INFORMATION section.

For normal BTL operation, connect the PBTL pin to local ground.

SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

TPA3110D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state.

If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit protection latch.

www.ti.com

THERMAL PROTECTION

Thermal protection on the TPA3110D2 prevents damage to the device when the internal die temperature exceeds 150 ° C. There is a ± 15 ° C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15 ° C. The device begins normal operation at this point with no external system interaction.

Thermal protection faults are NOT reported on the FAULT terminal.

Product Folder Link(s) :TPA3110D2

PVCC

GAIN1

6

AVCC

7

8

AGND

9

GVDD

OUTN

BSN

BSP

OUTP

23

22

21

20

TPA3110D2

FAULT

2

LINP

3

4

LINN

5

GAIN0

PVCC

BSN

OUTN

PGND

27

26

25

24

PLIMIT

10

RINN

11

12

RINP

13

NC

PGND

OUTP

BSP

PVCC

19

18

17

16

PBTL

14

PVCC

15

GND

29

PowerPAD

SD

1

PVCC

28

PVCC

100 μF 0.1 μF

1000 pF

100 μF

0.1 μF

1000 pF

Audio

Source

Control

System

100 kΩ

10 Ω

1 kΩ

FB

0.22 μF

1000 pF

0.22 μF

1000 pF

1 Fm

0.22 μF

FB

1000 pF

0.22 μF

10 kΩ

1 Fm

TPA3110D2

www.ti.com

....................................................................................................................................................................................................... SLOS528 – JULY 2009

APPLICATION INFORMATION

Figure 37. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs

Product Folder Link(s) :TPA3110D2

PVCC

GAIN1

6

AVCC

7

8

AGND

9

GVDD

OUTN

BSN

BSP

OUTP

23

22

21

20

TPA3110D2

FAULT

2

LINP

3

4

LINN

5

GAIN0

PVCC

BSN

OUTN

PGND

27

26

25

24

PLIMIT

10

RINN

11

12

RINP

13

NC

PGND

OUTP

BSP

PVCC

19

18

17

16

PBTL

14

PVCC

15

GND

29

PowerPAD

SD

1

PVCC

28

PVCC

100 μF 0.1 μF

1000 pF

100 μF

0.1 μF

1000 pF

Audio

Source

Control

System

100 kΩ

10 Ω

1 kΩ

FB

0.47 μF

1000 pF

0.47 μF

1000 pF

AVCC

1 Fm

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

www.ti.com

Figure 38. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input

Product Folder Link(s) :TPA3110D2

OUTP

OUTN

OUTP

Speaker

Current

OUTP

OUTN

OUTP-OUTN

Speaker

Current

OUTP

OUTN

OUTP-OUTN

Speaker

Current

0V

PVCC

NoOutput

PositiveOutput

NegativeOutput

0A

0V

-PVCC

OUTP-OUTN

TPA3110D2

www.ti.com

TPA3110D2 Modulation Scheme

The TPA3110D2 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

....................................................................................................................................................................................................... SLOS528 – JULY 2009

Figure 39. The TPA3110D2 Output Voltage and Current Waveforms Into an Inductive Load

Ferrite Bead Filter Considerations

Using the Advanced Emissions Suppression Technology in the TPA3110D2 amplifier it is possible to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter.

One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.

Product Folder Link(s) :TPA3110D2

FCCClassB

f-Frequency-Hz

830M

LimitLevel-dB V/mm

30M

20

230M 430M 630M

0

40

10

60

30

70

50

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at very low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3110D2 include 28L0138-80R-10 and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.

A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best.

Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPad™ beneath the chip.

www.ti.com

Figure 40. TPA3110D2 EMC spectrum with FCC Class B Limits

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × V the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3110D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is V

instead of 2 × V

CC

. As the output power increases, the pulses widen, making the

CC

ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

Product Folder Link(s) :TPA3110D2

, and the time at each voltage is half the period for

CC

1 mF

33 Hm

33 mH

OUTP

OUTN

L1

L2

C2

C3

2.2 mF

15 Hm

15 mH

OUTP

OUTN

L1

L2

C2

C3

2.2 mF

1nF

Ferrite

ChipBead

OUTP

OUTN

Ferrite

ChipBead

1nF

TPA3110D2

www.ti.com

When to Use an Output Filter for EMI Suppression

The TPA3110D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3110D2 EVM passes FCC Class B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.

There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are very sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used.

Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, it LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference.

....................................................................................................................................................................................................... SLOS528 – JULY 2009

Figure 41. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

Figure 42. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω

Figure 43. Typical Ferrite Chip Bead Filter (Chip Bead Example: )

Product Folder Link(s) :TPA3110D2

C

i

IN

Z

i

Z

f

Input

Signal

f=

1

2 Z Cp

i i

f =

c

1

2 Z Cp

i i

-3dB

f

c

C =

i

1

2 Z fp

i c

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

INPUT RESISTANCE

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 k Ω ± 20%, to the largest value, 60 k Ω ± 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps.

The -3-dB frequency can be calculated using Equation 2 . Use the ZIvalues given in Table 1 .

www.ti.com

(2)

INPUT CAPACITOR, C

In the typical application, an input capacitor (C proper dc level for optimum operation. In this case, C

I

) is required to allow the amplifier to bias the input signal to the

I

and the input impedance of the amplifier (Z

I

) form a

I

high-pass filter with the corner frequency determined in Equation 3 .

The value of CIis important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZIis 60 k Ω and the specification calls for a flat bass response down to 20 Hz. Equation 3 is reconfigured as Equation 4 .

In this example, CIis 0.13 µ F; so, one would likely choose a value of 0.15 µ F as this value is commonly used. If the gain is known and is constant, use ZIfrom Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network (C

) and the feedback network to the load. This

I

leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly.

(3)

(4)

Product Folder Link(s) :TPA3110D2

TPA3110D2

www.ti.com

....................................................................................................................................................................................................... SLOS528 – JULY 2009

POWER SUPPLY DECOUPLING, C

S

The TPA3110D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality capacitor typically 0.1 µ F to 1 µ F placed as close as possible to the device PVCC leads works best For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µ F or greater placed near the audio power amplifier is recommended. The 220 µ F capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 µ F or larger capacitor should be placed on each PVCC terminal. A 10 µ F capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency class D noise from entering the linear input amplifiers.

BSN and BSP CAPACITORS

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0.22 µ F ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 0.22 µ F capacitor must be connected from OUTPx to BSPx, and one 0.22 µ F capacitor must be connected from OUTNx to BSNx. (See the application circuit diagram in Figure 1 .)

The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

DIFFERENTIAL INPUTS

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3110D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3110D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same.

The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

Product Folder Link(s) :TPA3110D2

TPA3110D2

SLOS528 – JULY 2009 .......................................................................................................................................................................................................

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

The TPA3110D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements.

• Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (220 µ F or greater) bulk power supply decoupling capacitors should be placed near the TPA3110D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 µ F and 1 µ F also of good quality to the PVCC connections at each end of the chip.

• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.

• Grounding — The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3110D2.

• Output filter — The ferrite EMI filter (Figure 43 ) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 41 and Figure 42 ) should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground.

• Thermal Pad — The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB footprints, see figures at the end of this data sheet.

For an example layout, see the TPA3110D2 Evaluation Module (TPA3110D2EVM) User Manual. Both the EVM user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.

www.ti.com

Product Folder Link(s) :TPA3110D2

PACKAGE OPTION ADDENDUM

www.ti.com 4-Aug-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPA3110D2PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

no Sb/Br)

TPA3110D2PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TPA3110D2PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2009

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPA3110D2PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DLP® Products www.dlp.com Broadband www.ti.com/broadband DSP dsp.ti.com Digital Control www.ti.com/digitalcontrol Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Military www.ti.com/military Logic logic.ti.com Optical Networking www.ti.com/opticalnetwork Power Mgmt power.ti.com Security www.ti.com/security Microcontrollers microcontroller.ti.com Telephony www.ti.com/telephony RFID www.ti-rfid.com Video & Imaging www.ti.com/video RF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265