Datasheet TPA3004D2PHP Specification

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Page 1

10 nF

Cbs

10 nF

Cbs

PVCC PVCC

10 nF

Cbs

10 nF

Cbs

PVCC PVCC

220 pF

Cosc

Rosc

Ccpl

100 nF

Cvdd

Ccpr

Crinp

Crinn

Clinn

Clinp

LINP LINN

RINN RINP

SYSTEM CONTROL

VOL

VARDIFF VARMAX

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

PVCCL

BSLN

TPA3004D2

VCLAMPR

V2P5

RINP

LINN

LINP

AVDDREF VREF VARDIFF VARMAX VOLUME REFGND

MODE

MODE_OUT

VAROUTR VAROUTL

AVDD

AGND

COSC ROSC

AVCC

VCLAMPL

BSRP

PVCCR

ROUTP

PGNDR

ROUTN

PVCCR

BSRN

RINN

AVDD

AVCC

C2p5

FADE

10 µF10 µF

0.1 µF 0.1 µF

1 µF

0.1 µF

10 µF

1 µF

120 kΩ

1 µF

10 kΩ

0.1 µF

Cvcc 10 µF

MODE_OUT

RLINE_OUT LLINE_OUT

SYSTEM CONTROL

TPA3004D2

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12-W STEREO CLASS-D AUDIO POWER AMPLIFIER

WITH DC VOLUME CONTROL

Check for Samples: TPA3004D2

FEATURES

• 12-W/Ch Into an 8-Ω Load From 15-V Supply

• Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements

• 32-Step DC Volume Control From -40 dB to 36 dB

• Line Outputs For External Headphone Amplifier With Volume Control

• Regulated 5-V Supply Output for Powering TPA6110A2

• Space-Saving, Thermally-Enhanced PowerPAD™ Packaging

• Thermal and Short-Circuit Protection

APPLICATIONS

• LCD Monitors and TVs

• Powered Speakers

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

DESCRIPTION

The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3004D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the TPA3004D2 eliminates the need for external heatsinks when playing music.

Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from -40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range of gain from -56 dB to 20 dB.

An integrated 5-V regulated supply is provided for powering an external headphone amplifier.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Page 2

PHP PACKAGE

(TOP VIEW)

14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

1 2 3 4 5 6 7 8 9 10 11 12

BSRN

PVCCR

ROUTN

PGNDR

ROUTP

PVCCR

BSRP

VCLAMPR MODE_OUT MODE

VAROUTR VAROUTL FADE

COSC ROSC AGND VCLAMPL

SD RINN RINP V2P5

LINP LINN

VREF VARDIFF VARMAX VOLUME REFGND

BSLN

PVCCL

LOUTP

PVCCL

BSLP

TPA3004D2

AVDDREF

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

40°C to 85°C TPA3004D2PHP

(1) The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to

the part number (e.g., TPA3004D2PHPR).

AVAILABLE OPTIONS

PACKAGED DEVICE

48-PIN HTQFP (PHP)

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(1)

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Page 3

Biases

References

TTL Input

Buffer

Startup

Protection

Logic

Detect

Thermal

VDDok

RINP

RINN

VAROUTR

Ramp Generator

COSC

ROSC

VCCok

5V LDO

AVCC

AVDD

VDD

Deglitch &

Modulation

Logic

Gain

Adj.

Rfdbk2

Cint2

Gain

Control

Deglitch &

Modulation

Logic

Gain

Adj.

Rfdbk2

Cint2

LINP

LINN

VAROUTL

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSRP PVCCR(2)

ROUTP(2)

PGNDR

ROUTN(2)

PVCCR(2)

BSRN

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSLP

PVCCL(2)

LOUTP(2)

PGNDL

LOUTN(2)

PVCCL(2)

BSLN

VCLAMPL

VCLAMPR

VOLUME

VARDIFF VARMAX

To Gain Adj.

Blocks

VREF

REFGND

V2P5

Mode

Control

MODE

MODE_OUT

AVCC

AGND

AVDDREF

Gain

Adj.

Gain

Adj.

V2P5

FADE

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

FUNCTIONAL BLOCK DIAGRAM

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TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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Pin Functions

NO. NAME

AGND 26 - Analog ground for digital/analog cells in core AV

AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal. BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at

FADE 30 I Input for controlling volume ramp rate. A logic low on this pin places the amplifier in fade mode.

LINN 6 I Negative differential audio input for left channel LINP 5 I Positive differential audio input for left channel LOUTN 16, 17 O Class-D ½-H-bridge negative output for left channel LOUTP 20, 21 O Class-D ½-H-bridge positive output for left channel MODE 34 I Input for MODE control. A logic high on this pin places the amplifier in the variable output mode

MODE_OUT 35 O Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the

PGNDL 18, 19 - Power ground for left channel H-bridge PGNDR 42, 43 - Power ground for right channel H-bridge PVCCL 14, 15 Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to

PVCCL 22, 23 Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to

PVCCR 38,39 Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to

PVCCR 46, 47 Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to

REFGND 12 - Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume,

RINP 3 I Positive differential audio input for right channel RINN 2 I Negative differential audio input for right channel ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*V ROUTN 44, 45 O Class-D ½-H-bridge negative output for right channel ROUTP 40, 41 O Class-D ½-H-bridge positive output for right channel SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance

VARDIFF 9 I DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to

VARMAX 10 I DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF

VAROUTL 31 O Variable output for left channel audio. Line level output for driving external HP amplifier. VAROUTR 32 O Variable output for right channel audio. Line level output for driving external HP amplifier. VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors. VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors.

33 - High-voltage analog power supply (8.5 V to 18 V) 29 O 5-V Regulated output capable of 100-mA output

I/O DESCRIPTION

V2P5

A logic high on this pin allows a quick transition to the desired volume setting when cycling SD or during power-up.

and the Class-D outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as line-level outputs for external amplifiers.

MODE_OUT pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone amplifier control.

PVCCR or AVCC.

PVCCL or AVCC.

connect the DAC ground to this terminal.

to VCC.

GND or AVDDREF if VAROUT outputs are unconnected.

if VAROUT outputs are unconnected.

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TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Pin Functions (continued)

NO. NAME

VOLUME 11 I DC voltage that sets the gain of the Class-D and VAROUT outputs. VREF 8 I Analog reference for gain control section. V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using

— Thermal — Connect to AGND and PGND—should be center point for both grounds.

Pad

I/O DESCRIPTION

single-ended inputs.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range: AV Load impedance, R

Input voltage range, V

Supply current

Output current VAROUTL, VAROUTR 20 mA Continuous total power dissipation See the Thermal Information Table Operating free-air temperature range, T Operating junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The (TPA3004D2) incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to

a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.

CC,PVCC

MODE, VREF, VARDIFF, VARMAX, VOLUME, FADE 0 V to 5.5 V SD -0.3 V to VCC+ 0.3 V RINN, RINP, LINN, LINP -0.3 V to 7 V AV

AVDDREF 10 mA

(2)

stg

(1)

UNIT

-0.3 V to 20 V ≥ 3.6 Ω

120 mA

-40°C to 85°C

-40°C to 150°C

-65°C to 150°C

THERMAL INFORMATION

(1)(2)

JA JCtop JB

JT JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 26.6 Junction-to-case (top) thermal resistance 12.6 Junction-to-board thermal resistance 7.9 Junction-to-top characterization parameter 0.1 Junction-to-board characterization parameter 4.2 Junction-to-case (bottom) thermal resistance 0.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

Product Folder Link(s): TPA3004D2

TPS3004D2

PHP (48) PIN

UNITS

°C/W

Page 6

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Supply voltage, V

Volume reference voltage VREF 3.0 5.5 V Volume control pins, input voltage VARDIFF, VARMAX, VOLUME 5.5 V

High-level input voltage, V

Low-level input voltage, V

High-level output voltage, V Low-level output voltage, V

High-level input current, I

Low-level input current, I

Oscillator frequency, f

OSC

Operating free-air temperature, T Operating junction temperature, T

(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. The

junction temperature is controlled by the thermal design of the application and should be carefully considered in high power dissipation applications. See the thermal considerations section on pages 33-35 for recommendations on improving the thermal performance of your application.

PVCC, AV

≥ 3.6 Ω 8.5 18 V

CC;RL

SD 2 MODE 3.5 V FADE 4 SD 0.8 MODE, FADE 2 MODE_OUT, IOH= 1 mA AVDD–100mV V MODE_OUT, IOL= -1 mA AGND+100mV V MODE, VI= 5 V, VCC= 18 V 1 FADE, VI= 18 V, VCC= 18 V 150 µA SD, VI= 18 V, VCC= 18 V 50 MODE, FADE , VI= 0 V, VCC= 18 V 1 µA SD, VI= 0 V, VCC= 18 V 1 µA

225 275 kHz

(1)

–40 85 °C

125 °C

DC CHARACTERISTICS

TA= 25°C, VCC= 12 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

| VOS| INN and INP connected together, Gain = 36 dB 10 65 mV

V2P5 (terminal 4) 2.5-V Bias voltage No load V

PSRR VCC= 11.5 V to 12.5 V –80 dB I

CC(class-D)

CC(varout)

CC(class-D)

CC(SD)

DS(on)

max RL= 8 Ω, PO= 12 W, VCC= 15 V to 18 V 2 A

Class-D Output offset voltage (measured differentially)

0.45 x 0.5 x 0.55 x AV

5-V Regulated output 4.5 5 5.5 V

IO= 0 to 100 mA, SD = 2 V, VCC= 8.5 V to 18 V

Class-D power supply rejection ratio

Class-D mode quiescent current MODE = 2 V, SD = 2 V, VCC= 18 V 16 28.5 mA Variable output mode quiescent

current

MODE = 3.5 V, SD = 2 V, VCC= 18 V 7 9 mA

Class-D mode RMS current at max power

Supply current in shutdown mode

SD = 0.8 V, VCC= 12 V 1 10 SD = 0.8 V, VCC= 18 V 160

High side 300

Drain-source on-state resistance Low side 250 mΩ

VCC= 12 V, IO= 1 A, TJ= 25°C

Total 550 650

µA

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TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

AC CHARACTERISTICS FOR CLASS-D OUTPUTS

TA= 25°C, VCC= 12 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SVR

Supply ripple rejection ratio –67 dB

Maximum continuous output

O(max)

power(thermally limited)

Output integrated noise floor –82 dBV

Crosstalk, Class-D-Left → Class-D-Right

Crosstalk, Class-D → VAROUT

SNR Signal-to-noise ratio 102 dB

Thermal trip point 150 °C Thermal hysteresis 20 °C

VCC= 11.5 V to 12.5 V from 10 Hz to 1 kHz, Gain = 36 dB

RL= 4 Ω 7.5 W RL= 8 Ω, VCC= 15 V 12 W 20 Hz to 22 kHz, No weighting filter,

Gain = 0.5 dB Gain = 13.2 dB, PO= 1 W, RL= 8 Ω –77 dB

Maximum output at THD < 0.5%, Gain = 36 dB –63 dB Maximum output at THD+N < 0.5%, f = 1 kHz,

Gain = 0.5 dB

CHARACTERISTICS FOR VAROUT OUTPUTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

|VOS| Output offset voltage 10 65 mV

THD+N Total harmonic distortion + noise

PSRR DC power supply rejection ratio Gain = 20 dB –74 dB k

SVR

Supply ripple rejection ratio Gain = 20 dB, f = 1 kHz –95 dB Crosstalk, VAROUTL → VAROUTR Maximum output at THD < 0.5%, Gain = 20 dB –60 dB Crosstalk, VAROUT → Class-D Maximum output at THD < 0.5%, Gain = 20 dB –74 dB

Output integrated noise floor µV

Measured between V2P5 and VAROUT, Gain = 20 dB, RL= 10 kΩ

AV= 7.3 dB, f = 1 kHz, PO= 6 mW, RL= 32 Ω

AV= 7.3 dB, f = 1 kHz, RL= 2 kΩ, VO= 1 V

rms

0.025%

0.002%

20 Hz to 22 kHz, Gain = 20 dB 75 20 Hz to 22 kHz, Gain = –0.3 dB 15

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TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Table 1. DC Volume Control for Class-D Outputs

VOLTAGE ON THE VOLUME PIN AS A

PERCENTAGE OF VREF

(INCREASING VOLUME

OR FIXED GAIN)

% % dB

0 – 4.5 0 – 2.9 –75

4.5 – 6.7 2.9 – 5.1 –40.0

6.7– 8.91 5.1 – 7.2 –37.5

8.9 – 11.1 7.2 – 9.4 –35.0

11.1 – 13.3 9.4 – 11.6 –32.4

13.3 – 15.5 11.6 – 13.8 –29.9

15.5 – 17.7 13.8 – 16.0 –27.4

17.7 – 19.9 16.0 – 18.2 –24.8

19.9 – 22.1 18.2 – 20.4 –22.3

22.1 – 24.3 20.4 – 22.6 –19.8

24.3 – 26.5 22.6 – 24.8 –17.2

26.5 – 28.7 24.8 – 27.0 –14.7

28.7– 30.9 27.0 – 29.1 –12.2

30.9 – 33.1 29.1 – 31.3 –9.6

33.1 – 35.3 31.3 – 33.5 –7.1

35.3 – 37.5 33.5 – 35.7 –4.6

37.5 – 39.7 35.7 – 37.9 –2.0

39.7 – 41.9 37.9 – 40.1 0.5

41.9 – 44.1 40.1 – 42.3 3.1

44.1 – 46.4 42.3 – 44.5 5.6

46.4 – 48.6 44.5 – 46.7 8.1

48.6 – 50.8 46.7 – 48.9 10.7

50.8 – 53.0 48.9 – 51.0 13.2

53.0 – 55.2 51.0 – 53.2 15.7

55.2 – 57.4 53.2 – 55.4 18.3

57.4 – 59.6 55.4 – 57.6 20.8

59.6 – 61.8 57.6 – 59.8 23.3

61.8 – 64.0 59.8 – 62.0 25.9

64.0 – 66.2 62.0 – 64.2 28.4

66.2 – 68.4 64.2 – 66.4 30.9

68.4 – 70.6 66.4 – 68.6 33.5 >70.6 >68.6 36.0

(1) Tested in production. Remaining steps are specified by design.

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VOLTAGE ON THE VOLUME PIN AS A GAIN OF CLASS-D

PERCENTAGE OF VREF AMPLIFIER

(DECREASING VOLUME)

(1)

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TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Table 2. DC Volume Control for VAROUT Outputs

VAROUT_VOLUME (V)

FROM FIGURE 24 – AS A

PERCENTAGE OF VREF

(INCREASING VOLUME

OR FIXED GAIN)

% % dB

0 – 4.5 0 – 2.9 –66

4.5 – 6.7 2.9 – 5.1 –56.0

6.7– 8.91 5.1 – 7.2 –53.5

8.9 – 11.1 7.2 – 9.4 –50.9

11.1 – 13.3 9.4 – 11.6 –48.4

13.3 – 15.5 11.6 – 13.8 –45.9

15.5 – 17.7 13.8 – 16.0 –43.3

17.7 – 19.9 16.0 – 18.2 –40.8

19.9 – 22.1 18.2 – 20.4 –38.3

22.1 – 24.3 20.4 – 22.6 –35.7

24.3 – 26.5 22.6 – 24.8 –33.2

26.5 – 28.7 24.8 – 27.0 –30.7

28.7– 30.9 27.0 – 29.1 –28.1

30.9 – 33.1 29.1 – 31.3 –25.6

33.1 – 35.3 31.3 – 33.5 –23.1

35.3 – 37.5 33.5 – 35.7 –20.5

37.5 – 39.7 35.7 – 37.9 –18.0

39.7 – 41.9 37.9 – 40.1 –15.5

41.9 – 44.1 40.1 – 42.3 –13.0

44.1 – 46.4 42.3 – 44.5 –10.4

46.4 – 48.6 44.5 – 46.7 –7.9

48.6 – 50.8 46.7 – 48.9 –5.3

50.8 – 53.0 48.9 – 51.0 –2.8

53.0 – 55.2 51.0 – 53.2 –0.3

55.2 – 57.4 53.2 – 55.4 2.3

57.4 – 59.6 55.4 – 57.6 4.8

59.6 – 61.8 57.6 – 59.8 7.3

61.8 – 64.0 59.8 – 62.0 9.9

64.0 – 66.2 62.0 – 64.2 12.4

66.2 – 68.4 64.2 – 66.4 14.9

68.4 – 70.6 66.4 – 68.6 17.5 >70.6 >68.6 20.0

(1) VAROUT_VOLUME (V) = VOLUME (V) - VARDIFF (V), see section VOLUME CONTROL

OPERATION through MODE_OUT OPERATION section.

(2) Tested in production. Remaining steps are specified by design.

(1)

–

VAROUT_VOLUME (V) –

FROM FIGURE 24 – AS A GAIN OF VAROUT

PERCENTAGE OF VREF AMPLIFIER

(DECREASING VOLUME)

(1)

(2)

(1)

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TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

TYPICAL CHARACTERISTICS

Table 3. Table of Graphs

FIGURE

Class-D Efficiency vs Output power Figure 1

O(sd)

THD+N Class-D Total harmonic distortion + noise

SVR

THD+N VAROUT Total harmonic distortion + noise vs Output voltage Figure 32

SVR

Class-D Output power vs Load resistance Figure 2

vs Supply voltage Figure 3

Class-D Supply current vs Supply voltage Figure 4

vs Output Power Figure 5 Shutdown supply current vs Supply voltage Figure 6 Class-D Input impedance vs Gain Figure 7

vs Frequency Figure 8 – Figure 12

vs Output power Figure 13 – Figure 17 Class-D Supply ripple rejection ratio vs Frequency Figure 18 Class-D Closed loop response Figure 19 Class-D Intermodulation performance Figure 20 Class-D Input offset voltage vs Common-mode input voltage Figure 21 Class-D Crosstalk vs Frequency Figure 22 Class-D Mute attenuation Figure 23 Class-D Shutdown attenuation Figure 24

vs Frequency

Class-D Common-mode rejection ratio vs Frequency Figure 25 VAROUT Input resistance vs Gain Figure 26 VAROUT Noise vs Frequency Figure 27 VAROUT Closed Loop Response Figure 28 VAROUT Common-mode rejection ratio vs Frequency Figure 29 VAROUT Crosstalk vs Frequency Figure 30

vs Output power Figure 31

vs Frequency Figure 33 VAROUT Supply ripple rejection ratio vs Frequency Figure 34

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– Output Power – W

4 6 8 10

OUTPUT POWER

LOAD RESISTANCE

12 14 16

RL – Load Resistance – Ω

VCC = 8 V , THD = 1%

VCC = 12 V , THD = 10%

f = 1 kHz, LC Filter, Class-D, Resistive Load, TA = 25°C

VCC = 8 V , THD = 10%

VCC = 12 V , THD = 1%

Dashed line may require external heat sinking

PO – Output Power – W

Class-D, LC Filter, Resistive Load

EFFICIENCY

OUTPUT POWER

RL = 8 Ω, VCC = 18 V

0 2 4 6

Efficiency – %

100

8 10 12

RL = 4 Ω, VCC = 12 V

8 Ω Speaker

10% THD+N

10 11

OUTPUT POWER

SUPPLY VOLTAGE

12 13

– Output Power – W

VCC – Supply Voltage – V

8.5 15 16 17 18

TA = 25°C

8 Ω Speaker

1% THD+N

13 12

11 10

8.5

10 11

– Supply Current – mA

SUPPLY CURRENT

SUPPLY VOLTAGE

12 13 14

VCC – Supply Voltage – V

16 17 18

SD = 2 V, MODE = 2 V , Class-D, No Load

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 1. Figure 2.

Figure 3. Figure 4.

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Page 12

1500

1000

500

0 5 10 15

2000

SUPPLY CURRENT

OUTPUT POWER

2500

20 25

PO – Output Power – W

– Supply Current – mAI

VCC = 12 V , MODE = 2 V , Class-D, Left/Right Channel Total Output Power

4 Ω

8 Ω

16 Ω

0.5

1.5

2.5

3.5

4.5

8 10 12 14

16 18

– Shutdown Supply Current –

SHUTDOWN SUPPLY CURRENT

SUPPLY VOLTAGE

CC(sd)

Aµ

VCC – Supply Voltage – V

SD = 0 V, No Load

–50 –30 –10 10

100

120

30 50

– Input Impedance – k

Gain – dB

INPUT IMPEDANCE

GAIN

Ω

Class-D

f – Frequency – Hz

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

20 100 1k 10k

0.01

0.1

VCC = 8 V RL = 8 Ω Gain = +36 dB Class-D

PO = 0.25 W

PO = 1.5 W

PO = 3 W

THD+N – Total Harmonic Distortion + Noise – %

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 5. Figure 6.

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Figure 7. Figure 8.

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THD+N – Total Harmonic Distortion + Noise – %

f – Frequency – Hz

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

10 100 1k 10k

0.01

0.1

VCC = 12 V RL = 8 Ω Gain = +36 dB Class-D

PO = 0.5 W

PO = 2.5 W

PO = 5 W

PO = 12 W

PO = 1 W

PO = 4 W

THD+N –Total Harmonic Distortion + Noise – dB

VCC = 18 V , Gain = 36 dB, RL = 8 Ω

0.5

20 50 100 200 500 1 k

f – Frequency – Hz

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

2 k 5 k 10 k 20 k

0.2

0.05

0.1

0.02

0.01

f – Frequency – Hz

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

20 100 1k 10k

0.01

0.1

VCC = 8 V RL = 4 Ω Gain = +36 dB

PO = 2 W

PO = 0.5 W

PO = 4 W

THD+N – Total Harmonic Distortion + Noise – %

f – Frequency – Hz

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

20 100 1k 10k

0.01

0.1

VCC = 12 V RL = 4 Ω Gain = +36 dB

PO = 0.5 W

PO = 7 W

PO = 3.5 W

THD+N – Total Harmonic Distortion + Noise – %

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 9. Figure 10.

Figure 11. Figure 12.

Product Folder Link(s): TPA3004D2

Page 14

THD+N – Total Harmonic Distortion + Noise – %

PO – Output Power – W

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

10 m 100 m 1 10

0.01

0.1

VCC = 8 V RL = 8 Ω Gain = +13.2 dB Class-D

f = 1 kHz

f = 20 Hz

THD+N – Total Harmonic Distortion + Noise – %

PO – Output Power – W

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

10 m 100 m 1 10

0.01

0.1

VCC = 12 V RL = 8 Ω Gain = +13.2 dB Class-D

f = 1 kHz

f = 20 Hz

f = 20 kHz

f = 1 kHz

f = 20 Hz

THD+N –Total Harmonic Distortion + Noise – dB

VCC = 18 V , RL = 8 Ω

0.5

100 m 200 m 500 m 1 2

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

5 10 20

0.2

0.05

0.1

0.02

0.01

PO– Output Power – W

THD+N – Total Harmonic Distortion + Noise – %

PO – Output Power – W

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

20 m 100 m 1 10

0.01

0.1

VCC = 8 V RL = 4 Ω Gain = 13.2 dB

f = 1 kHz

f = 20 Hz

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 13. Figure 14.

www.ti.com

Figure 15. Figure 16.

Product Folder Link(s): TPA3004D2

Page 15

THD+N – Total Harmonic Distortion + Noise – %

PO – Output Power – W

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

20 m 100 m 1 10

0.01

0.1

VCC = 12 V RL = 4 Ω Gain = 13.2 dB

f = 1 kHz

f = 20 Hz

100 1 k 10 k

–80

–75

–70

–65

–60

–55

–50

–45

–40

RL = 8 Ω, C

2p5

= 1 µF,

Class-D

f – Frequency – Hz

SUPPLY RIPPLE REJECTION RATIO

FREQUENCY

SVR

– Supply Ripple Rejection Ratio – dB

VCC = 12 V

VCC = 8 V

20 20 k

–250

–200

–150

–100

–50

100

10 100 1 k 10 k 100 k 1 M

Gain

Phase

–250

–200

–150

–100

–50

100

Gain – dB

f – Frequency – Hz

CLOSED LOOP RESPONSE

Phase – Deg

VCC = 12 V , Gain= +36 dB, RL = 8 Ω Class-D

–140

–120

–100

–80

–60

–40

–20

50 100 1 k 10 k

FFT – dBr

INTERMODULATION PERFORMANCE

f – Frequency – Hz

VCC = 12 V , 19 kHz, 20 kHz, 1:1, PO = 1 W, RL = 8 Ω Gain= +13.2 dB, BW =20 Hz to 22 kHz, Class-D No Filter

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 17. Figure 18.

Figure 19. Figure 20.

Product Folder Link(s): TPA3004D2

Page 16

–1

0 1 2 3

– Input Offset Voltage – mV

4 5

INPUT OFFSET VOLTAGE

COMMON-MODE INPUT VOLTAGE

ICM

– Common-Mode Input Voltage – V

VCC = 12 V Class-D

VCC = 12 V , C

2p5

= 1 µF,

PO = 1 W, Gain = +13.2 dB, Class-D, RL = 8 Ω

–40

–70

–80 –90

Crosstalk – dB

–30

–10

f – Frequency – Hz

CROSSTALK

FREQUENCY

–60

–50

–20

100 1 k 10 k20

20 k

–80

–100

–110

–130

10 100 1 k

Mute Attenuation – dB

–60

–50

f – Frequency – Hz

MUTE ATTENUATION

FREQUENCY

–30

10 k

–120

–90

–70

–40

VCC = 12 V , RL = 8 Ω, VI = 1 V

rms

Class-D,

VOLUME = 0 V

–105

–115

–120

–130

10 100 1 k

Shutdown Attenuation – dB

–95

–90

f – Frequency – Hz

SHUTDOWN ATTENUATION

FREQUENCY

–80

10 k

–125

–110

–100

–85

VCC = 12 V , RL = 8 Ω, VI = 1 V

rms

Gain = +13.2 dB, Class-D

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 21. Figure 22.

www.ti.com

Figure 23. Figure 24.

Product Folder Link(s): TPA3004D2

Page 17

CMRR – Common-Mode Rejection Ratio – dB

–70

–80

–90

–100

10 100 1 k

–60

–50

f – Frequency – Hz

COMMON-MODE REJECTION RATIO

FREQUENCY

–40

10 k 100 k

VCC = 12 V , RL = 8 Ω, C

2p5

= 1 µF,

Class-D

–50 –30 –10

– Input Resistance – k

100

140

Gain – dB

INPUT RESISTANCE

GAIN

160

10 30

120

Ω

VAROUT

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

20 100 1 k 10 k

Noise FFT − dBV

f − Frequency − Hz

NOISE

FREQUENCY

VCC = 12 V , Gain = +20 dB, RL = 8 Ω, Inputs AC Coupled to GND, VAROUT, No Filter

−175

175

−150

−125

−100

−75

−50

−25

100

125

150

−22.493

9.318

−18.958

−15.424

−11.889

−8.354

−4.82

−1.285

2.249

5.784

10 100 1 k 10 k

12.853 Gain

Phase

Gain − dB

f − Frequency − Hz

BCLOSED LOOP RESPONSE

Phase − Deg

VCC = 12 V , Gain = +7.9 dB, RL = 8 Ω, VAROUT

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 25. Figure 26.

Figure 27. Figure 28.

Product Folder Link(s): TPA3004D2

Page 18

–60

–40

–58

–56

–54

–52

–50

–48

–46

–44

–42

20 100 1 k 10 k

CMRR – Common-Mode Rejection Ratio – dBv

f– Frequency – Hz

COMMON-MODE REJECTION RATIO

FREQUENCY

VCC = 12 V , RL = 8 Ω , C2P5 = 1 µF, VAROUT

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

20 100 1 k 10 k

G = 20 dB

G = 10 dB

G = 0 dB

G = –10 dB

VO = 1 V

rms,

RL = 10 kΩ, VAROUT

Crosstalk – dB

f – Frequency – Hz

CROSSTALK (VAROUTL-TO-VAROUTR)

FREQUENCY

0.001

0.01

0.02

0.1

0.2

20 m 100 m

200 m

1 2

THD+N –Total Harmonic Distortion + Noise – %

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT VOLTAGE

VCC = 12 V RL = 10 kΩ, Gain = +6 dB VAROUT

VO – Output Voltage – V

RMS

f = 1 kHz

0.001

0.01

0.02

0.1

0.2

20 µ 100 µ 200 µ 1 m 2 m 10 m 20 m

THD+N –Total Harmonic Distortion + Noise – %

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

VCC = 12 V RL = 32 Ω, Gain = +6 dB, VAROUT

PO – Output Power – W

f = 1 kHz

f = 20 kHz

f = 20 Hz

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 29. Figure 30.

www.ti.com

Figure 31. Figure 32.

Product Folder Link(s): TPA3004D2

Page 19

0.005

0.01

0.02

0.1

0.2

20 100 1 k 10 k

THD+N –Total Harmonic Distortion + Noise – %

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

f – Frequency – Hz

VCC = 12 V R

= 32 Ω,

PO = 5 mW, Gain = +7.9 dB, VAROUT

–110

–100

–90

–80

–70

–60

–50

–40

20 100 1 k 10 k

f – frequency – Hz

SUPPLY RIPPLE REJECTION RATIO

FREQUENCY

SVR

– Supply Ripple Rejection Ratio – dB

VCC = 12 V VAROUT

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 33. Figure 34.

Product Folder Link(s): TPA3004D2

Page 20

C11

C17

10 nF

C20

C12

10 nF

C21

220pF

100 nF

C14

LIN–

RIN–

SHUTDOWN

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

PVCCL

BSLN

TPA3004D2

VCLAMPR

V2P5

RINP

LINN

LINP

AVDDREF VREF VARDIFF VARMAX VOLUME REFGND

MODE

MODE_OUT

VAROUTR

VAROUTL

FADE

AVDD

AGND

COSC ROSC

AVCC

VCLAMPL

BSRP

PVCCR

ROUTP

PGNDR

ROUTN

PVCCR

BSRN

RINN

C16

50k

LOUT–

VCC

C15

10 nF

C18

C10

10 nF

C19

ROUT–

VCC

(Bead)

C24

1nF

(Bead)

C25 1nF

GND

GND GND

VAROUTR

VAROUTL AVDD

C13

GND

MODEB

MODE

AGND

PGND

GND

ROUT+

(Bead)

C22

1 nF

(Bead)

C23 1 nF

VCC

10 µF

0.1uF 0.1uF

1 µF

0.1 µF 10 µF

120 kΩ

1 µF

0.1 µF0.1 µF

10 µF

50 kΩ

1 µF

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

APPLICATION INFORMATION

www.ti.com

†

Schottky diodes only needed for short circuit protection when VCC > 15 V. See SHORT CIRCUIT PROTECTION

section in Application Information.

Figure 35. Stereo Class-D With Single-Ended Inputs

Product Folder Link(s): TPA3004D2

Page 21

C11

C17

10 nF

C20

C12

10 nF

C21

LIN–

RIN–

SHUTDOWN

BSLP

PVCCL PVCCL

LOUTP

PGNDL

PGNDL LOUTN LOUTN

PVCCL

BSLN

V2P5

RINP

LINN

LINP

AVDDREF

VREF

VARDIFF

VARMAX

VOLUME

REFGND

VCLAMPL

BSRP PVCCR PVCCR ROUTP ROUTP PGNDR PGNDR ROUTN ROUTN PVCCR PVCCR BSRN

RINN

LOUT– VCC

VCC LOUT+

C15

10 nF

C18

C10

10 nF

C19

ROUT–

VCC

(Bead)

C24

1 nF

(Bead)

C25

1 nF

GND

AGND

PGND

(Bead)

C22

1 nF

(Bead)

C23

1 nF

VCC

220 pF

100 nF

C14

Cvcc

VCLAMPR

MODE

MODE_OUT

VAROUTR

VAROUTL

FADE

AVDD

AGND

COSC

ROSC

AVCC

AVDD

AVCC

Cin1

Cin2

C16

Cout1

Cout2

Rout2

Rout1

AVDD

IN1

Vo1

VDD

Vo2 IN2

GND

BYP

TPA6110A2

Rhps2

Rhpf2

Rhps1

Rhpf1

Rin1

Rin2

ROUT+

0.1µF

0.1µ F

10 µF

µF

120k Ω

10kΩ

1 µF

10 µF

1 µF

10kΩ

0.47µF

1kΩ

220µF

10kΩ

220µF

10kΩ

µF

120 k Ω

0.1µ F0.1µF

10 µF

1 µF

1µF

1 µF

1µF

50 kΩ

LOUTP

TPA3004D2

(T1)

(T2)

(T3)

(T4)

C13

0.1

µF

PGND

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

†

Schottky diodes only needed for short circuit protection when VCC > 15 V. See SHORT CIRCUIT PROTECTION

section in Application Information.

Figure 36. Stereo Class-D With Single-Ended Inputs and Stereo Headphone Amplifier Interface

Product Folder Link(s): TPA3004D2

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0 V

–12 V

+12 V

Current

OUTP

Differential Voltage

Across Load

OUTN

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

www.ti.com

Class-D Operation

This section focuses on the class-D operation of the TPA3004D2.

Traditional Class-D Modulation Scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in

Figure 37. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,

causing high loss, thus causing a high supply current.

TPA3004D2 Modulation Scheme

The TPA3004D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

Figure 37. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an

Inductive Load With No Input

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0 V

–12 V

+12 V

Current

OUTP

OUTN

Differential

Voltage

Across

Load

0 V

–12 V

+12 V

Current

OUTP

OUTN

Differential

Voltage

Across

Load

Output = 0 V

Output > 0 V

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 38. The TPA3004D2 Output Voltage and Current Waveforms Into an Inductive Load

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3004D2 modulation scheme has very little loss in the load without a filter because the pulses are very short and the change in voltage is VCCinstead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker, which results in less power dissipation, therefore increasing efficiency.

Effects of Applying a Square Wave into a Speaker

Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2for frequencies beyond the audio band.

Product Folder Link(s): TPA3004D2

Page 24

RL) r

ds(on)

100% + 8ń(8 ) 0.58) 100% + 93.24%

(total)

+ POńEfficiency + 7.5 W ń 0.9324 + 8.04 W

(total)

(measured) * P

(total)

(theoretical) + 8.43* 8.04 + 0.387 W

(dis)

+ 0.387 W * (14 V 14.3 mA) + 0.19 W

0.22 µF

1 µF

15 µH

OUTP

OUTN

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

www.ti.com

Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency switching current. The amount of power dissipated in the speaker may be estimated by first considering the overall efficiency of the system. If the on-resistance (r

) of the output transistors is considered to cause the

ds(on)

dominant loss in the system, then the maximum theoretical efficiency for the TPA3004D2 with an 8-Ω load is as follows:

(1)

The maximum measured output power is approximately 7.5 W with an 12-V power supply. The total theoretical power supplied (P

) for this worst-case condition would therefore be as follows:

(total)

(2)

The efficiency measured in the lab using an 8-Ω speaker was 89%. The power not accounted for as dissipated across the r

may be calculated by simply subtracting the theoretical power from the measured power:

ds(on)

(3)

The quiescent supply current at 14 V is measured to be 14.3 mA. It can be assumed that the quiescent current encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any remaining power is dissipated in the speaker and is calculated as follows:

(4)

Note that these calculations are for the worst-case condition of 7.5 W delivered to the speaker. Since the 0.19 W is only 2.5% of the power delivered to the speaker, it may be concluded that the amount of power actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the power generated from a clipping waveform.

When to Use an Output Filter

Design the TPA3004D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter.

Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.

Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from the amplifier to the speaker.

Figure 39. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω

Product Folder Link(s): TPA3004D2

Page 25

0.1 µF

0.47 µF

33 µH

OUTP

OUTN

1 nF

Ferrite

Chip Bead

OUTP

OUTN

Ferrite

Chip Bead

1 nF

TPA3004D2

www.ti.com

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 40. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

Figure 41. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)

Volume Control Operation

Three pins labeled VOLUME, VARDIFF, and VARMAX control the class-D volume when driving speakers and the VAROUT volume. All of these pins are controlled with a dc voltage, which should not exceed VREF.

When driving speakers in class-D mode, the VOLUME pin is the only pin that controls the gain. Table 1 lists the gain in class-D mode as determined by the voltage on the VOLUME pin in reference to the voltage on VREF.

If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 35 in the Application Information section). For fixed gain, calculate the resistor divider values necessary to center the voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7 dB is desired, the resistors in the divider network can both be 10 kΩ. With these resistor values, a voltage of 50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB.

If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the VREF input and any fluctuations in the DAC output voltage will not affect the TPA3004D2 gain. The percentages in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME terminal is increased. The percentages in the second column should be used for the DAC voltages when decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the gain based on an increase or decrease in the desired system volume. This is explained further in a section below.

If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND. VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column in Table 1 should be used to determine the point at which the gain changes depending on the direction that the potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in

Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the

second column should be referenced.

Product Folder Link(s): TPA3004D2

Page 26

VARMAX (V)

VOLUME–VARDIFF

VARDIFF (V)

–

YES

VAROUT_VOLUME (V) = VOLUME (V) – VARDIFF (V)

VAROUT_VOLUME (V) = VARMAX (V)

Is VARMAX>

(VOLUME–VARDIFF)

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

www.ti.com

The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of the volume control can be found in Figure 43. The graph focuses on three gain steps with the trip points defined in the first and second columns of Table 1 for class-D gain. The dotted lines represent the hysteresis about each gain step.

The timing of the volume control circuitry is controlled by an internal 60 Hz clock. This clock determines the rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is reached. For example, if the TPA3004D2 is currently in the +0.53 db class-D gain step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36dB is 14 steps x 67ms/step =

0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step of +36 dB.

VARDIFF and VARMAX Operation

The TPA3004D2 allows the user to specify a difference between the class-D gain and VAROUT gain. This is desirable to avoid any listening discomfort when plugging in headphones. When interfacing with the variable outputs, the VARDIFF and VARMAX pins control the VAROUT channel gain proportional to the gain set by the voltage on the VOLUME pin. When VARDIFF=0 V, the difference between the class-D gain and the VAROUT gain is 16 dB. As the voltage on the VARDIFF terminal is increased, the VAROUT channel gain decreases. Internal to the TPA3004D2 device, the voltage on the VARDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to determine the VAROUT gain.

Some audio systems require that the gain be limited in the VAROUT mode to a level that is comfortable for headphone listening. The VARMAX terminal controls the maximum gain for the VAROUT channels.

The functionality of the VARDIFF and VARMAX pin are combined to fix the VAROUT channel gain. A block diagram of the combined functionality is shown in Figure 42. The value obtained from the block diagram for VAROUT_VOLUME is a DC voltage that can be used in conjunction with Table 2 to determine the VAROUT channel gain. Table 2 lists the gain in VAROUT mode as determined by the VAROUT_VOLUME voltage in reference to the voltage on VREF.

Figure 42. Block Diagram of VAROUT Volume Control

Product Folder Link(s): TPA3004D2

Page 27

0.5

3.1

5.6

2.10

2.00

2.11

2.21

Class-D Gain – dB

Voltage on VOLUME Pin – V

Decreasing Voltage on

VOLUME Terminal

Increasing Voltage on

VOLUME Terminal

(40.1%*VREF)

(44.1%*VREF)

(42.3%*VREF)

(41.9%*VREF)

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 43. DC Volume Control Operation, VREF = 5 V

MODE OPERATION

The MODE pin is an input for controlling the output mode of the TPA3004D2. A logic HIGH on this pin disables the Class-D outputs. A logic LOW on this pin enables the class-D outputs. The VAROUT outputs are active in both modes and can be used as line level inputs to an external powered subwoofer while driving internal stereo speakers with the class-D outputs. The trip levels are defined in the specifications table.

For interfacing with an external headphone amplifier like the TPA6110A2, the MODE pin can be connected to the switch on a headphone jack. When configured like Figure 36, the class-D outputs will be disabled when a headphone plug is inserted into the headphone jack.

MODE_OUT OPERATION

The MODE_OUT pin is an output for controlling the SHUTDOWN pin on an external headphone amplifier like the TPA6110A2 or for interfacing with other logic. The output voltages for a given load condition are given in the specifications table.

This output is controlled by the MODE pin logic. When the MODE input is driven to a logic low, the MODE_OUT output drives to a logic high. Conversely, when the MODE pin is driven to a logic high, the MODE_OUT output drives LOW. The MODE_OUT output is simply the inverted state of the MODE input.

It is designed in this manner because the TPA6110A2 SHUTDOWN input is active high. This allows the TPA3004D2 to place the TPA6110A2 into the shutdown state when driving internal speakers in the Class-D mode. Conversely, the MODE_OUT pin drives low to enable the TPA6110A2 headphone amplifier when headphones are plugged into the headphone jack and the MODE input is driven high.

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SD = 0V

TPA3004D2

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FADE OPERATION

The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions to and from the shutdown state and during power-up.

A logic low on this terminal, places the amplifier in the fade mode. During power-up or recovering from the shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute state, –75 dB, to the desired volume setting determined by the voltage on the volume control terminals. Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is reached. For example, if the TPA3004D2 is currently in the +0.53 db class-D gain step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36dB is 14 steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step of +36 dB.

Figure 44 shows a scope capture of the differential output (measured across OUT+ and OUT–) with the amplifier

in the fade mode. A 1 Vppdc voltage was applied across the differential inputs and a logic low was applied to the SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step to the next lower step at approximately 67 ms/step.

A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and during power-up. During power-up or recovering from the shutdown state (a logic high is applied to the SD terminal), the transition from the mute state, –75 dB, to the desired volume setting is less than 1 ms. Conversely, the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD terminal. For the best pop performance, the fade mode should be enabled (a logic low is applied to the FADE terminal).

Figure 44. Differential Output With FADE (Terminal 30) Held Low

Figure 45 shows a scope capture of the differential output with the fade effect disabled. The outputs transition to

the lowest gain state within 1ms of applying a logic low to the SD terminal.

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= 0 V

Input

Signal

*3dB

2p ZiC

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 45. Differential Output With FADE Terminal Held High

The switching frequency is determined using the values of the components connected to ROSC (pin 27) and COSC (pin 28) and may be calculated with the following equation:

OSC

= 6.6 / (R

OSC

× C

OSC

) .

INTERNAL 2.5-V BIAS GENERATOR CAPACITOR SELECTION

The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stages on both the class-D amplifiers and the variable amplifiers. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers.

The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance. During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75xV2P5, or 75% of its final value, the device turns on and the class-D outputs start switching. The startup time is not critical for the best depop performance since any pop sound that is heard is the result of the class-D outputs switching on and not the startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor.

A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.

INPUT RESISTANCE

Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or cutoff frequency also changes by over six times.

The –3-dB frequency can be calculated using Equation 5. Input impedance (ZI) vs Gain can be found in Figure 7.

Product Folder Link(s): TPA3004D2

(5)

Page 30

f =

2pZ C

i i

–3dB

2pZ

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

INPUT CAPACITOR, C

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In the typical application an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level (V2P5) for optimum operation. In this case, CIand the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in equation 6.

(6)

The value of CIis important, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where ZIis 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is reconfigured as Equation 7.

(7)

In this example, CIis 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is known and will be constant, use ZIfrom Figure 7 (Input Impedance vs Gain) to calculate CI. Calculations for C should be based off the impedance at the lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path from the input source through the input network (CI) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

Power Supply Decoupling, C

The TPA3004D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VCClead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.

BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit diagram in Figure 35.)

The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors attempt to hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. However, there is a leakage path and the voltage on the bootstrap capacitors slowly decrease while the high-side is conducting.

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AVDD – POWER-UP RESPONSE

(pin 33)

)

(pin 29)

Power–Up

Ch1 5.00 V/div Ch2 2.00 V/div M 10.0 µs

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

By driving the outputs into heavy clipping with a sine wave of less than 50 Hz, the bootstrap voltage can decrease below the minimum Vgsrequired to keep the high-side output MOSFET turned on. When this occurs, the output transistor becomes a source-follower and the output drops from VCCto approximately V

clamp

(voltage

on pins 25 and 36). For the majority of applications, driving a square wave at low frequencies is not a design consideration and the

recommended bootstrap capacitor value of 10-nF is acceptable. However, if this is a concern, increasing the bootstrap capacitors holds the gate voltage for a longer period of time and the drop in the output voltage does not occur. A value of 220-nF is recommended with a 51 Ω resistor placed in series between the outputs and bootstrap pins. The 51 Ω series resistor is necessary to limit the current charging and discharging the bootstrap capacitors.

VCLAMP Capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25) and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary with VCCand may not be used for powering any other circuitry.

Internal Regulated 5-V Supply (AVDD)

The AVDDterminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator, preamplifier, and volume control circuitry. It requires a 0.1-µF to 1-µF capacitor, placed very close to the pin, to ground to keep the regulator stable. The regulator may be used to power an external headphone amplifier or other circuitry, up to a current limit specified in the specification table. When powering external circuitry, like the TPA6110A2 headphone amplifier, an additional 10 µF or larger capacitor should be added to the AVDDterminal.

Differential Input

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3004D2 EVM with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3004D2 with a single-ended source, ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the audio source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the audio source instead of at the device input for best noise performance.

Figure 46. Power-Up Response

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T = T - P

Amax J JA Dissipated

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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SD OPERATION

The TPA3004D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state, I

CC(SD)

= 10 µA. SD should never be left

unconnected, because amplifier operation would be unpredictable.

POWER-OFF POP REDUCTION

For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing the power supply voltage.

Another method to reduce power-off pop is implemented in the hardware. A 100 µF – 150 µF capacitor can be added to the AVDDterminal in parallel with the 100-nF capacitor shown in Figure 35. The additional capacitance holds up the regulator voltage for a longer period of time and results in smaller power-off pop.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor.

SHORT-CIRCUIT PROTECTION

The TPA3004D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCCshorts. When a short-circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the protection circuitry will again activate. The trip-point for the short-circuit protection is nominally set at 8 A.

For VCC> 15 V, two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to the TPS3004D2 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTN as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5 V at a minimum of 1 A output current and a dc blocking voltage rating of at least 30 V. The diodes must also be rated to operate at a junction temperature of 150°C. If VCC< 15 V, the Schottky diodes are not required for short circuit protection.

If short-circuit protection is not required, the Schottky diodes may be omitted.

THERMAL PROTECTION

Thermal protection on the TPA3004D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20°C. The device begins normal operation at this point with no external system interaction.

THERMAL CONSIDERATIONS: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE

To calculate the maximum ambient temperature, the following equation may be used:

where: TJ= 125°C

= 19°C/W spacer 2-Layer PCB, 5 sq. in. copper, see Figure 47. (8)

To estimate the power dissipation, the following equation may be used:

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Page 33

Dissipated

= P

O(average)

x ((1 / Efficiency) – 1)

= ~75% for a 4-Ω load

TPA3004D2

www.ti.com

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

(9)

Example. What is the maximum ambient temperature for an application that requires the TPA3004D2 to drive 10 W into an 8-Ω speaker (stereo)?

Dissipated

Amax

= 20 W x ((1 / 0.85) – 1) = 3.5 W space (PO= 10 W * 2)

= 125°C – (19°C/W x 3.5 W) = 58.5°C

This calculation shows that the TPA3004D2 can drive 10 W of continuous RMS power per channel into an 8-Ω speaker up an ambient temperature of 58.5°C.

Figure 47 and Figure 48 show the results of several thermal experiments conducted with the TPA3004D2. Both

figures show that the best thermal performance can be achieved with more copper area for heat dissipation and an adequate number of thermal vias.

Figure 47 shows two curves for a 2-layer and 4-layer PCB. The 2-layer PCB layout was tightly controlled with a

fixed amount of 2 oz. copper on the bottom layer of the PCB. The amount of copper is shown on the x-axis. Nine thermal vias of 13 mil (0.33mm) diameter were drilled under the PowerPad and connected to the bottom layer. The top layer only consisted of traces for signal routing.

The 4-layer PCB layout was also tightly controlled with a fixed amount of 2 oz. copper in middle GND layer. The top layer only consisted of traces for signal routing. The bottom and other middle layer were left blank. Nine thermal vias of 0.33mm diameter were drilled under the PowerPad and connected to the middle layer.

Figure 48 shows the effect of the number of thermal vias drilled under the PowerPad on the thermal performance

of the PCB. The experiment was conducted with a 2-layer PCB and 3 square inches of copper on the bottom layer. For the best thermal performance, at least 16 vias in a 4x4 pattern should be used under the PowerPad. Refer to the TPA3004D2 EVM User's Manual, SLOU115, for an example layout with a 4x4 via pattern. PCB gerber files are available at request.

PRINTED CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3004D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.

• Decoupling capacitors — The high-frequency 0.1-µF decoupling capacitors should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC(pin 33) terminals as possible. The V2P5 (pin 4) capacitor, AVDD(pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the device as possible. Large (10 µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3004D2 on the PVCCL, PVCCR, and AVCCterminals.

• Grounding — The AVCC(pin 33) decoupling capacitor, AVDD(pin 29) capacitor, V2P5 (pin 4) capacitor, COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26 and pin 30). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42, 43). Analog ground and power ground may be connected at the PowerPAD, which should be used as a central ground connection or star ground for the TPA3004D2. Basically, an island should be created with a single connection to PGND at the PowerPAD.

• Output filter — The ferrite EMI filter (Figure 41) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 40 should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground.

• PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils). The PowerPAD size measures 4.55 x 4.55 mm. Four rows of solid vias (four vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For additional information, refer to the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002.

For an example layout, see the TPA3004D2 Evaluation Module (TPA3004D2EVM) User Manual, TI (SLOU158). Both the EVM user manual and the PowerPAD application note are available on the TI web site at

http://www.ti.com.

Product Folder Link(s): TPA3004D2

Page 34

1 1.5 2 2.5 3 3.5 4 4.5 5

Copper Area – sq. Inches

THERMAL RESISTANCE

COPPER AREA 2-LAYER PCB

1 2 3 4 5

Copper Area – sq. Inches

THERMAL RESISTANCE

COPPER AREA 4-LAYER PCB

– Thermal Resistance –

C/W

– Thermal Resistance –

C/W

4 6 8 10 12 14 16

Thermal Via Quantity (13 Mil Diameter)

THERMAL RESISTANCE

THERMAL VIA QUANTITY 2-LAYER PCB

– Thermal Resistance –

C/W

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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Figure 47. Thermal Resistance

Figure 48. Thermal Resistance

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TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:

• Audio analyzer or spectrum analyzer

• Digital multimeter (DMM)

• Oscilloscope

• Twisted pair wires

• Signal generator

• Power resistor(s)

• Linear regulated power supply

• Filter components

• EVM or other complete audio circuit

Figure 49 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine

wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 kΩ). Conversely the analyzer-input impedance should be high. The output impedance, R the hundreds of milliohms and can be ignored for all but the power-related calculations.

Figure 49(a) shows a class-AB amplifier system. They take an analog signal input and produce an analog signal

output. These amplifier circuits can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 49(b), which requires low pass filters in most

cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.

, of the APA is normally in

OUT

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Page 36

Analyzer

20 Hz – 20 kHz

(a) Basic Class–AB

APA

Signal

Generator

Power Supply

Analyzer

20 Hz – 20 kHz

(b) Filter–Free and Traditional Class–D

Class–D APA

Signal

Generator

Power Supply

Low–Pass RC

Filter

Low–Pass RC

Filter

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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(1) For efficiency measurements with filter-free class-D, RLshould be an inductive load like a speaker.

Figure 49. Audio Measurement Systems

The TPA3004D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave.

DIFFERENTIAL INPUT AND BTL OUTPUT

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in Figure 50. The differential input is a balanced input, meaning the positive (+) and negative (–) pins will have the same impedance to ground. Similarly, the BTL output equates to a balanced output.

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Audio Power

Amplifier

Generator

Low–Pass

RC Filter

GEN

OUT

Analyzer

ANA

Low–Pass

RC Filter

ANA

Twisted–Pair Wire

Evaluation Module

Twisted–Pair Wire

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

Figure 50. Differential Input—BTL output Measurement Circuit

The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:

• Use a balanced source to supply the input signal.

• Use an analyzer with balanced inputs.

• Use twisted-pair wire for all connections.

• Use shielding when the system environment is noisy.

• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 4).

Table 4 shows the recommended wire size for the power supply and load cables of the APA system. The real

concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.

Table 4. Recommended Minimum Wire Size for Power Cables

OUT

(W) (Ω) (mW) (mW)

10 4 18 22 16 40 18 42

2 4 18 22 3.2 8.0 3.7 8.5 1 8 22 28 2.0 8.0 2.1 8.1

< 0.75 8 22 28 1.5 6.1 1.6 6.2

AWG Size

DC Power Loss AC Power Loss

CLASS-D RC LOW-PASS FILTER

An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).

The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 51. R is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for R system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops.

and C

ANA

. The filter components, R

ANA

Product Folder Link(s): TPA3004D2

and C

FILT

, can then be derived for the

FILT

Page 38

FILT

VL= V

OUT

ANA

FILT

To APA

GND

AP Analyzer InputRC Low–Pass Filters

Load

OUT

ANA

ANA)RFILT

1 ) j

fC+ 2Ǹ f

MAX

FILT

2p fC R

FILT

TPA3004D2

SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

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Figure 51. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs

The transfer function for this circuit is shown in Equation 10 where wO= REQCEQ, REQ= R (C

FILT

+ C

). The filter frequency should be set above f

ANA

, the highest frequency of the measurement

MAX

FILT

||R

and CEQ=

ANA

bandwidth, to avoid attenuating the audio signal. Equation 11 provides this cutoff frequency, fC. The value of R

must be chosen large enough to minimize current that is shunted from the load, yet small enough to

FILT

minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R rule of thumb is that R error to less than 1% for R

should be small (~100 Ω) for most measurements. This reduces the measurement

FILT

≥ 10 kΩ.

ANA

FILT

and R

ANA

. A

An exception occurs with the efficiency measurements, where R reduce the current shunted through the filter. C

must be decreased by a factor of ten to maintain the same

FILT

must be increased by a factor of ten to

FILT

cutoff frequency. See Table 2 for the recommended filter component values. Once fCis determined and R

is selected, the filter capacitance is calculated using Equation 11. When the

FILT

calculated value is not available, it is better to choose a smaller capacitance value to keep fCabove the minimum desired value calculated in Equation 12.

Table 5 shows recommended values of R

was originally calculated to be 28 kHz for an f

FILT

and C

of 20 kHz. C

MAX

based on common component values. The value of f

FILT

, however, was calculated to be 57000 pF, but

FILT

the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead, and f is 34 kHz, which is above the desired value of 28 kHz.

Table 5. Typical RC Measurement Filter Values

MEASUREMENT R

Efficiency 1000 Ω 5600 pF All other measurements 100 Ω 56000 pF

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FILT

(10) (11)

(12)

Page 39

TPA3004D2

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SLOS407E –FEBRUARY 2003–REVISED JANUARY 2011

REVISION HISTORY

Changes from Original (February 2003) to Revision A Page

• Changed the data sheet From: Product Preview To Production Data ................................................................................. 1

Changes from Revision A (March 2003) to Revision B Page

• Updated the FUNCTIONAL BLOCK DIAGRAM ................................................................................................................... 3

• Updated Figure 35 .............................................................................................................................................................. 20

• Updated Figure 36 .............................................................................................................................................................. 21

• Changed Figure 39 title From: Cutoff Frequency of 41 kHz, To: Cutoff Frequency of 27 kHz, ......................................... 24

• Changed Figure 39 title From: Cutoff Frequency of 41 kHz, To: Cutoff Frequency of 27 kHz, ......................................... 25

• Changed text in section SELECTION OF COSC AND ROSC From: ROSC (pin 20) and COSC (pin 21) To: ROSC

(pin 27) and COSC (pin 28) ................................................................................................................................................ 29

• Added three paragraphs to the section BSN and BSP CAPACITORS .............................................................................. 30

• Added two paragraphs to the section SHORT-CIRCUIT PROTECTION ........................................................................... 32

• Added Note 1 to Figure 49 ................................................................................................................................................. 36

Changes from Revision B (August 2003) to Revision C Page

• Added 10µF between AVDD and AGND in Figure 35 ........................................................................................................ 20

• Updated Figure 36 .............................................................................................................................................................. 21

• Added section POWER-OFF POP REDUCTION ............................................................................................................... 32

Changes from Revision C (January 2004) to Revision D Page

• Changed the P

Test Condition From: RL= 8 Ω To: RL= 8 Ω, VCC= 15 V ................................................................... 7

O(max)

Changes from Revision D (September 2010) to Revision E Page

• Replaced the Dissipations Ratings table with the Thermal Information table. ..................................................................... 5

Product Folder Link(s): TPA3004D2

Page 40

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

TPA3004D2PHP ACTIVE HTQFP PHP 48 250 Green (RoHS

TPA3004D2PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS

TPA3004D2PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS

TPA3004D2PHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-4-260C-72 HR -40 to 85 TPA3004D2

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

6-Jun-2013

Samples

Addendum-Page 1

Page 41

PACKAGE OPTION ADDENDUM

www.ti.com

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

6-Jun-2013

Addendum-Page 2

Page 42

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPA3004D2PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 43

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPA3004D2PHPR HTQFP PHP 48 1000 367.0 367.0 38.0

Pack Materials-Page 2

Page 44

Page 45

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