Datasheet TP3054WM, TP3054N, TP3054N-X Datasheet (NATIONAL SEMICONDUCTOR)

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Page 1

TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO

Family

TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family

August 1994

General Description

The TP3054, TP3057 family consists of m-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded m-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.

Figure 1

, and a serial PCM

Connection Diagrams

Dual-In-Line Package

Features

Complete CODEC and filtering system (COMBO) including: Ð Transmit high-pass and low-pass filtering Ð Receive low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law or A-law compatible COder and DECoder Ð Internal precision voltage reference Ð Serial I/O interface Ð Internal auto-zero circuitry

m-law, 16-pinÐTP3054

A-law, 16-pinÐTP3057

Designed for D3/D4 and CCITT applications

5V operation

Low operating powerÐtypically 50 mW

Power-down standby modeÐtypically 3 mW

Automatic power-down

TTL or CMOS compatible digital interfaces

Maximizes line interface card circuit density

Dual-In-Line or surface mount packages

See also AN-370, ‘‘Techniques for Designing with CODEC/Filter COMBO Circuits’’

Plastic Chip Carriers

Top View

Order Number TP3054J or TP3057J

See NS Package Number J16A

Order Number TP3054N or TP3057N

See NS Package Number N16A

Order Number TP3054WM or TP3057WM

See NS Package Number M16B

COMBOÉand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.

TL/H/5510

TL/H/5510– 1

TL/H/5510– 10

Top View

Order Number TP3057V

See NS Package Number V20A

Page 2

Block Diagram

Pin Description

Symbol Function

GNDA Analog ground. All signals are referenced

O Analog output of the receive power ampli-

BCLKR/CLKSEL The bit clock which shifts data into DRaf-

MCLK

/PDN Receive master clock. Must be

Negative power supply pin.

5Vg5%.

to this pin.

fier.

Positive power supply pin.

5Vg5%.

Receive frame sync pulse which enables BCLK

to shift PCM data into DR.FSRis

an 8 kHz pulse train. See

Figures 2

and

for timing details.

Receive data input. PCM data is shifted into D

following the FSRleading edge.

ter the FS 64 kHz to 2.048 MHz. Alternatively, may

leading edge. May vary from

be a logic input which selects either

1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK

is used for both transmit and re-

ceive directions (see Table I).

1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK

, but

FIGURE 1 TL/H/5510– 2

Symbol Function

should be synchronous with MCLK formance. When MCLK ously low, MCLK ing. When MCLK high, the device is powered down.

MCLK

Transmit master clock. Must be 1.536 MHz,

1.544 MHz or 2.048 MHz. May be asynchronous with MCLK synchronous operation.

Transmit frame sync pulse input which enables

BCLK an 8 kHz pulse train, see

. Best performance is realized from

to shift out the PCM data on DX.FSXis

is connected continu-

is selected for all internal tim-

is connected continuously

Figures 2

for best per-

and3for

timing details.

BCLK

The bit clock which shifts out the PCM data on

. May vary from 64 kHz to 2.048 MHz, but

must be synchronous with MCLK

The TRI-STATEÉPCM data output which is en-

abled by FS

Open drain output which pulses low during the

encoder time slot.

Analog output of the transmit input amplifier.

Used to externally set gain.

IbInverting input of the transmit input amplifier.

VFXIaNon-inverting input of the transmit input amplifi-

er.

Page 3

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the D outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLK

/PDN pin

ent. Thus, 2 power-down control modes are available. The first is to pull the MCLK hold both FS will power-down approximately 1 ms after the last FS FS

pulse. Power-up will occur on the first FSXor FS

pulse. The TRI-STATE PCM data output, DX, will remain in

and

FSXand/or FSRpulses must be pres-

/PDN pin high; the alternative is to

and FSRinputs continuously lowÐthe device

the high impedance state until the second FS

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLK and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLK and a high level powers down the device. In either case, MCLK

will be selected as the master clock for both the

transmit and receive circuits. A bit clock must also be applied to BCLK select the proper internal divider for a master clock of 1.536

and the BCLKR/CLKSEL can be used to

/PDN powers up the device

MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.

With a fixed level on the BCLK selected as the bit clock for both the transmit and receive

/CLKSEL pin, BCLKXwill be

directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLK CLKSEL. In this synchronous mode, the bit clock, BCLK may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLK

Each FSXpulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled D bit clock periods, the TRI-STATE D high impedance state. With an FS latched via the D BCLK MCLK

output on the positive edge of BCLKX. After 8

input on the negative edge of BCLKX(or

if running). FSXand FSRmust be synchronous with

X/R

output is returned to a

pulse, PCM data is

TABLE I. Selection of Master Clock Frequencies

Master Clock

BCLKR/CLKSEL

Frequency Selected

TP3057 TP3054

Clocked 2.048 MHz 1.536 MHz or

0 1.536 MHz or 2.048 MHz

1.544 MHz

1 2.048 MHz 1.536 MHz or

and VFRO

pulse.

1.544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive clocks may be applied. MCLK

2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the

and MCLKRmust be

TP3054, and need not be synchronous. For best transmission performance, however, MCLK with MCLK logic levels to the MCLK connect MCLK Description). For 1.544 MHz operation, the device automati-

cally compensates for the 193rd clock pulse each frame. FS

with MCLK and must be synchronous with BCLK

, which is easily achieved by applying only static

starts each encoding cycle and must be synchronous

and BCLKX.FSRstarts each decoding cycle

/PDN pin. This will automatically

to all internal MCLKRfunctions (see Pin

clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLK 64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a

should be synchronous

. BCLKRmust be a

and BCLKRmay operate from

long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FS with timing relationships specified in during a falling edge of BCLK BCLK output the sign bit. The following seven rising edges clock

and FSR, must be one bit clock period long,

enables the DXTRI-STATE output buffer, which will

Figure 2

, the next rising edge of

. With FSXhigh

out the remaining seven bits, and the next falling edge disables the D BCLK of BCLK edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or

asynchronous operating mode.

output. With FSRhigh during a falling edge of

(BCLKXin synchronous mode), the next falling edge

latches in the sign bit. The following seven falling

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses, FS

and FSR, must be three or more bit clock periods long,

with timing relationships specified in transmit frame sync, FS short or long frame sync pulses are being used. For 64 kHz

, the COMBO will sense whether

Figure 3

. Based on the

operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D with the rising edge of FS whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLK the remaining seven bits. The D falling BCLK FS

receive frame sync pulse, FS D

(BCLKXin synchronous mode). All four devices may utilize

going low, whichever comes later. A rising edge on the

to be latched in on the next eight falling edges of BCLK

TRI-STATE output buffer is enabled

or the rising edge of BCLKX,

rising edges clock out

output is disabled by the

edge following the eighth rising edge, or by

, will cause the PCM data at

the long frame sync pulse in synchronous or asynchronous mode.

In applications where the LSB bit is used for signalling with FS

two bit clock periods long, the decoder will interpret the

lost LSB as ‘‘(/2’’ to minimize noise and distortion.

Page 4

Functional Description (Continued)

TRANSMIT SECTION

The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see

Figure 4

in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (t table of Transmission Characteristics). The FS pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D at the next FSXpulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms

. The low noise and wide bandwidth allow gains

) of nominally 2.5V peak (see

MAX

frame sync

(due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or m-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/ power amplifer capable of driving a 600X load to a level of

7.2 dBm. The receive section is unity-gain. Upon the occurrence of FS falling edge of the next eight BCLK the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The

total decoder delay isE10 ms (decoder update) plus

, the data at the DRinput is clocked in on the

(BCLKX) periods. At

110 ms (filter delay) plus 62.5 ms((/2 frame), which gives approximately 180 ms.

Page 5

Absolute Maximum Ratings

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

to GNDA 7V

VBBto GNDA

Voltage at any Analog Input

or Output V

Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

are assured by correlation with other production tests and/or product design and characterization. All signals referenced to

5.0Vg5%; T

GNDA. Typicals specified at V

0.3V to V

0§Cto70§C by correlation with 100% electrical testing at T

5.0V, V

0.3V

5.0V, T

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE

Input Low Voltage 0.6 V

Input High Voltage 2.2 V

Output Low Voltage DX,I

Output High Voltage DX,I

SIG TS

SIG

R,IL

X,IL

R,IH

Input Low Current GNDAsV

Input High Current V

Output Current in High Impedance DX, GNDAsV State (TRI-STATE)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

IIXA Input Leakage Current

RIXA Input Resistance

2.5VsV

ROXA Output Resistance Closed Loop, Unity Gain 1 3 X

RLXA Load Resistance GS

CLXA Load Capacitance GS

VOXA Output Dynamic Range GSX,R

AVXA Voltage Gain VFXIato GS

FUXA Unity Gain Bandwidth 1 2 MHz

VOSXA Offset Voltage

VCMXA Common-Mode Voltage CMRRXAl60 dB

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RORF Output Resistance Pin VFRO13X

RF Load Resistance VFRO

CLRF Load Capacitance 500 pF

VOSRO Output DC Offset Voltage

POWER DISSIPATION (ALL DEVICES)

ICC0 Power-Down Current No Load (Note) 0.5 1.5 mA

IBB0 Power-Down Current No Load (Note) 0.05 0.3 mA

ICC1 Power-Up Active Current No Load 5.0 9.0 mA

IBB1 Power-Up Active Current No Load 5.0 9.0 mA

Note: I

and I

CC0

are measured after first achieving a power-up state.

BB0

Voltage at any Digital Input or

Output V

Operating Temperature Range

Storage Temperature Range

0.3V to GNDAb0.3V

25§Ctoa125§C

65§Ctoa150§C

Lead Temperature (Soldering, 10 seconds) 300§C

ESD (Human Body Model) 2000V

Latch-Up Immunitye100 mA on any Pin

25§C. All other limits

25§C.

3.2 mA 0.4 V

1.0 mA 0.4 V

3.2 mA, Open Drain 0.4 V

3.2 mA 2.4 V

1.0 mA 2.4 V

VIL, All Digital Inputs

2.5V, VFXIaor VFXI

10 10 mA

200 200 nA

10 MX

10 kX

50 pF

10 kX

2.5V 600 X

2.8 2.8 V

5000 V/V

20 20 mV

2.5 2.5 V

200 200 mV

Page 6

Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V

0.7V. See Definitions and Timing Conventions section for test methods information.

5.0Vg5%; T

5.0V, V

0§Cto70§C by correlation with 100% electrical testing at T

5.0V, T

25§C. All timing parameters are measured at V

25§C. All other limits are

2.0V and V

Symbol Parameter Conditions Min Typ Max Units

1/t

WMH

WML

SBFM

SFFM

WBH

WBL

HBFL

HBFS

SFB

DBD

DBTS

DZC

DZF

SDB

HBD

HBFl

WFL

Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz

Rise Time of Master Clock MCLKXand MCLK

Fall Time of Master Clock MCLKXand MCLK

BCLK

/CLKSEL Pin. 1.544 MHz

MCLK

and MCLK

2.048 MHz

Period of Bit Clock 485 488 15725 ns

Rise Time of Bit Clock BCLKXand BCLK

Fall Time of Bit Clock BCLKXand BCLK

Width of Master Clock High MCLKXand MCLK

Width of Master Clock Low MCLKXand MCLK

160 ns

Set-Up Time from BCLKXHigh First Bit Clock after the Leading 100 ns to MCLK

Falling Edge Edge of FS

Set-Up Time from FSXHigh Long Frame Only 100 ns to MCLK

Width of Bit Clock High V

Width of Bit Clock Low V

Falling Edge

2.2V 160 ns

0.6V 160 ns

Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync

Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync

Set-Up Time from Frame Sync Long Frame Only 80 ns to Bit Clock Low

Delay Time from BCLKXHigh Loade150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid

Delay Time to TSXLow Loade150 pF plus 2 LSTTL Loads 140 ns

Delay Time from BCLKXLow to C Data Output Disabled

Delay Time to Valid Data from C

or BCLKX, Whichever

Comes Later

0 pF to 150 pF 50 165 ns

0 pF to 150 pF 20 165 ns

Set-Up Time from DRValid to 50 ns BCLK

Hold Time from BCLK D

Set-Up Time from FS BCLK

Hold Time from BCLK to FS

Low

R/X

Low to 50 ns

Invalid

Low Period Long)

X/R

Low Period Long)

X/R

R/X

to Short Frame Sync Pulse (1 Bit Clock 50 ns

X/R

Low Short Frame Sync Pulse (1 Bit Clock 100 ns

X/R

Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long)

or FSR)

(FS

Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level)

50 ns

Page 7

Timing Diagrams

TL/H/5510– 3

FIGURE 2. Short Frame Sync Timing

Page 8

Timing Diagrams (Continued)

TL/H/5510– 4

FIGURE 3. Long Frame Sync Timing

Page 9

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for

5.0Vg5%, V

limits are assured by correlation with other production tests and/or product design and characterization. GNDA

1.02 kHz, V

5.0V, T

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V

25§C.

25§C. All other

0V, f

5.0V, V

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of Nominal Gain) (600X)

0 dBm0 1.2276 Vrms

MAX

Virtual Decision Valve Defined Max Overload Level Per CCITT Rec. G711 TP3054 (3.17 dBm0) 2.501 V

TP3057 (3.14 dBm0) 2.492 V

Transmit Gain, Absolute T

Transmit Gain, Relative to G

25§C, V

Input at GS TP3054/57

fe16 Hz

50 Hz

60 Hz

200 Hz

300 Hzb3000 Hz

f fe3300 Hz

3400 Hz

4000 Hz

4600 Hz and Up, Measure

5V, V

0 dBm0 at 1020 Hz

0.15 0.15 dB

40 dB

30 dB

1.8

0.15 0.15 dB

0.35 0.05 dB

0.7 0 dB

26 dB

0.1 dB

14 dB

32 dB

Response from 0 Hz to 4000 Hz

XAT

XAV

XRL

Absolute Transmit Gain Variation Relative to G with Temperature

Absolute Transmit Gain Variation Relative to G with Supply Voltage

Transmit Gain Variations with Sinusoidal Test Method Level Reference Level

Receive Gain, Absolute T

25§C, V

InputeDigital Code Sequence for

40 dBm0 toa3 dBm0 50 dBm0 tob40 dBm0 55 dBm0 tob50 dBm0

5V, V

10 dBm0

0.1 0.1 dB

0.05 0.05 dB

0.2 0.2 dB

0.4 0.4 dB

1.2 1.2 dB

0 dBm0 Signal at 1020 Hz

TP3054/57

RAT

RAV

RRL

Receive Gain, Relative to G

Absolute Receive Gain Variation Relative to G with Temperature

Absolute Receive Gain Variation Relative to G with Supply Voltage

fe0 Hz to 3000 Hz

3300 Hz

3400 Hz

4000 Hz

Receive Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an

0.15 0.15 dB

0.35 0.05 dB

0.7 0 dB

0.1 0.1 dB

0.05 0.05 dB

14 dB

Ideally Encoded PCM Level

40 dBm0 toa3 dBm0

50 dBm0 tob40 dBm0

55 dBm0 tob50 dBm0

Receive Output Drive Level R

600X

0.2 0.2 dB

0.4 0.4 dB

1.2 1.2 dB

2.5 2.5 V

Page 10

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are

guaranteed for V 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA

0V, fe1.02 kHz, V

5.0V, V

5.0V, T

5.0Vg5%, V

0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V

25§C.

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

Symbol Parameter Conditions Min Typ Max Units

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Transmit Delay, Absolute fe1600 Hz 290 315 ms

Transmit Delay, Relative to D

fe500 Hz–600 Hz 195 220 ms

600 Hz–800 Hz 120 145 ms

800 Hz–1000 Hz 50 75 ms

1000 Hz–1600 Hz 20 40 ms

1600 Hz–2600 Hz 55 75 ms

2600 Hz–2800 Hz 80 105 ms

fe2800 Hz–3000 Hz 130 155 ms

Receive Delay, Absolute fe1600 Hz 180 200 ms

Receive Delay, Relative to D

fe500 Hz–1000 Hz

1000 Hz–1600 Hz

1600 Hz–2600 Hz 70 90 ms

2600 Hz–2800 Hz 100 125 ms

b b

40 30

25 ms

20 ms

fe2800 Hz–3000 Hz 145 175 ms

NOISE

PPSR

NPSR

PPSR

NPSR

Transmit Noise, C Message TP3054 12 15 dBrnC0 Weighted

Transmit Noise, P Message TP3057

Weighted

Receive Noise, C Message PCM Code is Alternating Positive Weighted and Negative Zero Ð TP3054 8 11 dBrnC0

Receive Noise, P Message PCM Code Equals Positive Weighted Zero Ð TP3057

Noise, Single Frequency fe0 kHz to 100 kHz, Loop Around

Measurement, VF

Positive Power Supply Rejection, VFXI

Transmit V

Negative Power Supply Rejection, VFXI

Transmit V

Positive Power Supply Rejection, PCM Code Equals Positive Zero

Receive V

Negative Power Supply Rejection, PCM Code Equals Positive Zero

Receive V

50 dBm0

Measure VF

fe0 Hz–4000 Hz 40 dBC

Measure VF

5.0 V

0 kHz–50 kHz (Note 2) 40 dBC

5.0 V

100 mVrms

50 dBm0

100 mVrms

4 kHz–25 kHz 40 dB 25 kHz–50 kHz 36 dB

5.0 V

0 Hz–4000 Hz 40 dBC 4 kHz–25 kHz 40 dB

0 Vrms

100 mVrms

67 dBm0p

79 dBm0p

53 dBm0

fe25 kHz–50 kHz 36 dB

Page 11

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are

guaranteed for V 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA

0V, fe1.02 kHz, V

5.0V, V

5.0V, T

5.0Vg5%, V

0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V

25§C.

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

Symbol Parameter Conditions Min Typ Max Units

SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0,

30 dB

at the Channel Output 300 Hz to 3400 Hz Input PCM Code Applied

at D

4600 Hz–7600 Hz 7600 Hz–8400 Hz 8400 Hz–100,000 Hz

30 dB

40 dB

30 dB

DISTORTION

STD STD

Signal to Total Distortion Sinusoidal Test Method (Note 3)

Transmit or Receive

Half-Channel

3.0 dBm0Level 33 dBC

0 dBm0 tob30 dBm0 36 dBC

40 dBm0 29 dBC

XMT RCV 30 dBC

55 dBm0 14 dBC

XMT RCV 15 dBC

SFD

IMD Intermodulation Distortion Loop Around Measurement,

Single Frequency Distortion,

Transmit

Single Frequency Distortion,

Receive

VF Frequencies in the Range

4 dBm0 tob21 dBm0, Two

46 dB

41 dB

300 Hz–3400 Hz

CROSSTALK

Transmit to Receive Crosstalk, fe300 Hz–3400 Hz

X-R

0 dBm0 Transmit Level D

Receive to Transmit Crosstalk, fe300 Hz–3400 Hz, VFXIeMultitone

R-X

0 dBm0 Receive Level (Note 2)

Quiet PCM Code

75 dB

70 dB

ENCODING FORMAT AT DXOUTPUT

TP3054

m-Law

(Includes Even Bit Inversion)

TP3057

A-Law

VIN(at GSX)eaFull-Scale 10000000 10101010

VIN(at GSX)e0V

11111111 11010101

Ð01111111 01010101

VIN(at GSX)ebFull-Scale 00000000 00101010

Note 1: Measured by extrapolation from the distortion test result atb50 dBm0.

Note 2: PPSR

Note 3: Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law.

, NPSRX, and CT

are measured with ab50 dBm0 activation signal applied to VFXIa.

R-X

Page 12

Applications Information

POWER SUPPLIES

While the pins of the TP305X family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used.

All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decoupling capacitors should be connected from this common ground point to V possible.

For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus.

and VBB, as close to the device as

R1eZ1

R2e20Z1.Z2

Where: N

and

Also: Z

Where Z

and Z

T-Pad Attenuator

POWER IN

POWER OUT

impedance with short circuit termination

impedance with open circuit termination

q-Pad Attenuator

This common ground point should be decoupled to V V

with 10 mF capacitors.

and

RECEIVE GAIN ADJUSTMENT

For applications where a TP305X family CODEC/filter receive output must drive a 600X load, but a peak swing lower

than

2.5V is required, the receive gain can be easily ad-

justed by inserting a matched T-pad or

q-pad at the output.

Table II lists the required resistor values for 600X terminations. As these are generally non-standard values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600X is obtained if the output impedance of the attenuator is in the range 282X to 319X (assuming a perfect transformer).

20Z1.Z2

Note: See Application Note 370 for further details.

R3eZ1

Z1.Z2

2NSa1

TL/H/5510– 5

Page 13

Applications Information (Continued)

TABLE II. Attentuator Tables for Z1

dB R1 R2 R3 R4

0.1 1.7 26k 3.5 52k

0.2 3.5 13k 6.9 26k

0.3 5.2 8.7k 10.4 17.4k

0.4 6.9 6.5k 13.8 13k

0.5 8.5 5.2k 17.3 10.5k

0.6 10.4 4.4k 21.3 8.7k

0.7 12.1 3.7k 24.2 7.5k

0.8 13.8 3.3k 27.7 6.5k

0.9 15.5 2.9k 31.1 5.8k

1.0 17.3 2.6l 34.6 5.2k 2 34.4 1.3k 70 2.6k 3 51.3 850 107 1.8k 4 68 650 144 1.3k 5 84 494 183 1.1k 6 100 402 224 900 7 115 380 269 785 8 379 284 317 698 9 143 244 370 630

10 156 211 427 527 11 168 184 490 535 12 180 161 550 500 13 190 142 635 473 14 200 125 720 450 15 210 110 816 430 16 218 98 924 413 18 233 77 1.17k 386 20 246 61 1.5k 366

(All Values in X)

eZ2e

300X

Typical Synchronous Application

Note 1: XMIT gaine20clog

R1aR2

FIGURE 4

where (R1aR2)l10 KX.

TL/H/5510– 6

Page 14

Connection Diagrams (Continued)

Plastic Chip Carrier

Top View

Order Number TP3057V

See NS Package Number V20A

TL/H/5510– 7

Page 15

Physical Dimensions inches (millimeters)

Cavity Dual-In-Line Package (J)

Order Number TP3054J or TP3057J

NS Package Number J16A

Molded Small Outline Package (WM)

Order Number TP3054WM or TP3057WM

NS Package Number M16B

Page 16

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number TP3054N or TP3057N

NS Package Number N16A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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