Datasheet TOP264EG Specification

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Page 1

TOP264-271 TOPSwitch-JX Family

Integrated Off-Line Switcher with EcoSmart for Highly Efﬁcient Power Supplies

™

Technology

Product Highlights

EcoSmart – Energy Efcient

• Ideal for applications from 10 W to 245 W

• Energy efﬁcient over entire load range

• No-load consumption below 100 mW at 265 VAC

• Up to 750 mW standby output power for 1 W input at 230 VAC

High Design Flexibility for Low System Cost

• Multi-mode PWM control maximizes efﬁciency at all loads

• 132 kHz operation reduces transformer and power supply size

• 66 kHz option for highest efﬁciency requirements

• Accurate programmable current limit

• Optimized line feed-forward for line ripple rejection

• Frequency jittering reduces EMI ﬁlter cost

• Fully integrated soft-start for minimum start-up stress

• 725 V rated MOSFET

• Simpliﬁes meeting design derating requirements

Extensive Protection Features

• Auto-restart limits power delivery to <3% during overload faults

• Output short-circuit protection (SCP)

• Output over-current protection (OCP)

• Output overload protection (OPP)

• Output overvoltage protection (OVP)

• User programmable for hysteretic/latching shutdown

• Simple fast AC reset

• Primary or secondary sensed

• Line undervoltage (UV) detection prevents turn-off glitches

• Line overvoltage (OV) shutdown extends line surge withstand

• Accurate thermal shutdown with large hysteresis (OTP)

Advanced Package Options

™

• eDIP

• eSIP

• eSOP

• Extended creepage to DRAIN pin

• Heat sink is connected to SOURCE for low EMI

-12 package:

• 43 W / 117 W universal input power output capability with

PCB / metal heat sink

• Low proﬁle horizontal orientation for ultra-slim designs

• Heat transfer to both PCB and heat sink

• Optional external heat sink provides thermal impedance

equivalent to a TO-220

™

-7C package:

• 177 W universal input output power capability

• Vertical orientation for minimum PCB footprint

• Simple heat sink mounting using clip provides thermal

impedance equivalent to a TO-220

™

-12 package:

• 66 W universal input output power capability

• Low proﬁle surface mounted for ultra-slim designs

• Heat transfer to PCB via exposed pad and SOURCE pins

• Supports wave or reﬂow soldering

Figure 1. Typical Flyback Application.

eSIP-7C (E Package)

Figure 2. Package Options.

eSOP-12B (K Package)

eDIP-12B (V Package)

Description

TOPSwitch-JX cost effectively incorporates a 725 V power MOSFET, high-voltage switched current source, multi-mode PWM control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device.

Typical Applications

• Notebook or laptop adapter

• Generic adapter

• Printer

• LCD monitor

• Set-top box

• PC or LCD TV standby

• Audio ampliﬁer

Output Power Ratings

See next page.

www.powerint.com August 2012

This Product is Covered by Patents and/or Pending Patent Applications.

Page 2

TOP264-271

Output Power Table

85-265 VAC

Adapter

Open

Frame

Product

Adapter

TOP264EG/VG 30 W 62 W 20 W 43 W

TOP265EG/VG 40 W 81 W 26 W 57 W

TOP266EG/VG 60 W 119 W 40 W 86 W

TOP267EG/VG 85 W 137 W 55 W 103 W

TOP268EG/VG 105 W 148 W 70 W 112 W

TOP269EG/VG 128 W 162 W 80 W 120 W

TOP270EG/VG 147 W 190 W 93 W 140 W

TOP271EG/VG 177 W 244 W 118 W 177 W

PCB Copper Area

Open

Frame

Product

230 VAC ±15%

Adapter

TOP264VG 21 W 34 W 12 W 22.5 W TOP264KG 30 W 49 W 16 W 30 W TOP265VG 22.5 W 36 W 15 W 25 W TOP265KG 33 W 53 W 20 W 34 W TOP266VG 24 W 39 W 17 W 28.5 W TOP266KG 36 W 58 W 23 W 39 W TOP267VG 27.5 W 44 W 19 W 32 W TOP267KG 40 W 65 W 26 W 45 W TOP268VG 30 W 48 W 21.5 W 36 W TOP268KG 46 W 73 W 30 W 50 W TOP269VG 32 W 51 W 22.5 W 37.5 W TOP269KG 50 W 81 W 33 W 55 W TOP270VG 34 W 55 W 24.5 W 41 W TOP270KG 56 W 91 W 36 W 60 W TOP271VG 36 W 59 W 26 W 43 W TOP271KG 63 W 102 W 40 W 66 W

Table 1. Output Power Table.

Notes:

1. See Key Application Considerations section for more details.

2. Maximum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient temperature.

3. Maximum continuous power in an open frame design at +50 °C ambient temperature.

4. 230 VAC or 110/115 VAC with doubler.

5. Packages: E: eSIP-7C, V: eDIP-12, K: eSOP-12. See Part Ordering Information section.

Metal Heat Sink

230 VAC ±15%

Open

Frame

85-265 VAC

Adapter

Open

Frame

Rev. E 08/12

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TOP264-271

CONTROL (C)

EXTERNAL CURRENT

LIMIT (X)

VOLTAGE

MONITOR (V)

FREQUENCY (F)

SHUNT REGULATOR/

ERROR AMPLIFIER

Figure 3. Functional Block Diagram.

CURRENT

LIMIT

ADJUST

1 V

LINE

SENSE

5.8 V

4.8 V

STOP LOGIC

INTERNAL UV

COMPARATOR

STOP

MAX

OSCILLATOR WITH JITTER

66k/132k

F REDUCTION

SOFT START I

PS(UPPER)

PS(LOWER)

5.8 V

I (LIMIT)

ON/OFF

+ V

OV/

OVPV

MAX

PS(UPPER)

PS(LOWER)

PWM

SOFT

START

SOFT START

MAX

CLOCK

OFF

÷ 16

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

INTERNAL SUPPLY

SRQ

PS(UPPER)

PS(LOWER)

CURRENT LIMIT

COMPARATOR

CONTROLLED

TURN-ON

GATE DRIVER

SOURCE (S)

LEADING

EDGE

BLANKING

PI-4511-012810

DRAIN (D)

SOURCE (S)

Pin Functional Description

DRAIN (D) Pin:

High-voltage power MOSFET DRAIN pin. The internal start-up bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for drain current.

CONTROL (C) Pin:

Error ampliﬁer and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor.

EXTERNAL CURRENT LIMIT (X) Pin:

Input pin for external current limit adjustment remote-ON/OFF and device reset. A connection to SOURCE pin disables all functions on this pin. This pin should not be left ﬂoating.

VOLTAGE MONITOR (V) Pin:

Input for OV, UV, line feed-forward with DC overvoltage protection (OVP), remote-ON/OFF. A connection to the SOURCE pin disables all functions on this pin. This pin should not be left ﬂoating.

FREQUENCY (F) Pin:

Input pin for selecting switching frequency 132 kHz if connected to SOURCE pin and 66 kHz if connected to CONTROL pin. This pin should not be left ﬂoating.

reduction, output

MAX

NO CONNECTION (NC) Pin:

Internally not connected, ﬂoating potential pin.

E Package

(eSIP-7C)

7D5S4F3C2X1

Exposed Pad (On Bottom) Internally Connected to SOURCE Pin

Exposed Pad (Hidden) Internally Connected to SOURCE Pin

S 12

S 11

S 10

S 9

S 8

S 7

V 1

X 2

C 3

F 4

D 6

Exposed Pad Internally Connected to SOURCE Pin

V Package (eDIP-12B)

K Package

(eSOP-12B)

1 V

2 X

3 C

4 F

6 D

12 S

11 S

10 S

9 S

8 S

7 S

PI-5568-061011

SOURCE (S) Pin:

Output MOSFET source connection for high-voltage power return. Primary-side control circuit common and reference point.

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Figure 4. Pin Conguration (Top View).

Rev. E 08/12

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TOP264-271

12 kΩ

VUV = IUV × R V

For R

4 MΩ

VUV = 102.8 VDC V

MAX

For RIL = 12 kΩ

See Figure 37 for other resistor values (R I

= 4 MΩ

= 451 VDC

@100 VDC = 76% @375 VDC = 41%

LIMIT

) to select different

values.

LIMIT

Input

Voltage

CONTROL

Figure 5. Package Line-Sense and Externally Set Current Limit.

LS + VV

= 61%

(IV = IUV) (IV = IOV)

TOP264-271 Functional Description

Like TOPSwitch-HX, TOP264-271 is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high-voltage power MOSFET. During normal operation the duty cycle of the power MOSFET decreases linearly with increasing CONTROL pin current as shown in Figure 6.

In addition to the three terminal TOPSwitch features, such as the high-voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, the TOP264-271 incorporates many additional functions that reduce system cost, increase power supply performance and design ﬂexibility. A patented high-volta ge CMOS technology allows both the high-voltage power MOSFET and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip.

Three terminals, FREQUENCY, VOLTAGE-MONITOR, and EXTERNAL CURRENT LIMIT have been used t o implement some of the new funct ions. These terminals can be connect ed to the SOURCE pin to operate the TOP264-271 in a TOPSwitchlike three terminal mode. However, even in this three terminal mode, the TOP264-271 o ffers many transparent features that do not require any external components:

1. A fully integrated 17 ms soft-start signiﬁcantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during start-up.

2. A maximum duty cycle (DC storage capacitor, lower input voltage requirement and/or higher power capability.

3. Multi-mode operation optimizes and improves the power supply efﬁciency over the entire load range while maintaining good cross regulation in multi-output supplies.

4. Switching frequency of 132 kHz reduces the transformer size with no noticeable impact on EMI.

5. Frequency jittering reduces EMI in the full frequency mode at high-load condition.

) of 78% allows smaller input

MAX

Auto-Restart

PI-5579-111210

Figure 6. Control Pin Characteristics (Multi-Mode Operation).

Duty Cycle (%) Drain Peak Current

100

To Current Limit Ratio (%)

Full Frequency Mode

132

Frequency (kHz)

IB I

CD1

Jitter

C01

Slope = PWM Gain

Variable

Frequency

Mode

C02

C03

COFF

CONTROL

Current

CONTROL

Current

Low

Frequency

Mode

Multi-Cycle Modulation

CONTROL

Current

PI-5665-110609

6. Hysteretic over-temperature shutdown ensures thermal fault protection.

7. Packages with omitted pins and lead forming provide large drain creepage distance.

8. Reduction of the auto-restart duty cycle and frequency to improve the protection of the power supply and load during open-loop fault, short-circuit, or loss of regulation.

9. Tighter tolerances on I2f power coefﬁcient, current limit reduction, PWM gain and thermal shutdown threshold.

The VOLTAGE-MONITOR (V) pin is usually used for line sensing by connecting a 4 MW resistor from this pin to the rectiﬁed DC high-voltage bus to implement line overvoltage (OV), undervoltage (UV) and dual-slope line feed-forward with DC

MAX

reduction. In this mode, the value of the resistor determines the OV/UV thresholds and the DC

is reduced linearly with a dual

MAX

slope to improve line ripple rejection. In addition, it also provides another threshold to implement the latched and

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TOP264-271

hysteretic output overvoltage protection (OVP). The pin can also be used as a remote-ON/OFF using the IUV threshold.

The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to SOURCE through a resistor. This pin can also be used as a remote-ON/OFF input.

The FREQUENCY (F) pin sets the switching frequency in the full frequency PWM mode to the default value of 132 kHz when connected to SOURCE pin. A half frequency option of 66 kHz can be chosen by connecting this pin to the CONTROL pin instead. Leaving this pin open is not recommended.

CONTROL (C) Pin Operation

The CONTROL pin is a low impedance node that is capable of receiving a combined supply and feedback current. During normal operation, a shunt regulator is used to separate the feedback signal from the supply current. CONTROL pin voltage VC is the supply voltage for the control circuitry including the MOSFET gate driver. An external bypass capacitor closely connected between the CONTROL and SOURCE pins is required to supply the instantaneous gate drive current. The total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation. When rectiﬁed DC high-voltage is applied to the DRAIN pin during start-up, the MOSFET is initially off, and the CONTROL pin capacitor is charged through a switched high-voltage current source connected internally between the DRAIN and CONTROL pins. When the CONTROL pin voltage VC reaches approximately 5.8 V, the control circuitry is activated and the soft-start begins. The soft-start circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. If no external feedback/supply current is fed into the CONTROL pin by the end of the soft-start, the high-voltage current source is turned off and the CONTROL pin will start discharging in response to the supply current drawn by the control circuitry. If the power supply is designed properly, and no fault condition such as open-loop or shorted output exists, the feedback loop will close, providing external CONTROL pin current, before the CONTROL pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 V (internal supply undervoltage lockout threshold). When the externally fed current charges the CONTROL pin to the shunt regulator voltage of 5.8 V, current in excess of the consumption of the chip is shunted to SOURCE through an NMOS current mirror as shown in Figure 3. The output current of that NMOS current mirror controls the duty cycle of the power MOSFET to provide closed loop regulation. The shunt regulator has a ﬁnite low output impedance ZC that sets the gain of the error ampliﬁer when used in a primary feedback conﬁguration. The dynamic impedance ZC of the CONTROL pin together with the external CONTROL pin capacitance sets the dominant pole for the control loop.

When a fault condition such as an open-loop or shorted output prevents the ﬂow of an external current into the CONTROL pin, the capacitor on the CONTROL pin discharges towards 4.8 V. At 4.8 V, auto-restart is activated, which turns the output

MOSFET off and puts the control circuitry in a low current standby mode. The high-voltage current source turns on and charges the external capacitance again. A hysteretic internal supply undervoltage comparator keeps VC within a window of typically 4.8 V to 5.8 V by turning the high-voltage current source on and off as shown in Figure 8. The auto-restart circuit has a divide-by-sixteen counter, which prevents the output MOSFET from turning on again until sixteen discharge/charge cycles have elapsed. This is accomplished by enabling the output MOSFET only when the divide-by-sixteen counter reaches the full count (S15). The counter effectively limits TOP264-271 power dissipation by reducing the auto-restart duty cycle to typically 2%. Auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop.

Oscillator and Switching Frequency

The internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a triangular waveform for the timing of the pulse width modulator. This oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle.

The nominal full switching frequency of 132 kHz was chosen to minimize transformer size while keeping the fundamental EMI frequency below 150 kHz. The FREQUENCY pin, when shorted to the CONTROL pin, lowers the full switching frequency to 66 kHz (half frequency), which may be preferable in some cases such as noise sensitive video applications or a high efﬁciency standby mode. Otherwise, the FRE QUE NCY pin should be connected to the SOURCE pin for the default 132 kHz.

To further reduce the EMI level, the switching frequency in the full frequency PWM mode is jittered (frequency modulated) by approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for 132 kHz operation at a 250 Hz (typical) rate as shown in Figure 7. The jitter is turned off gradually as the system is entering the variable frequency mode with a ﬁxed peak drain current.

Pulse Width Modulator

The pulse width modulator implements multi-mode control by driving the output MOSFET with a duty cycle inversely proportional to the current into the CONTROL pin that is in excess of the internal supply current of the chip (see Figure 6). The feedback error signal, in the form of the excess current, is ﬁltered by an RC network with a typical corner frequency of 7 kHz to reduce the effect of switching noise in the chip supply current generated by the MOSFET gate driver.

To optimize power supply efﬁciency, four different control modes are implemented. At maximum load, the modulator operates in full frequency PWM mode; as load decreases, the modulator automatically transitions, ﬁrst to variable frequency PWM mode, then to low frequency PWM mode. At light load, the control operation switches from PWM control to multi-cyclemodulation control, and the modulator operates in multi-cyclemodulation mode. Although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess CONTROL pin current shown in Figure 6 is maintained through all three PWM

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Rev. E 08/12

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PI-4530-041107

Switching Frequency

TOP264-271

OSC

4 ms

Maximum Duty Cycle

The maximum duty cycle, DC

, is set at a default maximum

MAX

value of 78% (typical). However, by connecting the VOLTAGEMONITOR t o t he r ectiﬁed DC hi gh-voltage bus through a resistor with appropriate value (4 MW typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 V to 380 V, with dual gain slopes.

DRAIN

Time

Figure 7. Switching Frequency Jitter (Idealized V

Waveforms).

DRAIN

modes. Please see the following sections for the details of the operation of each mode and the transitions between modes.

Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the CONTROL pin current (IC) reaches IB. In this mode, the average switching frequency is kept constant at f cycle is reduced from DC

(pin selectable 132 kHz or 66 kHz). Duty

OSC

through the reduct ion o f t he on -time

MAX

when IC is increased beyond IB. This operation is identical to the PWM control of all other TOPSwitch families. TOP264-271 only operates in this mode if the cycle-by-cycle peak drain current stays above k and I

(set) is the current limit externally set via the EXTERNAL

LIMIT

PS(UPPER)

× I

LIMIT

(set), where k

is 55% (typical)

PS(UPPER)

CURRENT LIMIT (X) pin. Variable Frequency PWM mode: When peak drain current is

lowered to k

PS(UPPER)

× I

(set) as a result of power supply load

LIMIT

reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at k I

(set) while switching frequency drops from the initial full

LIMIT

frequency of f frequency of f

(132 kHz or 66 kHz) towards the minimum

OSC

(30 kHz typical). Duty cycle reduction is

MCM(MIN)

PS(UPPER)

accomplished by extending the off-time. Low Frequency PWM mode: When switching frequency

reaches f

(30 kHz typical), the PWM modulator starts to

MCM(MIN)

transition to low frequency mode. In this mode, switching frequency is held constant at f

and duty cycle is reduced,

MCM(MIN)

similar to the full frequency PWM mode, through the reduction of the on-time. Peak drain current decreases from the initial value of k k

PS(LOWER)

× I

PS(UPPER)

(set), where k

LIMIT

× I

(set) towards the minimum value of

LIMIT

is 25% (typical) and I

PS(LOWER)

LIMIT

(set)

is the current limit externally set via the X pin. Multi-Cycle-Modulation mode: When peak drain current is

lowered to k

PS(LOWER)

× I

(set), the modulator transitions to

LIMIT

multi-cycle-modulation mode. In this mode, at each turn-on, the modulator enables output switching for a period of T at the switching frequency of f at 30 kHz) with the peak drain current of k

(4 or 5 consecutive pulses

MCM(MIN)

PS(LOWER)

and stays off until the CONTROL pin current falls below I This mode of operation not only keeps peak drain current low

× I

(set),

LIMIT

MCM(MIN)

C(OFF)

but also minimizes harmonic frequencies between 6 kHz and 30 kHz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly suppressed.

Error Ampliﬁer

The shunt regulator can also perform the function of an error ampliﬁer in primary-side feedback applications. The shunt regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The CONTROL pin dynamic impedance ZC sets the gain of the error ampliﬁer. The CONTROL pin clamps external circuit signals to the VC voltage level. The CONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current IFB for the pulse width modulator.

On-Chip Current Limit with External Programmability

The cycle-by-cycle peak drain current limit circuit uses the output MOSFET ON-resistance as a sense resistor. A current limit comparator compares the output MOSFET ON-state drain to source voltage V current causes V

with a threshold voltage. High drain

DS(ON)

to exceed the threshold voltage and turns

DS(ON)

the output MOSFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in R

of the output MOSFET.

DS(ON)

The default current limit of TOP264-271 is preset internally. However, with a resistor connected between EXTERNAL CURRENT LIMIT (X) pin and SOURCE pin, current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. By setting current limit low, a larger TOP264-271 than necessary for the power required can be used to take advantage of the lower R

for higher efﬁciency/

DS(ON)

smaller heat sinking requirements. With a second resistor connected between the EXTERNAL CURRENT LIMIT (X) pin and the rectiﬁed DC high-voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an RCD clamp, this power limiting technique reduces maximum clamp voltage at high-line. This allows for higher reﬂected voltage designs as well as reducing clamp dissipation.

The leading edge blanking circuit inhibits the current limit comparator for a short time after the output MOSFET is turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectiﬁer reverse recovery time should not cause premature termination of the switching pulse. The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOSFET. During start-up and fault conditions the controller prevents excessive drain currents by reducing the switching frequency.

Line Undervoltage Detection (UV)

At power-up, UV keeps TOP264-271 off until the input line voltage reaches the undervoltage threshold. At power-down,

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TOP264-271

LINE

0 V

S14

S15

0 V

DRAIN

0 V

OUT

0 V

Note: S0 through S15 are the output states of the auto-restart counter

Figure 8. Typical Waveforms for (1) Power-Up (2) Normal Operation (3) Auto-Restart (4) Power-Down.

UV prevents auto-restart attempts after the output goes out of regulation. This eliminates power-down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. A single resistor connected from the VOLTAGE-MONITOR pin to the rectiﬁed DC high-voltage bus sets UV threshold during power-up. Once the power supply is successfully turned on, the UV threshold is lowered to 44% of the initial UV threshold to allow extended input voltage operating range (UV low threshold). If the UV low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until UV (high threshold) has been reached again. If the power supply

S13 S12 S0 S15 S13 S12 S0 S15S14

In order to reduce the no-load input power of TOP264-271 designs, the V pin operates at very low currents. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 10 mm of the V pin to minimize the V pin node area. The DC bus should then be routed to the line-sense resistors. Note that external capacitance must not be connected to the V pin as this

may cause misoperation of the V pin related functions. loses regulation before reaching the UV low threshold, the device will enter auto-restart. At the end of each auto-restart cycle (S15), the UV comparator is enabled. If the UV high threshold is not exceeded, the MOSFET will be disabled during the next cycle (see Figure 8). The UV feature can be disabled independent of the OV feature.

Hysteretic or Latching Output Overvoltage Protection (OVP)

The detection of the hysteretic or latching output overvoltage

protection (OVP) is through the trigger of the line overvoltage

threshold. The V pin voltage will drop by 0.5 V, and the

controller measures the e xternal a ttached impedance immediat ely

after this voltage drops. If IV exceeds I

Line Overvoltage Shutdown (OV)

The same resistor used for UV also sets an overvoltage threshold, which, once exceeded, will force TOP264-271 to stop switching instantaneously (after completion of the current switching cycle). If this condition lasts for at least 100 ms, the TOP264-271 output will be forced into off state. When the line voltage is back to normal with a small amount of hysteresis provided on the OV threshold to prevent noise triggering, the state machine sets to S13 and forces TOP264-271 to go through the entire auto-restart sequence before attempting to switch again. The ratio of OV and UV thresholds is preset at

4.5, as can be seen in Figure 9. When the MOSFET is off, the rectiﬁed DC high-voltage surge capability is increased to the voltage rating of the MOSFET (725 V), due to the absence of the reﬂected voltage and leakage spikes on the drain. The OV feature can be disabled independent of the UV feature.

longer than 100 ms, TOP264-271 will latch into a permanent

off-state for the latching OVP. It only can be reset if IX exceeds

= -27 mA (typ) or VC goes below the power-up reset

X(TH)

threshold (V

exceed I

OV(LS)

will initiate the line overvoltage and the hysteretic OVP. Their

behavior will be identical to the line overvoltage shutdown (OV)

that has been described in detail in the previous section.

During a fault condition resulting from loss of feedback, output

voltage will rapidly rise above the nominal voltage. The increase

in output voltage will also result in an increase in the voltage at

the output of the bias winding. A voltage at the output of the

bias winding that exceeds of the sum of the voltage rating of the

Zener diode connected from the bias winding output to the V

pin and V pin voltage, will cause a current in excess of IV to be

injected into the V pin, which will trigger the OVP feature.

S14

) and then back to normal. If IV does not

C(RESET)

S13

S12

S0 S15

S15

(336 mA typical)

OV(LS)

5.8 V

4.8 V

PI-4531-121206

or exceeds no longer than 100 ms, TOP264-271

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TOP264-271

If the power supply is operating under heavy load or low input line conditions when an open-loop occurs, the output voltage may not rise signiﬁcantly. Under these conditions, a latching shutdown will not occur until load or line conditions change. Nevertheless, the operation provides the desired protection by preventing signiﬁcant rise in the output voltage when the line or load conditions do change. Primary-side OVP protection with the TOP264-271 in a typical application will prevent a nominal 12 V output from rising above approximately 20 V under openloop conditions. If greater accuracy is required, a secondary sensed OVP circuit is recommended.

Line Feed-Forward with DC

Reduction

MAX

The same resistor used for UV and OV also implements line voltage feed-forward, which minimizes output line ripple and reduces power supply output sensitivity to line transients. Note that for the same CONTROL pin current, higher line voltage results in smaller operating duty cycle. As an added feature, the maximum duty cycle DC

is also reduced from 78% (typical) at a voltage slightly

MAX

lower than the UV threshold to 36% (typical) at the OV threshold. DC

of 36% at high-line was chosen to ensure that the power

MAX

capability of the TOP264-271 is not restricted by this feature under normal operation. TOP264-271 provides a better ﬁt to the ideal feed-forward by using two reduction slopes: -1% per mA for all bus voltage less than 195 V (typical for 4 MW line impedance) and

-0.25% per mA for all bus voltage more than 195 V.

Remote-ON/OFF

TOP264-271 can be turned on or off by controlling the current into

the VOLTA GE- MONIT OR pin or out from the EXTERNAL CURRENT

LIMIT pin. In addition, the VOLTAGE-MONITOR pin has a 1 V

threshold comparator connect ed at it s input. This voltage

threshold can also be used to perform remote-ON/OFF control.

When a signal is received at the VOLTAGE-MONITOR pin or the

EXTERNAL CURRENT LIMIT pin to disable the output through

any of the pin functions such as OV, UV and remote-ON/OFF,

TOP264-271 alwa ys comple tes its current switching cycle before

the output is forced off.

As seen above, the remote-ON/OFF feature can also be used

as a standby or power switch to turn off the TOP264-271 and

keep it in a very low power consumption state for indeﬁnitely long

periods. If the TOP264-271 is held in remote-off state for long

enough time to allow the CONTROL pin to discharge to the

internal supply undervoltage threshold of 4.8 V (approximately

32 ms for a 47 mF CONTROL pin capacitance), the CONTROL

pin goes into the hysteretic mode of regulation. In this mode,

the CONTROL pin goes through alt ernate charge and discharge

cycles between 4.8 V and 5.8 V (see CONTROL pin operation

section above) and runs entirely off the high-voltage DC input,

but with very low power consumption (<100 mW typical at

230 VAC with X pin open). When the TOP264-271 is remotely

Voltage Monitor and External Current Limit Pin Table*

Figure Number 13 14 15 16 17 18 19 20 21 22 23 24

Three Terminal Operation Line Undervoltage (UV) Line Overvoltage (OV) Line Feed-Forward (DC Output Overvoltage Protection (OVP) Overload Power Limiting (OPP) External Current Limit Remote-ON/OFF Device Reset Fast AC Reset AC Brown-Out *This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Conﬁgurations that are possible.

Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Conguration Options.

MAX

)

3 3 3 3 3

3 3 3 3

3 3 3 3 3 3

3 3 3

Rev. E 08/12

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Page 9

TOP264-271

V PinX Pin

Output MOSFET Switching

Current

Limit

Maximum

Duty Cycle

(Enabled)

(Disabled)

(Default)

LIMIT

(78%)

MAX

REM(N)

Disabled when supply output goes out of regulation

(Non-Latching) (Latching)

OV(LS)

Pin Voltage

-250 -200 -150 -100 -50 0 25 50 75 100 125 336

X and V Pins Current (µA)

Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of each functional pin operation refer to the Functional Description section of the data sheet.

Figure 9. VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Characteristics.

turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the CONTROL pin reaches 5.8 V. In the worst-case, the delay from remote-on to start-up can be equal to the full discharge/charge cycle time of the CONTROL pin, which is approximately 125 ms for a 47 mF CONTROL pin capacitor. This reduced consumption remote-off mode can eliminate expensive and unreliable in-line mechanical switches. It also allows for microprocessor controlled turn-on and turn-off sequences that may be required in certain applications such as inkjet and laser printers.

Soft-Start

The 17 ms soft-start sweeps the peak drain current and switching frequency linearly from minimum to maximum value by operating through the low frequency PWM mode and the variable frequency mode before entering the full frequency mode. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after being in hysteretic regulation of CONTROL pin voltage (VC), due to remote-off or thermal shutdown conditions. This effectively minimizes current and voltage stresses on the output MOSFET,

PI-5528-060409

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Rev. E 08/12

Page 10

TOP264-271

the clamp circuit and the output rectiﬁer during start-up. This feature also helps minimize output overshoot and prevents saturation of the transformer during start-up.

Shutdown/Auto-Restart (for OCP, SCP, OPP)

To minimize TOP264-271 power dissipation under fault conditions such as over current (OC), short-circuit (SC) or over power (OP), the shutdown/auto-restart circuit turns the power supply on and off at an auto-restart duty cycle of typically 2% if an out of regulation condition persists. Loss of regulation interrupts the external current into the CONTROL pin. VC regulation changes from shunt mode to the hysteretic autorestart mode as described in CONTROL pin operation section. When the fault condition is removed, the power supply output becomes regulated, VC regulation returns to shunt mode, and normal operation of the power supply resumes.

Hysteretic Over-Temperature Protection (OTP)

Temperature protection is provided by a precision analog circuit that turns the output MOSFET off when the junction temperature exceeds the thermal shutdown temperature (142 °C typical). When the junction temperature cools to below the lower hysteretic temperature point, normal operation resumes, thus providing automatic recovery. A large hysteresis of 75 °C (typical) is provided to prevent overheating of the PC board due to a continuous fault condition. VC is regulated in hysteretic

mode, and a 4.8 V to 5.8 V (typical) triangular waveform is present on the CONTROL pin while in thermal shutdown.

Bandgap Reference

All critical TOP264-271 internal voltages are derived from a temperature-compensated bandgap reference. This voltage reference i s used to g ener ate all other internal current referen ces, which are trimmed to accurately set the switching frequency, MOSFET gate drive current, current limit, and the line OV/UV/ OVP thresholds. TOP264-271 has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances.

High-Voltage Bias Current Source

This high-voltage current source biases TOP264-271 from the DRAIN pin and charges the CONTROL pin external capacitance during start-up or hysteretic operation. Hysteretic operation occurs during auto-restart, remote-off and over-temperature shutdown. In this mode of operation, the current source is switched on and off, with an effective duty cycle of approximately 35%. This duty cycle is determined by the ratio of CONTROL pin charge (IC) and discharge currents (I

CD1

and I

CD2

). This current source is turned off during normal operation when the output MOSFET is switching. The effect of the current source switching will be seen on the DRAIN voltage waveform as small disturbances and is normal.

Rev. E 08/12

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Page 11

CONTROL (C)

EXTERNAL CURRENT LIMIT (X)

200 µA

VBG + V

TOP264-271

(Negative Current Sense - ON/OFF,

Current Limit Adjustment, OVP Latch Reset)

VOLTAGE MONITOR (V)

REF

400 µA

Figure 10. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplied Schematic.

(Voltage Sense, ON/OFF)

1 V

(Positive Current Sense - Undervoltage,

Overvoltage, ON/OFF, Maximum Duty

Cycle Reduction, Output Over-

voltage Protection)

PI-5567-030910

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Rev. E 08/12

Page 12

TOP264-271

Typical Uses of FREQUENCY (F) Pin

Input

Voltage

CONTROL

PI-2654-071700

Figure 11. Full Frequency Operation (132 kHz). Figure 12. Half Frequency Operation (66 kHz).

Input

Voltage

CONTROL

PI-2655-071700

Rev. E 08/12

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Page 13

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins

PI-6119-061011

V Package (eDIP-12)

Input

Voltage

E Package

(eSIP-7C)

CONTROL

X F

V X C SF D

S D

S 12

S 11

S 10

S 9 S 8

S 7

K Package (eSOP-12)

1 V

2 X

3 C

4 F

6 D

D C

Figure 13. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL

CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin.)

1 V 2 X

3 C 4 F

6 D

S 12

S 11 S 10

S 9 S 8

S 7

Figure 14. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.

Input

Voltage

CONTROL

TOP264-271

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

4 MΩR

@100 VDC = 76%

MAX

@375 VDC = 41%

MAX

451 VDC

LS + VV

PI-4717-120307

(IV = IUV) (IV = IOV)

Input

Voltage

VUV = IUV × R V

For R

= 4 MΩ

= 102.8 VDC

4 MΩ

OVP

DC DC

451 VDC

Sense Output Voltage

OVP

MAX

(IV = IUV)

LS + VV

(IV = IOV)

LS + VV

@ 100 VDC = 76% @ 375 VDC = 41%

D V

CONTROL

>3kΩ

OVP

PI-4719-120307

Figure 15. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Hysteretic Output Overvoltage Protection.

4 MΩ

LS + VV

(IV = IOV)

= I

For Values Shown V

= 457.2 VDC

55 kΩ

1N4148

Input

Voltage

CONTROL

PI-4721-120307

Figure 17. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum

Duty Cycle Reduced at Low-Line and Further Reduction with Increasing Line Voltage.

Input

= RLS × I

4 MΩ

For Values Shown V

40 kΩ

UV + VV

= 103.8 VDC

Voltage

D V

6.2 V

CONTROL

PI-4720-120307

Figure 16. Line-Sensing for Undervoltage Only (Overvoltage Disabled).

Input

Voltage

CONTROL

For R

= 12 kΩ

= 61%

LIMIT

For R

= 19 kΩ

= 37%

LIMIT

See Figure 37 for other resistor values (R

PI-5580-111210

Figure 18. External Set Current Limit.

(IV = IUV)

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Rev. E 08/12

Page 14

TOP264-271

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)

Input

Voltage

2.5 MΩR

CONTROL

R 6 kΩ

100% @ 100 VDC

LIMIT

53% @ 300 VDC

LIMIT

PI-5465-061009

Figure 19. Current Limit Reduction with Line Voltage.

Input

Voltage

CONTROL

can be an optocoupler

output or can be replaced by a manual switch.

For R

16 kΩ

= 61%

LIMIT

= 37%

LIMIT

ON/OFF

PI-5531-072309

Figure 21. Active-On Remote-ON/OFF with Externally Set Current Limit,

and Latch Reset

12 kΩ

19 kΩ

Input

Voltage

QR can be an optocoupler output or can be replaced by a manual switch.

CONTROL

47 KΩ

ON/OFF

PI-5466-061009

Figure 20. Active-On (Fail Safe) Remote-ON/OFF, and Latch Reset.

VUV = IUV × R V

@100 VDC = 76%

4 MΩ

MAX

@375 VDC = 41%

MAX

can be an optocoupler

output or can be replaced by a manual switch.

16 kΩ

For R

LS + VV

LIMIT

ON/OFF

PI-5467-061009

Input

Voltage

CONTROL

Figure 22. Active-On Remote-ON/OFF with Line-Sense and External

Current Limit, and Latch Reset.

(IV = IUV)

(IV = IoV)

12 kΩ

= 61%

Input

Voltage

CONTROL

12 kΩ

4 MΩ

VUV = IUV x R V

For R

= 4 MΩ

= 102.8 VDC

= 451 VDC

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

For R

LIMIT

See Figure 37 for other resistor values

) to select different

values.

LIMIT

LS + VV

= 12 kΩ

= 61%

(IV = IUV) (IV = IoV)

PI-5565-111210

Input

Voltage

Typ. 65 VAC brownout threshold. <3 s AC latch reset time. Higher gain QR allows increasing R1/ decreasing C1 for lower no-load input power.

CONTROL

39 kΩ

4 MΩ

PI-5652-110609

1N4007

47 nF

Figure 23. Line Sensing and Externally Set Current Limit. Figure 24. Externally Set Current Limit, Fast AC Latch Reset and Brown-Out.

Rev. E 08/12

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Input

Page 15

PI-5667-030810

Application Example

TOP264-271

Low No-Load, High Efciency, 65 W, Universal Input Adapter Power Supply

The circuit shown in Figure 25 shows a 90 VAC to 265 VAC input, 19 V, 3.42 A output power supply, designed for operation inside a sealed adapter case type. The goals of the design were highest full load efﬁciency, highest a v era ge e fﬁciency (average of 25%, 50%, 75% and 100% load points), and very low no-load consumption. Additional requirements included latching output overvoltage shutdown and compliance to safety agency limited power source (LPS) limits. Measured efﬁciency and no-load performance is summarized in the table shown in the schematic which easily exceed current energy efﬁciency requirements.

In order to meet these design goals the following key design decisions were made.

PI Part Selection

• One device size larger selected than required for power

delivery to increase efﬁciency

The current limit programming feature of TOPSwitch-JX allows the selection of a larger device than needed for power delivery. This gives higher full load, low-line efﬁciency by reducing the MOSFET conduction losses (I

RMS

× R

) but maintains the

DS(ON)

overload power, transformer and other components size as if a smaller device had been used.

For this design one device size larger than required for power delivery (as recommended by the power table) was selected. This typically gives the highest efﬁciency. Further increases in device size often results in the same or lower efﬁciency due to the larger switching losses associated with a larger MOSFET.

Line-Sense Resistor Values

• Increasing line-sensing resistance from 4 MW to 10.2 MW to

reduce no-load input power dissipation by 16 mW

Line-sensing is provided by resistors R3 and R4 and sets the line undervoltage and overvoltage thresholds. The combined value of these resistors was increased from the standard 4 MW to 10 .2 MW. This reduced the resistor dissipation, and therefore contribution to no-load input power, from ~26 mW t o ~10 mW. To compensate the resultant change in the UV (turn-on) threshold resistor R2 0 w as a dded be tween t he CONTR OL and V OLTAGEMONITOR pins. This adds a DC current equal to ~16 mA into the VOLTAGE MONITOR pin, requiring only 9 mA to be provided via R3 and R4 to reach the VOLTAGE MONITOR pin UV (turn-on) threshold current of 25 mA and setting the UV threshold to 95 VDC.

This technique does effectively disable the line OV feature as the resultant OV threshold is raised from ~450 VDC to ~980 VDC. However in this design there was no impact as the value of input capacitance (C2) was sufﬁcient to allow the design to withstand differential line surges greater than 2 kV without the peak drain voltage reaching the BV

rating of U1.

DSS

Speciﬁc guidelines and detailed calculations for the value of R20 may be found in the TOPSwitch-JX Application Note (AN-47).

Clamp Conﬁguration – RZCD vs RCD

• An RZCD (Zener bleed) was selected over an RCD clamp to

give higher light load efﬁciency and lower no-load consumption

The clamp network is formed by VR2, C4, R5, R6, R11, R28, R29 and D2. It limits the peak drain voltage spike caused by leakage inductance to below the BV

rating of the internal

DSS

Input Voltage (VAC)

Full Power Efciency (%) 86.6 89.1

Average Efciency (%) 89.5

No-load Input Power (mW) 57.7

GBU8J

600 V

12 mH

2.2 MΩR22.2 MΩ

330 nF

275 VAC

200 µH

4 A

90 - 265

VAC

120 µF

400 V

90 230

115

88.4

89.8

59.7 86.7

5.1 MΩR710 MΩ

5.1 MΩ

11 kΩ

10 MΩ

R11

300 Ω

2.2 nF

R24

2.2 Ω

1 kV

VR2

SMAJ250A

300 Ω

R29

300 Ω

TOPSwitch-JX

TOP269EG

1000 pF

630 V

150 Ω

RS1K

CONTROL

R28

300 Ω

BAV19WS

R20

191 kΩ

MMBT4403

220 nF

25 V

1 nF

250 VAC

RM10

100 nF

50 V

C11

FL1

FL2

BAV21WS-

7-F

R14

20 Ω

4.7 kΩ

ZMM5244B-7

Figure 25. Schematic of High Efciency 19 V, 65 W, Universal Input Flyback Supply with Low No-load.

www.powerint.com

R12

VR1

1/8 W

6.8 Ω

1/8 W

470 pF

R25

20 Ω

R13

47 µF

16 V

C15 50 V

C12 1 nF

100 V

V30100C

R10

100 Ω

PS2501-

MMBT3904

C10

56 µF

35 V

U3B

1-H-A

R15 33 Ω

C13

470 µF

25 V

PS2501-

C22

100 nF

50 V

470 µF

U3A

1-H-A

C14 25 V

R16

20 kΩ

1.6 kΩ

6.8 nF

147 kΩ R27

10 kΩ

C16

22 nF

50 V

LMV431AIMF

R22

C19

50 V

R17

R19

20 kΩ

R18

10 kΩ

C21

10 nF

50 V

19 V, 3.42 A

RTN

Rev. E 08/12

Page 16

TOP264-271

TOPSwitch-JX MOSFET. This arrangement was selected over a standard RCD clamp to improve light load efﬁciency and no-load input power.

In a standard RCD clamp C4 would be discharged by a parallel resistor rather than a resistor and series Zener. In an RCD clamp the resistor value is selected to limit the peak drain voltage under full load and overload conditions. However under light or no-load conditions this resistor value now causes the capacitor voltage to di scharge si gniﬁcant ly as both the leakage inductance energy and switching frequency are lower. As the capacitor has to be recharged to above the reﬂected output voltage each switching cycle the lower capacitor voltage represents wasted energy. It has the effect of making the clamp dissipation appear as a signiﬁcant load just as if it were connected to the output of the power supply.

The RZCD arrangement solves this problem by preventing the voltage across the capacitor discharging below a minimum value (deﬁned by the voltage rating of VR2) and therefore minimizing clamp dissipation under light and no-loa d condit ions .

Resistors R6 and R28 provide damping of high frequency ringing to reduce EMI. Due to the resistance in series with VR2, limiting the peak current, standard power Zeners vs a TVS type may be used for lower cost (although a TVS type was selected due to availability of a SMD version). Diode D2 was selected to have an 800 V vs the typical 600 V rating due to its longer reverse recovery time of 500 ns. This allows some recovery of the clamp energy during the reverse recovery time of the diode improving efﬁciency. Multiple resistors were used in parallel to share dissipation as SMD components were used.

Feedback Conﬁguration

• A Darlington connection formed together with optocoupler

transistor to reduce secondary-side feedback current and therefore no-load input power.

• Low voltage, low current voltage reference IC used on

secondary-side to reduce secondary-side feedback current and therefore no-load input power.

• Bias winding voltage tuned to ~9 V at no-load, high-line to

reduce no-load input power.

Typically the feedback current into the CONTROL pin at high-line is ~3 mA. This current is both sourced from the bias winding (voltage across C10) and directly from the output. Both of these represent a load on the output of the power supply.

To minimize the dissipation from the bias winding under no-load conditions the number of bias winding turns and value of C10 was adjusted to give a minimum voltage across C10 of ~9 V. This is the minimum required to keep the optocoupler biased. To minimize the dissipation of the secondary-side feedback circuit Q2 was added to form a Darlington connection with U3B. This reduced the feedback current on the secondary to ~1 mA. The increased loop gain (due to the hFE of the transistor) was compensated by increasing the value of R16 and the addition of R25. A standard 2.5 V TL431 voltage reference was replaced with the 1.24 V LMV431 to reduce the supply current requirement from 1 mA to 100 mA.

Output Rectiﬁer Choice

• Higher current rating, low V

Schottky rectiﬁer diode selected

for output rectiﬁer.

A dual 15 A, 100 V Schottky rectiﬁer diode with a VF of 0.455 V at 5 A was selected for D5. This is a higher current rating than required to reduce resistive and forward voltage losses to improve both full load and average efﬁciency. The use of a 100 V Schottky was possible due to the high transformer primary to secondary turns ratio (V

= 110 V) which was in turn possible due to the

high-voltage rating of the TOPSwitch-JX internal MOSFET.

Increased Output Overvoltage Shutdown Sensitivity

• Transistor Q1 and VR1 added to improve the output over-

voltage shutdown sensitivity.

During an open-loop condition the output and therefore bias winding voltage will rise. When this exceeds the voltage of VR1 plus a VBE voltage drop Q1 turns on and current is fed into the VOLTAGE MONITOR pin. The addition of Q1 ensures that the current into the VOLTAGE MONITOR pin is sufﬁcient to exceed the latching shutdown threshold even when the output is fully loaded while the supply is operating at low-line as under this condition the output voltage overshoot is relatively small

Output overload power limitation is provided via the current limit programming feature of the X pin and R7, R8 and R9. Resistors R8 and R9 reduce the device current limit as a function of increasing line voltage to provide a roughly ﬂat overload power characteristic, below the 100 VA limited power source (LPS) requirement. In order to still meet this under a single fault condition (such as open circuit of R8) the rise in the bias voltage that occurs during an overload condition is also used to trigger a latching shutdown.

Rev. E 08/12

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Page 17

TOP264-271

Very Low No-Load, High Efciency, 30 W, Universal Input, Open Frame, Power Supply

The circuit shown in Figure 26 below shows an 85 VAC to 265 VAC input, 12 V, 2.5 A output power supply. The goals of the design were highest full load efﬁciency, average efﬁciency (average of 25%, 50%, 75% and 100% load points), very low noload consumption. A dditional r equir ements included la tching output overvoltage shutdown and compliance to safety agency limited power source (LPS) limits. Actual efﬁciency and no-load performance is summarized in the table shown in the schematic which easily exceed current energy efﬁciency requirements.

In order to meet these design goals the following key design decisions were made.

PI Part Selection

• Ambient of 40 °C allowed one device size smaller than

indicated by the power table

The device selected for this design was based on the 85-265 VAC, Open Frame, PCB heat sinking column of power table (Table 1). One device size smaller was selected (TOP266V vs TOP267V) due to the ambient speciﬁcation of 40 °C (vs the 50°C assumed in the power table) and the optimum PCB area and layout for the device heat sink. The subsequent thermal and efﬁciency data conﬁrmed this choice. The maximum device temperature was 107 °C at full load, 40 °C, 85 VAC, 47 Hz (worst-case conditions) and average efﬁciency exceeded 83% ENERGY STAR and EuP Tier 2 requirements.

Transformer Core Selection

• 132 kHz switching frequency allowed the selection of smaller

core for lower cost.

The size of the magnetic core is a function of the switching frequency. The choice of the higher switching frequency of 132 kHz allowed for the use of a smaller core size. The higher switching frequency does not negatively impact the efﬁciency in TOPSwitch-JX designs due its small drain to source capacitance (C

) as compared to that of discrete MOSFETs.

OSS

Line-Sense Resistor Values

• Increasing line-sensing resistance from 4 MW to 10.2 MW to

reduce no-load input power dissipation by 16 mW.

Line-sensing is provided by resistors R1 and R2 and sets the line undervoltage and overvoltage thresholds. The combined value of these resistors was increased from the standard 4 MW to 10 .2 MW. This reduces the current into the VOLTAGE MONITOR pin, and therefore contribution to no-load input po wer, from ~ 26 mW to ~10 mW. To compensate the resultant change in the UV threshold resistor R12 was added between the CONTROL and VOLTAGE-MONITOR pins. This adds a DC current equal to ~16 mA into the VOLTAGE MONITOR pin, requiring only 9 mA to be provided via R1 and R2 to reach the VOLTAGE MONITOR pin UV threshold current of 25 mA and setting the UV threshold to approximately 95 VDC.

This technique does effectively disable the line OV feature as the resultant OV threshold is raised from ~450 VDC to ~980 VDC. However in this design there was no impact as the value of input capacitance (C3) was sufﬁcient to allow the design to withstand differential line surges greater than 1 kV without the peak drain voltage reaching the BV

rating of U1.

DSS

Speciﬁc guidelines and detailed calculations for the value of R12 may be found in the TOPSwitch-JX Application Note.

Input Voltage (VAC)

Full Load Efciency (%) 81.25 86.21

Average Efciency (%) 85.13

No-load Input Power (mW) 60.8

14 mH

100 nF

275 VAC

3.15 A

85 - 264

VAC

85 230

115

83.94

84.97

61.98 74.74

1N4007D21N4007

C3 82 µF 400 V

1N4007D41N4007

5.1 MΩR310 MΩ

5.1 MΩ

10 MΩ

TOPSwitch-JX

R15

14.3 kΩ 1%

TOP266VG

P6KE180A

R5 10 kΩ 1/2 W

VR1

FR107

CONTROL

4.7 nF 1 kV

BAV19WS

191 kΩ

R12

C11 1 nF

250 VAC

EF25

VR3

ZMM5245B-7

100 nF

50 V

7,8

11,12

BAV21WS-

7-F

R16

6.8 Ω

1/8 W

C10

47 µF

25 V

C12 1 nF

200 V

10 Ω

LTV817D

Figure 26. Schematic of High Efciency 12 V, 30 W, Universal Input Flyback Supply with Very Low No-load.

47 µF

25 V

U2B

D8,9

SB560

R17

22 Ω

C14

680 µF

25 V

R18

110 Ω

C18

47 nF

50 V

C15

680 µF

25 V

3.3 µH

R19

470 Ω

D10

LL4148

U2A

LTV817D

LMV431A

C20

33 nF

50 V

C16

100 µF

25 V

R21

86.6 kΩ 1%

R23

10 kΩ

PI-5775-030810

12 V, 2.5 A

RTN

www.powerint.com

Rev. E 08/12

Page 18

TOP264-271

Clamp Conﬁguration – RZCD vs RCD

• An RZCD (Zener bleed) was selected over RCD to give higher

light load efﬁciency and lower no-load consumption.

The clamp network is formed by VR1, C4, R5 and D5. It limits the peak drain voltage spike caused by leakage inductance to below the BV

rating of the internal TOPSwitch-JX MOSFET.

DSS

This arrangement was selected over a standard RCD clamp to improve light load efﬁciency and no-load input power.

In a standard RCD clamp C4 would be discharged by a parallel resistor rather than a resistor and series Zener. In an RCD clamp the resistor value of R5 is selected to limit the peak drain voltage under full load and overload conditions. However under light or no-load conditions this resistor value now causes the capacitor voltage to discharge signiﬁcantly as both the leakage inductance energy and switching frequency are lower. As the capacitor has to be recharged to above the reﬂected output voltage each switching cycle the lower capacitor voltage represents wasted energy. It has the effect of making the clamp dissipation appear as a signiﬁcant load just as if it were connected to the output of the power supply.

The RZCD arrangement solves this problem by preventing the voltage across the capacitor discharging below a minimum value (deﬁned by the voltage rating of VR1) and therefore minimizing clamp dissipation under light and no-loa d condit ions . Zener VR1 is shown as a high peak dissipation capable TVS however a standard lower cost Zener may also be used due to the low peak current that component experiences.

In many designs a resistor value of less than 50 W may be used in series with C4 to damp out high frequency ringing and improve EMI but this was not necessary in this case.

Feedback Conﬁguration

• A high CTR optocoupler was used to reduce secondary bias

currents and no-load input power.

• Low voltage, low current voltage reference IC used on

secondary-side to reduce secondary-side feedback current and no-load input power.

• Bias winding voltage tuned to ~9 V at no-load, high-line to

reduce no-load input power.

To minimize the dissipation from the bias winding under no-load conditions the number of bias winding turns and value of C7 was adjusted to give a minimum voltage across C7 of ~9 V. This is the minimum required to keep the optocoupler biased and the output in regulation.

To minimize the dissipation of the secondary-side feedback circuit a high CTR (CTR of 300 – 600%) optocoupler type was used. This reduces the secondary-side opto-led current from ~3 mA to <~1 mA and therefore the effective load on the output. A standard 2.5 V TL431 voltage reference was replaced with the

1.24 V LMV431 to reduce the supply current requirement of this component from 1 mA to 100 mA.

Output Rectiﬁer Choice

• Use of high V

allows the use of a 60 V Schottky diode for

high efﬁciency and lower cost.

The higher BV

rating of the TOPSwitch-JX of 725 V

DSS

(compared to 600 V or 650 V rating of typical power MOSFETs) allowed a higher transformer primary to secondary turns ratio (reﬂected output voltage or VOR). This reduced the output diode voltage stress and allowed the use of cheaper and more efﬁcient 60 V (vs 80 V or 100 V) Schottky diodes. The efﬁciency improvement occurs due the lower forward voltage drop of the lower voltage diodes. Two parallel connected axial 5 A, 60 V Schottky rectiﬁer diodes were selected for both low-cost and high efﬁciency. This allowed PCB heat sinking of the diode for low cost while maintaining efﬁciency compared to a single higher current TO-220 packaged diode mounted on a heat sink. For this conﬁguration the recommendation is that each diode is rated at twice the output current and that the diodes share a common cathode PCB area for heat sinking so that their temperatures track. In practice the diodes current share quite effectively as can be demonstrated by monitoring their individual temperatures.

Output Inductor Post Filter Soft-Finish

• Inductor L2 used to provide an output soft-ﬁnish and eliminate

a capacitor.

To prevent output overshoot during start-up the voltage appearing across L2 is used to provide a soft-ﬁnish function. When the voltage across L2 exceeds the forward drop of U2A and D10 current ﬂows though the optocoupler LED and provides feedback to the primary. This arrangement acts to limit the rate of rise of the output voltage until it reaches regulation and eliminates the capacitor that is typically placed across U3 to provide the same function.

Key Application Considerations

TOPSwitch-JX vs. TOPSwitch-HX

Table 3 compares the features and performance differences between TOPSwitch-JX and TOPSwitch-HX. Many of the new features eliminate the need for additional discrete components. Other features increase the robustness of design, allowing cost savings in the transformer and other power components.

TOP264-271 Design Considerations

Power Table

The data sheet power table (Table 1) represents the maximum practical continuous output power based on the following conditions:

1. 12 V output.

2. Schottky or high efﬁciency output diode.

3. 135 V reﬂected voltage (VOR) and efﬁciency estimates.

4. A 100 VDC minimum DC bus for 85-265 VAC and 250 VDC minimum for 230 VAC.

5. Sufﬁcient heat sinking to keep device temperature ≤110 °C.

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Page 19

TOP264-271

TOPSwitch-HX vs. TOPSwitch-JX

Function TOPSwitch-HX TOPSwitch-JX TOPSwitch-JX Advantages

CONTROL current I 0% duty cycle

eDIP-12 / eSOP-12 packages

Breakdown voltage BV

Fast AC reset 3 external transistor circuits

Table 3. Comparison Between TOPSwitch-HX and TOPSwitch-JX.

C(OFF)

= IB + 3.4 mA

C(OFF)

(TOP256-258) IB = External bias current

Not available Available

Min. 700 V at TJ = 25 °C Min. 725 V at TJ = 25 °C

DSS

using the V pin

= IB + 1.6 mA

C(OFF)

(TOP266-268)

1 external transistor circuit using the X pin

6. Power levels shown in the power table for the V package device assume 6.45 cm2 of 610 g/m2 copper heat sink area in an enclosed adapter, or 19.4 cm2 in an open frame.

The provided peak power depends on the current limit for the respective device.

TOP264-271 Selection

Selecting the optimum TOP264-271 depends upon required maximum output power, efﬁciency, heat sinking constraints, system requirements and cost goals. With the option to externally reduce current limit, TOP264-271 may be used for lower power applications where higher efﬁciency is needed or minimal heat sinking is available.

Input Capacitor

The input capacitor must be chosen to provide the minimum DC voltage required for the TOP264-271 converter to maintain regulation at the lowest speciﬁed input voltage and maximum output power. Since TOP264-271 has a high DC

limit and an

MAX

optimized dual slope line feed forward for ripple rejection, it is possible to use a smaller input capacitor. For TOP264-271, a capacitance of 2 mF per watt is possible for universal input with an appropriately designed transformer.

Primary Clamp and Output Reﬂected Voltage V

A primary clamp is necessary to limit the peak TOP264-271 drain to source voltage. A Zener clamp requires few parts and takes up little board space. F or g ood efﬁciency, the clamp Zener should be selected to be at least 1 .5 times the output reﬂected voltage VOR, as this keeps the leakage spike conduction time short. When using a Zener clamp in a universal input application, a VOR of less than 135 V is recommended to allow for the absolute tolerances and temperature variations of the Zener. This will ensure efﬁcient operation of the clamp circuit and will also keep the maximum drain voltage below t he ra ted breakdown voltage of the TOP264-271 MOSFET. A high VOR is required to take full advantage of the wider DC

of TOP264-271. An RCD (or

MAX

RCDZ) clamp provides t i ghter clamp voltage tolerance than a Zener clamp and allows a VOR as high as 150 V . RCD clamp

• Reduced CONTROL current

• Better no-load performance (<0.1 W)

• Better standby performance

• 66/132 kHz frequency option for DIP style heat sink

less designs

• Better thermal performance for increased power

capability over DIP-8 / SMD-8 packages

• Simpliﬁes meeting customer derating requirements

(e.g. 80%)

• Extended line surge withstand

• Saves 5 components

dissipation can be minimized by reducing the external current limit as a function of input line voltage (see Figure 19) . The RCD clamp is more cost effective than the Zener clamp but requires more careful design (see Quick Design Checklist).

Output Diode

The output diode is selected for peak inverse voltage, output current, and thermal conditions in the applicati on (including heat sinking, air circulation, etc.). The higher DC

of TOP264-271,

MAX

along with an appropriate transformer turns ratio, can allow the use of a 80 V Schottky diode for higher efﬁciency on output voltages as high as 15 V.

Bias Winding Capacitor

Due to the low frequency operation at no-load, a bias winding capacitance of 10 mF minimum is recommended. Ensure a minimum bias winding voltage of >9 V at zero load for correct operation and output voltage regulation.

Soft-Start

Generally, a power supply experiences maximum stress at start-up before the feedback loop achieves regulation. For a period of 17 ms, the on-chip soft-start linearly increases the drain peak current and switching frequency from their low starting values to their respective maximum values. This causes the output voltage to rise in an orderly manner, allowing time for the feedback loop to take control of the duty cycle. This reduces the stress on the TOP264-271 MOSFET, clamp circuit and output diode(s), and helps prevent transformer saturation during start-up. Also, soft-start limits the amount of output voltage overshoot and, in many applications, eliminates the need for a soft-ﬁnish capacitor. Note that as soon as the loop closes the soft-start function ceases even if this is prior to the end of the 17 ms soft-start period.

EMI

The frequency jitter feature modulates the switching fr equency over a narrow band as a means to reduce conducted EMI peaks associated with the harmonics of the fundamental swit chi ng frequency. This is particularly beneﬁcial for average detection

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Page 20

TOP264-271

mode. As can be seen in Figures 27 and 28, the beneﬁts of jitter increase with the order of the switching harmonic due to an increase in frequency deviation. The FREQUENCY pin offers a switching frequency option of 132 kHz or 66 kHz. In applications that require heavy snubber on the drain node f or r educing high frequency radiated noise (f or example, video noise sensitive applications such as VCRs, DVDs, monitors, TVs, etc.), operating at 66 kHz will reduce snubber loss, resulting in better efﬁciency. Also, in applications where transformer size is not a concern, use of the 66 kHz option will provide lower EMI and higher efﬁciency. Note that the second harmonic of 66 kHz is still below 1 50 kHz, above which the conducted EMI speciﬁcations get much tighter. For 10 W or below, it is possible to use a simple inductor in place of a more costly AC input common mode choke to meet worldwide conducted EMI limits.

Transformer Design

It is recommended that the transformer be designed for maximum operating ﬂux density of 3000 Gauss and a peak ﬂux density of 4200 Gauss at maximum current limit. The turns ratio should be chosen for a reﬂected voltage (VOR) no greater than 135 V when using a Zener clamp or 150 V (max) when using an RCD clamp with current li mit r educt ion wit h line voltage (overload protection). For designs where operating current is signiﬁcant ly lower than the default current limit, it is recommended to use an externally set current limit close to the operating peak current to reduce peak ﬂux density and peak power (see Figure 18).

Standby Consumption

Frequency reduction can signiﬁcantly reduce power loss at light or no-load, especially when a Zener clamp is used. For very low secondary power consumption, use a TL431 regulator for feedback control. A typical TOP264-271 circuit automatically enters MCM mode at no-load and the low frequency mode at light load, which results in extremely low losses under no-load or standby conditions.

High Power Designs

The TOP264-271 family contains parts that can deliver up to 162 W. High power designs need special considerations. Guidance for high power designs can be found in the Design Guide for TOP264-271 (AN-47).

TOP264-271 Layout Considerations

The TOP264-271 has multiple pins and may operate at high power levels. The following guidelines should be carefully followed.

Primary Side Connections

Use a single point (Kelvin) connection at the negative terminal of the input ﬁlter capacitor for the SOURCE pin and bias winding return. This improves surge capabilities by returning surge currents from the bias winding directly to the input ﬁlter capacitor. The CONTROL pin bypass capacitor should be located as close as possible to the SOURCE and CONTROL pins, and its SOURCE connection trace should not be shared by the main MOSFET switching currents. All SOURCE pin referenced components connected to the VOLTAGE MONITOR (V) pin or EXTERNAL CURRENT LIMIT (X) pin should also be located

closely between their respective pin and SOURCE. Once again, the SOURCE connection t ra ce of these components should not be shared by the main MOSFET switching currents. It is very critical that SOURCE pin switching currents are returned to the input capacitor negative terminal through a separate trace that is not shared by t he component s connected to CONTROL , VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pins. This is because the SOURCE pin is also the controller ground reference pin. Any traces to the VOLTAGE MONITOR, EXTERNAL CURRENT LIMIT or CONTROL pins should be kept as short as possible and away from the DRAIN trace to prevent noise coupling. Voltage monitor resistors (RLS in Figures 14, 15, 19, 22, 23, 26, 30) and primary-side OVP circuit components V

in Figures (29, 30) should be located close to the

ZOV/ROV

VOLTAGE MONITOR pin to minimize the trace length on t he VOL TAGE MONITOR pin side. Resistors connected to the VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pin should be connected as close to the bulk capacitor positive terminal as possible while routing these connections away from the power switching circuitry. In addition to the 47 mF CONTROL pin

-10

Amplitude (dBµV)

-10

-20

0.15 1 10 30

EN55022B (QP) EN55022B (AV)

Frequency (MHz)

Figure 27. Fixed Frequency Operation without Jitter.

-10

Amplitude (dBµV)

-10

-20

0.15 1 10 30

TOPSwitch-JX (with jitter)

EN55022B (QP) EN55022B (AV)

Frequency (MHz)

Figure 28. TOPSwitch-JX Full Range EMI Scan (132 kHz with Jitter) with

Identical Circuitry and Conditions.

PI-2576-010600

PI-5583-090309

Rev. E 08/12

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Page 21

TOP264-271

capacitor, a high frequency bypass capacitor (CBP) in parallel should be used for better noise immunity. The feedback optocoupler output should also be located close to the CONTROL and SOURCE pins of TOP264-271 and away from the drain and clamp component traces. The primary-side clamp circuit should be positioned such t hat the loop area fr om t he transformer end (shar ed with DRAIN) and t he clamp capacit or is minimized. The bias winding return node should be connected via a dedicated trace directly to the bulk capacitor and not to the SOURCE pins. This ensures that surge currents are routed away from the SOURCE pins of the TOPSwitch-JX.

Y Capacitor

The Y capacitor should be connected close to the secondary output return pin(s) and the positive primary DC input pin of the transformer. If the Y capacitor is returned to the negative end of the input bulk capacitor (rather than the positive end) a dedicated trace must be used to make this connection. This is to “steer” leakage currents away from the SOURCE pins in case of a common-mode surge event.

Heat Sinking

The exposed pad of the E package (eSIP-7C), K package (eSOP-12) and the V package (eDIP-12) are internally electrically tied to the SOURCE pin. To avoid circulating currents, a heat sink attached to the exposed pad should not be electrically tied to any primary ground/source nodes on the PC board. On double sided boards, top side and bottom side ar eas connect ed with vias can be used to increase the effective heat sinking area. The K package exposed pad may be directly soldered to a copper area for optimum thermal transfer. In addition, sufﬁcient copper area should be provided at the anode and cathode leads of the output diode(s) for heat sinking. In Figure 29, a narrow trace is shown between the output rectiﬁer and output ﬁlter capacitor. This trace acts as a thermal relief between the rectiﬁer and ﬁlter capacitor to prevent excessive heating of the capacitor.

Quick Design Checklist

In order to reduce the no-load input power of TOP264-271 designs, the VOLTAGE MONITOR pin operates at very low current. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the VOLTAGE MONITOR pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or

power traces from other converters. If the line-sensing features are used, then the sense resistors must be placed within 10 mm of the VOLTAGE MONITOR pin to minimize the VOLTAGE MONITOR pin node area. The DC bus should then be routed to the line-sense resistors. Note that external capacitance must not be connected to the VOLTAGE MONITOR pin as this may cause misoperation of the VOLTAGE MONITOR pin related functions. As with any power supply design, all TOP264-271 designs should be veriﬁed on the bench to make sure that components speciﬁcations are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended:

1. Maximum drain voltage – Verify that peak VDS does not exceed 675 V at highest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just before the power supply goes into auto-restart (loss of regulation).

2. Maximum drain current – At maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of transformer saturation and excessive leading edge current spikes. TOP264-271 has a leading edge blanking time of 220 ns to prevent premature termination of the ON-cycle. Verify that the leading edge current spike is below the allowed current limit envelope (see Figure 34) for the drain current waveform at the end of the 220 ns blanking period.

3. Thermal check – At maximum output power, both minimum and maximum voltage and ambient temperature; verify that temperature speciﬁcations are not exceeded for TOP264271, transformer, output diodes and output capacitors. Enough thermal margin should be allowed for the part-topart variation of the R

of TOP264-271, as speciﬁed in

DS(ON)

the data sheet. The margin required can either be calculated from the values in the parameter table or it can be accounted for by connecting an external resistance in series with the DRAIN pin and attached to the same heat sink, having a resistance value that is equal to the difference between the measured R

of the device under test and the worst-case

DS(ON)

maximum speciﬁcation.

Design Tools

Up-to-date information on design tools can be found at the Power Integrations website: www.powerint.com

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Rev. E 08/12

Page 22

TOP264-271

Maximize Copper Area

for Optimum Heat Sinking

–

OUT

RLS1

RPL1

+–

Input Filter

RIL CBP

RPL2

RLS2

VZOV

R12

C10

ROV

R16

R5D5

Clamp Circuit

VR1

Transformer

C11

Capacitor

Figure 29. Layout Considerations for TOPSwitch-JX using V Package and Operating at 132 kHz.

Output Filter

Capacitors

Output

Rectifiers

Y-

Capacitor

C16

C18

C17

HF LC

Post-Filter

PI-5752-061311

Maximize Copper Area

for Optimum Heat Sinking

+–

Input Filter

Capacitor

RPL1

RIL

RLS1

RIL

CBP

–

OUT

CB+

ROV

RPL2

RLS2

C10

VZOV

R12

R16CBP

Output Filter

Capacitors

Transformer

C17

C18

C16

HF LC

Post-Filter

Output

VR1

C11

Rectiers

Y-

Capacitor

Clamp Circuit

PI-6173-081412

Figure 30. Layout Considerations for TOPSwitch-JX using K Package and Operating at 132 kHz.

Rev. E 08/12

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Page 23

TOP264-271

Input Filter

Capacitor

RLS2

RLS1

RPL1

CBP

ROV

Clamp Circuit

HS1

Isolation Barrier

Y-

Capacitor

C16 R12

HS2

Output

Rectifier

F X

VR1

RIL

Transformer

C17

Output Filter

Capacitors

HF LC

Post-Filter

PI-5793-030910

RPL2

VZOV

R10

JP2

R15

R17

R13

C21

C18

R21

R20

OUT

C19

Figure 31. Layout Considerations for TOPSwitch-JX using E Package and Operating at 132 kHz.

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Page 24

TOP264-271

Absolute Maximum Ratings

(2)

DRAIN Pin Peak Voltage .....................................-0.3 V to 725 V

DRAIN Pin Peak Current: TOP264 ................................... 2.08 A

DRAIN Pin Peak Current: TOP265 ................................... 2.72 A

DRAIN Pin Peak Current: TOP266 ................................... 4.08 A

DRAIN Pin Peak Current: TOP267 ................................... 5.44 A

DRAIN Pin Peak Current: TOP268 ................................... 6.88 A

DRAIN Pin Peak Current: TOP269 ................................... 7.73 A

DRAIN Pin Peak Current: TOP270 ................................... 9.00 A

DRAIN Pin Peak Current: TOP271 ................................. 11.10 A

CONTROL Pin Voltage ............................................-0.3 V to 9 V

CONTROL Pin Current .................................................. 100 mA

VOLTAGE MONITOR Pin Voltage ...........................-0.3 V to 9 V

CURRENT LIMIT Pin Voltage ..............................-0.3 V to 4.5 V

Thermal Resistance

Thermal Resistance: E Package

(qJA) .......................................... 105 °C/W

(qJC) .............................................. 2 °C/W

V Package

(qJA) ...........................68 °C/W

(3)

, 58 °C/W

(qJC) .............................................. 2 °C/W

K Package

(qJA) ...........................45 °C/W

(3)

, 38 °C/W

(qJC) .............................................. 2 °C/W

Conditions

Parameter Symbol

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 35

(Unless Otherwise Speciﬁed)

Control Functions Switching Frequency

in Full Frequency Mode (average)

Frequency Jitter Deviation

Frequency Jitter Modulation Rate

Maximum Duty Cycle DC

OSC

MAX

TJ = 25 °C

IC = I

CD1

FREQUENCY Pin

Connected to SOURCE

FREQUENCY Pin

Connected to CONTROL

132 kHz Operation ±5

66 kHz Operation ±2.5

FREQUENCY Pin Voltage ......................................-0.3 V to 9 V

Storage Temperature ...................................... -65 °C to 150 °C

Operating Junction Temperature ......................-40 °C to 150 °C

Lead Temperature

(1)

........................................................260 °C

Notes:

1. 1/16 in. from case for 5 seconds.

2. Maximum ratings speciﬁed may be applied one at a time without causing permanent damage to the product. Expo sure to Absolute Maximum Rating conditions for extended

periods of time may affect product reliability.

Notes:

(1)

1. Free standing with no heat sink.

(2)

2. Measured at the back surface of tab.

3. Soldered (including exposed pad for K package) to typical

(4)

application PCB with a heat sinking area of 0.36 sq. in. (232mm2),

(2)

2 oz. (610 g/m2) copper clad.

4. Soldered (including exposed pad for K package) to typical application PCB with a heat sinking area of 1 sq. in. (645 mm2),

(4)

2 oz. (610 g/m2) copper clad.

(2)

Min Typ Max Units

119 132 145

59.4 66 72.6

250 Hz

IV ≤ I

V(DC)

VV = 0 V

75 78 83

IV = 95 mA 30

kHz

Soft-Start Time t

PWM Gain DC

PWM Gain Temperature Drift

External Bias Current I

Rev. E 08/12

SOFT

REG

TJ = 25 °C 17 ms

TJ = 25 °C

IB < IC < I

C01

See Note C

TJ = 25 °C

IC ≥ I

C01

See Note A

See Note B -0.01 %/mA/°C

66 kHz Operation

TOP264-265 -62 -50 -40 TOP266-268 -54 -44 -34 TOP269-271 -50 -40 -30 TOP264-265 -61 -51 -41 TOP266-268 -60 -50 -40 TOP269-271 -57 -48 -38

TOP264-265 0.8 1.4 2.0

TOP269-271 1.0 1.6 2.2

%/mA

mATOP266-268 0.9 1.5 2.1

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Page 25

Conditions

Parameter Symbol

SOURCE = 0 V; TJ = -40 to 125 °C

(Unless Otherwise Speciﬁed)

Control Functions (cont.)

External Bias Current I

132 kHz Operation

66 kHz Operation

CONTROL Current at 0% Duty Cycle

C(OFF)

132 kHz Operation

Dynamic Impedance Z

IC = 2.5 mA; TJ = 25 °C, See Figure 33 13 21 25

Dynamic Impedance Temperature Drift

CONTROL Pin Internal Filter Pole

Upper Peak Current to Set Current Limit Ratio

Lower Peak Current to Set Current Limit Ratio

PS(UPPER)

PS(LOWER)

TJ = 25 °C

See Note C

TJ = 25 °C

See Note C

Multi-CycleModulation Switching

MCM(MIN)

TJ = 25 °C 30 kHz

Frequency Minimum Multi-Cycle-

Modulation On Period

MCM(MIN)

TJ = 25 °C 135 ms

Shutdown/Auto-Restart CONTROL Pin

Charging Current Charging Current

Temperature Drift

C(CH)

TJ = 25 °C

See Note B 0.5 %/°C

Auto-Restart Upper Threshold

C(AR)U

Voltage Auto-Restart Lower

Threshold Voltage

C(AR)L

Voltage Monitor (V) and External Current Limit (X) Inputs Auto-Restart

Hysteresis Voltage Auto-Restart

Duty Cycle Auto-Restart

Frequency

C(AR)HYST

Line Undervoltage Threshold Current and

TJ = 25 °C

Hysteresis (V Pin) Line Overvoltage

Threshold Current and

TJ = 25 °C

Hysteresis (V Pin)

TOP264-271

Min Typ Max Units

TOP264-265 0.9 1.5 2.1

TOP269-271 1.5 2.1 2.8 TOP264-265 2.9 3.9 TOP266-268 3.1 4.1 TOP269-271 3.3 4.3 TOP264-265 3.1 4.1 TOP266-268 3.4 4.4 TOP269-271 3.8 4.8

0.18 %/°C

7 kHz

50 55 60 %

25 %

VC = 0 V VC = 5 V

Threshold 22 25 27 mA

Hysteresis 14 mA

Threshold 107 112 117 mA

Hysteresis 4 mA

-5.0 -3.5 -1.0

-3.0 -1.8 -0.6

5.8 V

4.5 4.8 5.1 V

0.8 1.0 V

2 4 %

0.5 Hz

mATOP266-268 1.2 1.8 2.4

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Rev. E 08/12

Page 26

TOP264-271

Conditions

Parameter Symbol

Voltage Monitor (V) and External Current Limit (X) Inputs (cont.) Output Overvoltage

Latching Shutdown

OV(LS)

Threshold Current

SOURCE = 0 V; TJ = -40 to 125 °C

(Unless Otherwise Speciﬁed)

TJ = 25 °C 269 336 403 mA

Min Typ Max Units

V Pin Remote ON/OFF Voltage

X Pin Remote-ON/OFF and Latch Reset Negative Threshold Current and Hysteresis

V Pin Short-Circuit Current

X Pin Short-Circuit Current

V Pin Voltage (Positive Current)

V Pin Voltage Hysteresis (Positive Current)

X Pin Voltage (Negative Current)

Maximum Duty Cycle Reduction Onset Threshold Current

Maximum Duty Cycle Reduction Slope

REM(N)

V(SC)

V(HYST)

V(DC)

V(TH)

X(SC)

TJ = 25 °C 0.8 1.0 1.6 V

Threshold -35 -27 -20

TJ = 25 °C

Hysteresis 5

TJ = 25 °C VV = V

300 400 500 mA

Normal Mode -260 -200 -140

VX = 0 V

Auto-Restart Mode -95 -75 -55

IV = I

TOP264-TOP271 2.83 3.0 3.25 V

IV = I

0.2 0.5 V

IX = -50 mA 1.23 1.30 1.37

IX = -150 mA 1.15 1.22 1.29

IC ≥ IB, TJ = 25 °C 18.9 22.0 24.2 mA

< IV <48 mA -1.0

TJ = 25 °C

V(DC)

%/mA

IV ≥48 mA -0.25

Remote-OFF DRAIN Supply Current

Remote-ON Delay t

Remote-OFF Set-up Time

Frequency Input FREQUENCY Pin

Threshold Voltage FREQUENCY Pin

Input Current

Rev. E 08/12

D(RMT)

R(ON)

R(OFF)

X or V Pin Floating 0.6 1.0

= 150 V

DRAIN

From Remote-ON to Drain

V Pin Shorted to

CONTROL

66 kHz 3.0

1.0 1.6

Turn-On

See Note C

Minimum Time Before Drain

132 kHz 1.5

66 kHz 3.0

Turn-On to Disable Cycle

1.5

www.powerint.com

VF = V

132 kHz

10 55 90 mA

See Note C

TJ = 25 °C

See Note B 2.9 V

Page 27

Parameter Symbol

Circuit Protection

Self Protection Current Limit (See Note D)

Initial Current Limit I

Power Coefcient P

Leading Edge Blanking Time

Current Limit Delay t Thermal Shutdown

Temperature Thermal Shutdown

Hysteresis Power-Up Reset

Threshold Voltage

LIMIT

INIT

COEFF

LEB

IL(D)

C(RESET)

TOP264-271

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

(Unless Otherwise Speciﬁed)

TOP264

TJ = 25 °C

TOP265

TJ = 25 °C

TOP266

TJ = 25 °C

TOP267

TJ = 25 °C

TOP268

TJ = 25 °C

TOP269

TJ = 25 °C

TOP270

TJ = 25 °C

TOP271

TJ = 25 °C

di/dt = 270 mA/ms 1.209 1.30 1.391

di/dt = 350 mA/ms 1.581 1.70 1.819

di/dt = 530 mA/ms 2.371 2.55 2.728

di/dt = 625 mA/ms 2.800 3.01 3.222

di/dt = 675 mA/ms 3.023 3.25 3.478

di/dt = 720 mA/ms 3.236 3.48 3.723

di/dt = 870 mA/ms 3.906 4.20 4.494

di/dt = 1065 mA/ms 4.808 5.17 5.532

See Note C

TJ = 25 °C,

See Note E

IX ≤ - 165 mA 0.9 × I2f I2f 1.2 × I2f IX ≤ - 117 mA 0.9 × I2f I2f 1.2 × I2f

TJ = 25 °C, See Figure 34 220 ns

Figure 35 (S1 Open Condition) 1.75 3.0 4.25 V

Min Typ Max Units

0.70 ×

LIMIT(MIN)

100 ns

135 142 150 °C

75 °C

A2kHz

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Rev. E 08/12

Page 28

TOP264-271

Conditions

Parameter Symbol

Output

ON-State Resistance

DS(ON)

DRAIN Supply Voltage TJ ≤ 85 °C, See Note F

SOURCE = 0 V; TJ = -40 to 125 °C

(Unless Otherwise Speciﬁed)

TOP264

ID = 150 mA

TOP265

ID = 200 mA

TOP266

ID = 300 mA

TOP267

ID = 400 mA

TOP268

ID = 500 mA

TOP269

ID = 600 mA

TOP270

ID = 700 mA

TOP271

ID = 800 mA

TJ = 25 °C 5.4 6.25

TJ = 100 °C 8.35 9.70

TJ = 25 °C 4.1 4.70

TJ = 100 °C 6.3 7.30

TJ = 25 °C 2.8 3.20

TJ = 100 °C 4.1 4.75

TJ = 25 °C 2.0 2.30

TJ = 100 °C 3.1 3.60

TJ = 25 °C 1.7 1.95

TJ = 100 °C 2.5 2.90

TJ = 25 °C 1.45 1.70

TJ = 100 °C 2.25 2.60

TJ = 25 °C 1.20 1.40

TJ = 100 °C 1.80 2.10

TJ = 25 °C 1.05 1.20

TJ = 100 °C 1.55 1.80

Min Typ Max Units

OFF-State Drain Leakage Current

Breakdown Voltage

DSS

Rise Time t Fall Time t

Supply Voltage Characteristics

Control Supply/

CD1

Discharge Current

CD2

DSS

VV = Floating, Device Not Switching,

VDS = 580 V, TJ = 125 °C

VV = Floating, Device Not Switching,

TJ = 25 °C, See Note G

Measured in a Typical Flyback

Converter Application

TOP264-265 0.6 1.2 2.0

Output

MOSFET

Enabled VX, VV =

0 V

66 kHz

Operation

132 kHz

Operation

TOP266-268 0.9 1.4 2.3 TOP269-271 1.1 1.6 2.5 TOP264-265 0.8 1.4 2.1 TOP266-268 1.2 1.7 2.4 TOP269-271 1.5 2.1 2.9

Output MOSFET Disabled

VX, VV = 0 V

470 mA

725

100 ns

50 ns

0.3 0.5 1.2

Rev. E 08/12

www.powerint.com

Page 29

TOP264-271

NOTES: A. Derived during test from the parameters DC

B. For speciﬁcations with negative values, a negative temperature coefﬁcient corresponds to an increase in magnitude with increasing

temperature, and a positive temperature coefﬁcient corresponds to a decrease in magnitude with increasing temperature. C. Guaranteed by characterization. Not tested in production. D. For externally adjusted current limit values, please refer to Figures 36 and 37 (Current Limit vs. External Current Limit Resistance)

in the Typical Performance Characteristics section. The tolerance speciﬁed is only valid at full current limit. E. I2f calculation is based on typical values of I

pin connection. See f

speciﬁcation for detail.

OSC

F. The device will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops signiﬁcantly at temperatures below

0 °C. For reliable start-up at 18 V in sub-zero temperatures, designers must ensure that circuit capacitors meet recommended

capacitance values. G. Breakdown voltage may be checked against minimum BV

minimum BV

DSS

LIMIT

, IB and I

MAX

and f

OSC,

at 132 kHz.

C(OFF)

i.e. I

× f

LIMIT(TYP)

speciﬁcation by ramping the DRAIN pin voltage up to but not exceeding

DSS

, where f

OSC

= 66 kHz or 132 kHz depending on FREQUENCY

OSC

www.powerint.com

Rev. E 08/12

Page 30

TOP264-271

CONTROL Pin Current (mA)

DRAIN Current (normalized)

90%

DRAIN

VOLTAGE

D =

10%

0 V

PI-2039-033001

Figure 32. Duty Cycle Measurement.

(Blanking Time)

120

1.3

1.2

100

Dynamic

Impedance

PI-4737-061207

Slope

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

5 6 7 8 9

CONTROL Pin Voltage (V)

Figure 33. CONTROL Pin I-V Characteristic. Figure 34. Drain Current Operating Envelope.

LEB

INIT(MIN)

0 1 2 6 83

4 5 7

Time (µs)

PI-4758-061407

Figure 35. TOPSwitch-JX General Test Circuit.

Rev. E 08/12

(X and V Pins)

40 V

0-15 V

NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.

470 Ω

5 W

5-50 V

0-300 kΩ

0.1 µF47 µF

CONTROL

0-60 kΩ

SFX

www.powerint.com

Page 31

PI-5581-090309

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

-200 -150 -100 -50 0

Normalized Current Limit

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

Typical

Notes:

1. Maximum and Minimum levels are based on characterization.

2. T

= 0 OC to 125 OC.

Minimum

Maximum

Normalized Current Limit

Normalized di/dt

IX ( µA )

PI-5582-090309

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

0 5 10 15 20 25 30 35 40 45

( kΩ )

Normalized Current Limit (A)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

Normalized di/dt (mA/

Notes:

1. Maximum and Minimum levels are based on characterization.

2. T

= 0 OC to 125 OC.

3. Includes the variation of X pin voltage.

Typical

Maximum

Minimum

Normalized Current Limit

Normalized di/dt

Typical Performance Characteristics

Figure 36. Normalized Current Limit vs. X Pin Current.

TOP264-271

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Figure 37. Normalized Current Limit vs. External Current Limit Resistance.

Rev. E 08/12

Page 32

TOP264-271

Junction Temperature (°C)

Breakdown Voltage

(Normalized to 25

Junction Temperature (°C)

Output Frequency

(Normalized to 25

Junction Temperature (°C)

(Normalized to 25

1.2

PI-4739-061507

(Normalized to 25

Junction Temperature (°C)

Overvoltage Threshold

(Normalized to 25

Junction Temperature (°C)

Undervoltage Threshold

(Normalized to 25

Typical Performance Characteristics (cont.)

1.1

PI-176B-033001

°C)

1.2

1.0

°C)

0.8

1.0

0.6

0.4

0.2

0.9

-50 -25 0 25 50 75 100 125 150

Figure 38. Breakdown Voltage vs. Temperature. Figure 39. Frequency vs. Temperature.

-50 -25 0 25 50 75 100 125 150

1.2

1.0

ϒC)

0.8

0.6

°C)

1.0

0.8

0.6

PI-4760-061407

PI-4759-061407

0.4

Current Limit

0.2

-50 -25 0 25 50 75 100 125 150

Figure 40. Internal Current Limit vs. Temperature.

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50 -25 0 25 50 75 100 125 150

PI-4761-061407

0.4

Current Limit

0.2

-50 -25 0255075 100 125 150

Junction Temperature (°C)

Figure 41. External Current Limit vs. Temperature with RIL = 10.5 kW.

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50 -25 0 25 50 75 100 125 150

PI-4762-100610

Figure 42. Overvoltage Threshold vs. Temperature.

Rev. E 08/12

Figure 43. Undervoltage Threshold vs. Temperature.

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Page 33

Typical Performance Characteristics (cont.)

VOLTAGE MONITOR Pin Voltage (V)

EXTERNAL CURRENT LIMIT

CONTROL Current

(Normalized to 25

Onset Threshold Current

(Normalized to 25

Drain Pin Voltage (V)

CONTROL Pin Current (mA)

Drain Voltage (V)

DRAIN Current (A)

TOP264-271

5.5

4.5

3.5

2.5

0 100 200 500400300

VOLTAGE-MONITOR Pin Current (µA)

Figure 44. VOLTAGE-MONITOR Pin vs. Current.

1.2

1.0

°C)

0.8

0.6

PI-4740-060607

PI-4763-072208

1.6

VX = 1.354 - 1147.5 × IX + 1.759 × 106 ×

1.4

)2 with -180 µA < I

< -25 µA

1.2

1.0

0.8

0.6

Pin Voltage (V)

0.4

0.2

-200 -150 -50-100 0

EXTERNAL CURRENT LIMIT Pin Current (µA)

Figure 45. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.

1.2

1.0

°C)

0.8

0.6

PI-4741-110907

PI-4764-061407

0.4

0.2

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Figure 46. Control Current Out at 0% Duty Cycle vs. Temperature.

= 25 °C

CASE

= 100 °C

CASE

2 4 6 8 10 12 14 16 18 20

Scaling Factors: TOP271 1.62 TOP270 1.42 TOP269 1.17 TOP268 1.00 TOP267 0.85 TOP266 0.61 TOP265 0.42 TOP264 0.32

PI-5569-110409

0.4

0.2

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Figure 47. Maximum Duty Cycle Reduction Onset Threshold

Current vs. Temperature.

VC = 5 V

0.5

PI-4744-072208

-0.5

-1

-1.5

-2

-2.5

0 20 40 60 80 100

www.powerint.com

Figure 48. Output Characteristics.

Figure 49. IC vs. DRAIN Voltage.

Rev. E 08/12

Page 34

TOP264-271

DRAIN Capacitance (pF)

Drain Pin Voltage (V)

Remote OFF DRAIN Supply Current

(Normalized to 25

Typical Performance Characteristics (cont.)

10000

Scaling Factors: TOP271 1.62 TOP270 1.42 TOP269 1.17 TOP268 1.00

1000

TOP267 0.85 TOP266 0.61 TOP265 0.42 TOP264 0.32

100

0 100 200 300 400 500 600

Drain Pin Voltage (V)

Figure 50. C

vs. DRAIN Voltage.

OSS

°C)

1.2

1.0

0.8

PI-5570-090309

500

Scaling Factors: TOP271 1.62 TOP270 1.42

400

TOP269 1.17

300

TOP268 1.00 TOP267 0.85 TOP266 0.61 TOP265 0.42 TOP264 0.32

132 kHz

200

Power (mW)

100

0 200100 400 500 600300 700

Figure 51. DRAIN Capacitance Power.

PI-4745-061407

PI-5571-090309

66 kHz

0.6

0.4

0.2

-50

0-25 5025 10075 125 150

Junction Temperature (°C)

Figure 52. Remote-OFF DRAIN Supply Current vs. Temperature.

Rev. E 08/12

www.powerint.com

Page 35

eSIP-7C (E Package)

TOP264-271

0.403 (10.24)

0.397 (10.08)

0.325 (8.25)

0.320 (8.13)

Pin #1

I.D.

0.070 (1.78) Ref.

0.050 (1.27)

FRONT VIEW

10° Ref.

All Around

0.378 (9.60) Ref.

END VIEW

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead flash or protrusions.

5. Controlling dimensions in inches (mm).

0.021 (0.53)

0.019 (0.48)

0.048 (1.22)

0.046 (1.17)

0.019 (0.48) Ref.

Detail A

0.140 (3.56)

0.120 (3.05)

0.016 (0.41)

0.011 (0.28)

0.020 M 0.51 M C

0.060 (1.52) Ref.

0.081 (2.06)

0.077 (1.96)

0.290 (7.37) Ref.

0.519 (13.18) Ref.

0.016 (0.41) Ref.

0.047 (1.19)

6×

0.118 (3.00)

SIDE VIEW

0.020 (0.50)

0.023 (0.58)

0.027 (0.70)

DETAIL A

0.207 (5.26)

0.187 (4.75)

0.100 (2.54)

PIN 1

0.100 (2.54)

0.059 (1.50)

0.264 (6.70) Ref.

0.198 (5.04) Ref.

0.033 (0.84)

0.028 (0.71)

0.010 M 0.25 M C A B

BACK VIEW

0.050 (1.27)

0.155 (3.93)

0.100 (2.54) 0.100 (2.54)

MOUNTING HOLE PATTERN

(not to scale)

6×

PIN 7

0.059 (1.50)

PI-4917-061510

www.powerint.com

Rev. E 08/12

Page 36

TOP264-271

2. Dimensions noted are determined at the outer-

flash, but including any mismatch between the

Pin #1 I.D.

(Laser Marked)

0.004 [0.10] C B

0.325 [8.26] Max.

1 2 3 4 6

0.120 [3.05] Ref.

eDIP-12B (V Package)

Seating Plane

0.010 [0.25] Ref.

0.016 [0.41]

0.011 [0.28]

0.004 [0.10] C A

11×

0.400 [10.16]

0.059 [1.50] Ref, typ.

0.350 [8.89]

12 11 10 9 8 7 7 12

TOP VIEW

0.019 [0.48] Ref.

0.031 [0.80]

0.028 [0.72]

0.07 [1.78] 0.03 [0.76]

0.356 [9.04] Ref.

0.070 [1.78]

SIDE VIEW

0.225 [5.72] Max.

0.049 [1.23]

0.046 [1.16]

0.192 [4.87] Ref.

Mounting Hole Pattern Dimensions

0.400 [10.16]

0.412 [10.46] Ref.

0.306 [7.77] Ref.

Detail A

0.104 [2.65] Ref.

0.092 [2.34]

0.086 [2.18]

0.022 [0.56] Ref.

0.020 [0.51] Ref.

DETAIL A (Scale = 9X)

Drill Hole 0.03 [0.76] Round Pad 0.05 [1.27] Solder Mask 0.056 [1.42]

0.436 [11.08]

0.406 [10.32]

0.400 [10.16]

5 ±

END VIEW

0.028 [0.71] Ref.

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

most extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead

top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead flash or protrusions.

5. Controlling dimensions in inches [mm].

6. Datums A and B to be determined at Datum H.

7. Measured with the leads constrained to be perpendicular to Datum C.

8. Measured with the leads unconstrained.

9. Lead numbering per JEDEC SPP-012.

10. Exposed pad is nominally located at the center line of Datums A and B. “Max” dimensions noted include both size and positional tolerances.

0.023 [0.58]

0.018 [0.46]

0.010 [0.25] M C A B

BOTTOM VIEW

0.059 [1.50] Ref, typ.

3 4

11×

PI-5556a-100311

Rev. E 08/12

Page 37

Pin #1 I.D.

(Laser Marked)

0.460 [11.68]

0.400 [10.16]

0.004 [0.10] C A 2X

0.059 [1.50] Ref, Typ

0.059 [1.50]

eSOP-12B (K Package)

0.356 [9.04]

0.325 [8.26] Max.

7 12

Ref, Typ

0.004 [0.10] C B

0.350 [8.89]

Ref.

0.055 [1.40] Ref.

0.225 [5.72] Max.

0.010 [0.25]

TOP264-271

0 -

0.034 [0.85]

0.026 [0.65]

DETAIL A (Scale = 9X)

0.010 [0.25] Ref.

Gauge Plane

Seating Plane

0.008 [0.20] C

2X, 5/6 Lead Tips

0.098 [2.49]

0.086 [2.18]

0.006 [0.15]

0.000 [0.00] Seating plane to

package bottom standoff

0.028 [0.71]

0.067 [1.70]

3 4 6 6 1

0.023 [0.58]

0.018 [0.46]

11×

3 4

0.010 (0.25) M C A B

0.120 [3.05] Ref

0.070 [1.78]

TOP VIEW BOTTOM VIEW

0.032 [0.80]

0.029 [0.72]

0.092 [2.34]

0.086 [2.18]

Seating

0.004 [0.10] C

SIDE VIEW

Detail A

0.306 [7.77] Ref.

END VIEW

Plane

Land Pattern

0.217 [5.51]

Dimensions

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash,

tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007

0.321 [8.15]

[0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include interlead flash or protrusions.

5. Controlling dimensions in inches [mm].

6. Datums A and B to be determined at Datum H.

7. Exposed pad is nominally located at the centerline of

Datums A and B. “Max” dimensions noted include both size and positional tolerances.

0.429 [10.90]

0.028 [0.71] Ref.

0.016 [0.41]

0.011 [0.28] 11×

0.020 [0.51] Ref.

0.049 [1.23]

0.046 [1.16]

0.019 [0.48] Ref.

0.022 [0.56] Ref.

PI-5748a-100311

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Rev. E 08/12

Page 38

TOP264-271

Part Ordering Information

TOP 264 E G - TL

Rev. E 08/12

• TOPSwitch Product Family

• JX Series Number

• Package Identier

E Plastic eSIP-7C V Plastic eDIP-12

K Plastic eSOP-12

• Pin Finish

G Halogen Free and RoHS Compliant

• Tape & Reel and Other Options Blank Standard Conﬁgurations

www.powerint.com

Page 39

TOP264-271

Revision Notes Date

A Release data sheet. 01/10 B Added eDIP parts. 01/10 B Page 4 “latching” changed to “hysteretic”. Table 3 updated. 03/10 B Sentence in ‘Line-Sense Resistor Values’ section updated. 07/10 C Added K package parts. 11/10 D Updated K and V package drawings. 06/11 E Added eDIP-12B and eSOP-12B packages. Removed eDIP-12 and eSOP-12 packages. 10/11 E Updated Figure 2 and K package layout. 08/12

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Rev. E 08/12

Page 40