Datasheet TOP253PN, TOP256PN, TOP256YN, TOP252MN Specification

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TOP252-262 TOPSwitch-HX Family

Enhanced EcoSmart, Integrated Off-Line Switcher with Advanced Feature Set and Extended Power Range

Product Highlights

Lower System Cost, Higher Design Flexibility

• Multi-mode operation maximizes efﬁciency at all loads

• New eSIP-7F and eSIP-7C packages

• Low thermal impedance junction-to-case (2 °C per watt)

• Low height is ideal for adapters where space is limited

• Simple mounting using a clip to aid low cost manufacturing

• Horizontal eSIP-7F package ideal for ultra low height adapter

and monitor applications

• Extended package creepage distance from DRAIN pin to

adjacent pin and to heat sink

• No heat sink required up to 35 W using P, G and M packages

with universal input voltage and up to 48 W at 230 VAC

• Output overvoltage protection (OVP) is user programmable for

latching/non-latching shutdown with fast AC reset

• Allows both primary and secondary sensing

• Line undervoltage (UV) detection prevents turn-off glitches

• Line overvoltage (OV) shutdown extends line surge limit

• Accurate programmable current limit

• Optimized line feed-forward for line ripple rejection

• 132 kHz frequency (254Y-258Y and all E/L packages) reduces

transformer and power supply size

• Half frequency option for video applications

• Frequency jittering reduces EMI ﬁlter cost

TOPSwitch-HX

Figure 1. Typical Flyback Application.

• Heat sink is connected to SOURCE for low EMI

• Improved auto-restart delivers <3% of maximum power in

CONTROL

PI-4510-100206

OUT

short circuit and open loop fault conditions

• Accurate hysteretic thermal shutdown function automatically

recovers without requiring a reset

• Fully integrated soft-start for minimum start-up stress

• Extended creepage between DRAIN and all other pins

improves ﬁeld reliability

Output Power Table

Product

TOP252PN/GN

TOP252MN 21 W 13 W

TOP253PN/GN

TOP253MN 43 W 29 W

TOP254PN/GN

TOP254MN 62 W 40 W

TOP255PN/GN

TOP255MN 81 W 52 W

TOP256PN/GN

TOP256MN 98 W 64 W

TOP257PN/GN

TOP257MN 119 W 78 W

TOP258PN/GN

TOP258MN 140 W 92 W

Table 1. Output Power Table. (for notes see page 2).

230 VAC ±15%

Adapter

Frame

9 W 15 W

15 W 25 W

16 W 28 W

19 W 30 W

21 W 34 W

25 W 41 W

29 W 48 W

Open

Peak3Adapter

21 W

38 W

47 W

54 W

63 W

70 W

77 W

85-265 VAC

Open

Frame

6 W 10 W

9 W 15 W

11 W 20 W

13 W 22 W

15 W 26 W

19 W 30 W

22 W 35 W

Peak

13 W

25 W

30 W

35 W

40 W

45 W

50 W

Product

230 VAC ±15% 85-265 VAC

Open

Adapter

Frame

Adapter

TOP252EN/EG 10 W 21 W 6 W 13 W TOP253EN/EG 21 W 43 W 13 W 29 W TOP254EN/YN/EG 30 W 62 W 20 W 43 W TOP255EN/YN/EG 40 W 81 W 26 W 57 W TOP255LN 40 W 81 W 26 W 57 W

TOP256EN/YN/EG 60 W 119 W 40 W 86 W

TOP256LN 60 W 88 W 40 W 64 W TOP257EN/YN/EG 85 W 157 W 55 W 119 W TOP257LN 85 W 105 W 55 W 78 W TOP258EN/YN/EG 105 W 195 W 70 W 148 W TOP258LN 105 W 122 W 70 W 92 W

TOP259EN/YN/EG 128 W 238 W 80 W 171 W

TOP259LN 128 W 162 W 80 W 120 W TOP260EN/YN/EG 147 W 275 W 93 W 200 W TOP260LN 147 W 190 W 93 W 140 W TOP261EN/YN/EG 177 W 333 W 118 W 254 W TOP261LN 177 W 244 W 118 W 177 W TOP262EN TOP262LN

177 W 333 W 118 W 254 W 177 W 244 W 118 W 177 W

Open

Frame

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This Product is Covered by Patents and/or Pending Patent Applications.

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TOP252-262

EcoSmart™– Energy Efﬁcient

• Energy efﬁcient over entire load range

• No-load consumption

• Less than 200 mW at 230 VAC

• Standby power for 1 W input

• >600 mW output at 110 VAC input

• >500 mW output at 265 VAC input

Description

TOPSwitch™-HX cost effectively incorporates a 700 V power MOSFET, high voltage switched current source, PWM control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device.

Notes for Table 1:

1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient. Use of an external heat sink will increase power capability.

2. Minimum continuous power in an open frame design at +50 °C ambient.

3. Peak power capability in any design at +50 °C ambient.

4. 230 VAC or 110/115 VAC with doubler.

5. Packages: P: DIP-8C, G: SMD-8C, M: SDIP-10C, Y: TO-220-7C, E: eSIP-7C, L: eSIP-7F. See part ordering information.

6. TOP261 and TOP262 have the same current limit set point. In some applications TOP262 may run cooler than TOP261 due to a lower R

for the larger device.

DS(ON)

Y Package Option for TOP259-261

In order to improve noise-immunity on large TOPSwitch-HX Y package parts, the F pin has been removed (TOP259-261YN are ﬁxed at 66 kHz switching frequency) and replaced with a SIGNAL GROUND (G) pin. This pin acts as a low noise path for the C pin capacitor and the X pin resistor. It is only required for the TOP259-261YN package parts.

TOPSwitch-HX

Figure 2. Typical Flyback Application TOP259YN, TOP260YN and TOP261YN.

CONTROL

PI-4973-122607

OUT

Rev. J 08/16

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TOP252-262

Section List

Functional Block Diagram ....................................................................................................................................... 4

Pin Functional Description ...................................................................................................................................... 6

TOPSwitch-HX Family Functional Description ....................................................................................................... 7

CONTROL (C) Pin Operation .................................................................................................................................... 8

Oscillator and Switching Frequency .......................................................................................................................... 8

Pulse Width Modulator ............................................................................................................................................ 9

Maximum Load Cycle .............................................................................................................................................. 9

Error Ampliﬁer .......................................................................................................................................................... 9

On-Chip Current Limit with External Programmability ............................................................................................... 9

Line Undervoltage Detection (UV) ........................................................................................................................... 10

Line Overvoltage Shutdown (OV) ............................................................................................................................ 11

Hysteretic or Latching Output Overvoltage Protection (OVP)...................................................................................11

Line Feed-Forward with DC

Remote ON/OFF and Synchronization .................................................................................................................... 13

Soft-Start ............................................................................................................................................................... 13

Shutdown/Auto-Restart ......................................................................................................................................... 13

Hysteretic Over-Temperature Protection ................................................................................................................. 13

Bandgap Reference ............................................................................................................................................... 13

High-Voltage Bias Current Source .......................................................................................................................... 13

Typical Uses of FREQUENCY (F) Pin ...................................................................................................................... 15

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins .......................................... 16

Typical Uses of MULTI-FUNCTION (M) Pin ........................................................................................................... 18

Application Examples .............................................................................................................................................. 21

A High Efﬁciency, 35 W, Dual Output – Universal Input Power Supply ..................................................................... 21

A High Efﬁciency, 150 W, 250-380 VDC Input Power Supply .................................................................................. 22

A High Efﬁciency, 20 W Continuous – 80 W Peak, Universal Input Power Supply ................................................... 23

A High Efﬁciency, 65 W, Universal Input Power Supply ........................................................................................... 24

Key Application Considerations .............................................................................................................................. 25

TOPSwitch-HX vs.TOPSwitch-GX

TOPSwitch-HX Design Considerations .................................................................................................................. 26

TOPSwitch-HX Layout Considerations ................................................................................................................... 27

Quick Design Checklist .......................................................................................................................................... 31

Design Tools .......................................................................................................................................................... 31

Product Speciﬁcations and Test Conditions .......................................................................................................... 32

Typical Performance Characteristics .................................................................................................................... 39

Package Outlines .................................................................................................................................................... 43

Part Ordering Information ........................................................................................................................................ 47

Reduction .............................................................................................................. 13

MAX

.......................................................................................................................

. 25

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TOP252-262

SOURCE (S)

CONTROL (C)

MULTI-

FUNCTION (M)

SHUNT REGULATOR/

ERROR AMPLIFIER

CURRENT

LIMIT

ADJUST

LINE

SENSE

INTERNAL SUPPLY

DRAIN (D)

5.8 V

I (LIMIT)

ON/OFF

+ V

5.8 V

4.8 V

INTERNAL UV

COMPARATOR

STOP LOGIC

MAX

STOP

OSCILLATOR

WITH JITTER

OV/

OVPV

MAX

F REDUCTION

SOFT

START

SOFT START

MAX

CLOCK

÷ 16

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

SRQ

PS(UPPER)

PS(LOWER)

CURRENT LIMIT

COMPARATOR

SOURCE (S)

CONTROLLED

TURN-ON

GATE DRIVER

LEADING

EDGE

BLANKING

F REDUCTION

SOFT START I

PS(UPPER)

PS(LOWER)

PS(UPPER)

PS(LOWER)

PWM

OFF

Figure 3a. Functional Block Diagram (P and G Packages).

CONTROL (C)

EXTERNAL

CURRENT

LIMIT (X)

VOLTAGE

MONITOR (V)

SHUNT REGULATOR/

ERROR AMPLIFIER

CURRENT

LIMIT

ADJUST

1 V

LINE

SENSE

5.8 V

I (LIMIT)

ON/OFF

+ V

4.8 V

STOP LOGIC

OV/

OVPV

MAX

PS(UPPER)

PS(LOWER)

INTERNAL UV

COMPARATOR

STOP

OSCILLATOR

MAX

WITH JITTER

F REDUCTION

SOFT START I

PS(UPPER)

PS(LOWER)

PWM

SOFT

START

SOFT START

MAX

CLOCK

OFF

÷ 16

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

INTERNAL SUPPLY

SRQ

PS(UPPER)

PS(LOWER)

CURRENT LIMIT

COMPARATOR

CONTROLLED

TURN-ON

GATE DRIVER

PI-4508-120307

SOURCE (S)

LEADING

EDGE

BLANKING

DRAIN (D)

Figure 3b. Functional Block Diagram (M Package).

Rev. J 08/16

PI-4643-040507

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TOP252-262

SOURCE (S)

GROUND (G)

SOURCE (S)

CONTROL (C)

EXTERNAL CURRENT

LIMIT (X)

VOLTAGE

MONITOR (V)

FREQUENCY (F)

SHUNT REGULATOR/

ERROR AMPLIFIER

CURRENT

LIMIT

ADJUST

1 V

LINE

SENSE

+ V

OVPV

5.8 V

I (LIMIT)

ON/OFF

OV/

MAX

PS(UPPER)

PS(LOWER)

5.8 V

4.8 V

INTERNAL UV

COMPARATOR

STOP LOGIC

66k/132k

SOFT START I

PS(UPPER)

PS(LOWER)

MAX

F REDUCTION

SOFT

STOP

START

OSCILLATOR WITH JITTER

PWM

SOFT START

MAX

CLOCK

OFF

÷ 16

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

INTERNAL SUPPLY

SRQ

PS(UPPER)

PS(LOWER)

CURRENT LIMIT

COMPARATOR

CONTROLLED

TURN-ON

GATE DRIVER

SOURCE (S)

LEADING

EDGE

BLANKING

DRAIN (D)

Figure 3c. Functional Block Diagram (TOP254-258 YN Package and all eSIP Packages).

CONTROL (C)

EXTERNAL CURRENT

LIMIT (X)

VOLTAGE

MONITOR (V)

SHUNT REGULATOR/

ERROR AMPLIFIER

CURRENT

LIMIT

ADJUST

1 V

LINE

SENSE

5.8 V

I (LIMIT)

ON/OFF

+ V

4.8 V

INTERNAL UV

COMPARATOR

SOFT START

STOP LOGIC

SOFT

MAX

STOP

START

OSCILLATOR WITH JITTER

MAX

CLOCK

OV/

OVPV

MAX

F REDUCTION

SOFT START

PS(UPPER)

PS(LOWER)

PS(UPPER)

PS(LOWER)

PWM

OFF

÷ 16

SHUTDOWN/

AUTO-RESTART

HYSTERETIC

THERMAL

SHUTDOWN

INTERNAL SUPPLY

SRQ

PS(UPPER)

PS(LOWER)

CURRENT LIMIT

COMPARATOR

CONTROLLED

GATE DRIVER

SOURCE (S)

TURN-ON

LEADING

BLANKING

PI-4511-012810

DRAIN (D)

EDGE

Figure 3d. Functional Block Diagram TOP259YN, TOP260YN, TOP261YN.

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PI-4974-122607

SIGNAL

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TOP252-262

Pin Functional Description

DRAIN (D) Pin:

High-voltage power MOSFET DRAIN pin. The internal start-up bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for drain current.

CONTROL (C) Pin:

Error ampliﬁer and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor.

EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package):

Input pin for external current limit adjustment and remote ON/OFF. A connection to SOURCE pin disables all functions on this pin.

E Package (eSIP-7C)

Exposed Pad (Hidden) Internally Connected to SOURCE Pin

Y Package (TO-220-7C)

Note: Y package for TOP259-261

VOLTAGE MONITOR (V) Pin (Y & M package only):

Input for OV, UV, line feed forward with DC

reduction, output

MAX

overvoltage protection (OVP), remote ON/OFF and device reset. A connection to the SOURCE pin disables all functions on this pin.

MULTI-FUNCTION (M) Pin (P & G packages only):

This pin combines the functions of the VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) pins of the Y package into one pin. Input pin for OV, UV, line feed forward with DC

12 kΩ

VUV = IUV × R V

For R

4 MΩ

VUV = 102.8 VDC V

MAX

For RIL = 12 kΩ

See Figure 55b for

other resistor values (R I

LS + VV

= 4 MΩ

= 451 VDC

@100 VDC = 76% @375 VDC = 41%

= 61%

LIMIT

) to select different

values.

LIMIT

Input

Voltage

CONTROL

Figure 5. TOP254-258 Y and All M/E/L Package Line Sense and Externally Set

Current Limit.

MAX

(IV = IUV)

(IV = IOV)

PI-4711-021308

7D5S4F3C2X1

L Package (eSIP-7F)

Lead Bend Outward from Drawing (Refer to eSIP-7F Package

7D5S4F3C2X1

Outline Drawing)

M Package

P and G Package

Figure 4. Pin Conﬁguration (Top View).

Tab Internally Connected to SOURCE Pin

Y Package (TO-220-7C)

Note: Y package for TOP254-258

Tab Internally Connected to SOURCE Pin

7D5G4S3C2X1

7D5F4S3C2X1

PI-4644-091108

4 MΩ

X G

VUV = IUV × R V

= 4 MΩ

For R

VUV = 102.8 VDC

= 451 VDC

@100 VDC = 76%

MAX

@375 VDC = 41%

MAX

For RIL = 12 kΩ

LIMIT

See Figure 55b for other resistor values

) to select different

values.

LIMIT

Input

Voltage

Figure 6. TOP259-261 Y Package Line Sense and External Current Limit.

CONTROL

12 kΩ

LS + VV

= 61%

(IV = IUV)

(IV = IOV)

Input

Voltage

D M

Figure 7. P/G Package Line Sense.

CONTROL

4 MΩ

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

DC DC

451 VDC

@100 VDC = 76%

MAX

@375 VDC = 41%

MAX

LS + VM

PI-4712-120307

(IM = IUV) (IM = IOV)

PI-4983-021308

Rev. J 08/16

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Page 7

Input

Voltage

D M

Figure 8. P/G Package Externally Set Current Limit.

CONTROL

For R

= 12 kΩ

= 61%

LIMIT

For R

= 19 kΩ

= 37%

LIMIT

See Figure 55b for other resistor values (R select different I

) to

values.

LIMIT

PI-4713-021308

Auto-Restart

Duty Cycle (%) Drain Peak Current

100

TOP252-262

Slope = PWM Gain

(constant over load range)

CONTROL

Current

reduction, output overvoltage protection (OVP), external current limit adjustment, remote ON/OFF and device reset. A connection to SOURCE pin disables all functions on this pin and makes TOPSwitch-HX operate in simple three terminal mode (like TOPSwitch-II).

FREQUENCY (F) Pin (TOP254-258Y, and all E and L packages):

Input pin for selecting switching frequency 132 kHz if connected to SOURCE pin and 66 kHz if connected to CONTROL pin. The switching frequency is internally set for ﬁxed 66 kHz operation in the P, G, M package and TOP259YN, TOP260YN an d TO P261YN.

SIGNAL GROUND (G) Pin (TOP259YN, TOP260YN & TOP261YN only):

Return for C pin capacitor and X pin resistor.

SOURCE (S) Pin:

Output MOSFET source connection for high voltage power return. Primary side control circuit common and reference point.

TOPSwitch-HX Family Functional Description

Like TOPSwitch-GX, TOPSwitch-HX is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power MOSFET. During normal operation the duty cycle of the power MOSFET decreases linearly with increasing CONTROL pin current as shown in Figure 9.

In addition to the three terminal TOPSwitch features, such as the high voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, the TOPSwitch-HX incorporates many additional functions that reduce system cost, increase power supply performance and design ﬂexibility. A patented high voltage CMOS technology allows both the high-voltage power MOSFET and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip.

Three terminals, FREQUENCY, VOLTAGE-MONITOR, and EXTERNAL CURRENT LIMIT (available in Y and E/L packages),

To Current Limit Ratio (%)

CONTROL

Current

Full Frequency Mode

132

Variable

Frequency

Jitter

Frequency (kHz)

IB I

CD1

Figure 9. Control Pin Characteristics (Multi-Mode Operation).

C01

Mode

C02

C03

Low

Frequency

Mode

Multi-Cycle Modulation

CONTROL

COFF

Current

PI-4645-041107

two terminals, VOLTAGE-MONITOR and EXTERNAL CURRENT LIMIT (available in M package) or one terminal MULTI-FUNCTION (available in P and G package) have been used to implement some of the new functions. These terminals can be connected to the SOURCE pin to operate the TOPSwitch-HX in a TOPSwitch-like three terminal mode. However, even in this three terminal mode, the TOPSwitch-HX offers many transparent features that do not require any external components:

1. A fully integrated 17 ms soft-start signiﬁcantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during start-up.

2. A maximum duty cycle (DC

) of 78% allows smaller input

MAX

storage capacitor, lower input voltage requirement and/or higher power capability.

3. Multi-mode operation optimizes and improves the power supply efﬁciency over the entire load range while maintaining good cross regulation in multi-output supplies.

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TOP252-262

4. Switching frequency of 132 kHz reduces the transformer size with no noticeable impact on EMI.

5. Frequency jittering reduces EMI in the full frequency mode at high load condition.

6. Hysteretic over-temperature shutdown ensures automatic recovery from thermal fault. Large hysteresis prevents circuit board overheating.

7. Packages with omitted pins and lead forming provide large drain creepage distance.

8. Reduction of the auto-restart duty cycle and frequency to improve the protection of the power supply and load during open loop fault, short circuit, or loss of regulation.

9. Tighter tolerances on I2f power coefﬁcient, current limit reduction, PWM gain and thermal shutdown threshold.

The VOLTAGE-MONITOR (V) pin is usually used for line sensing by connecting a 4 MW resistor from this pin to the rectiﬁed DC high voltage bus to implement line overvoltage (OV), undervoltage (UV) and dual-slope line feed-forward with DC

MAX

reduction. In this mode, the value of the resistor determines the OV/UV thresholds and the DC

is reduced linearly with a dual

MAX

slope to improve line ripple rejection. In addition, it also provides another threshold to implement the latched and hysteretic output overvoltage protection (OVP). The pin can also be used as a remote ON/OFF using the I

threshold.

The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to SOURCE through a resistor. This pin can also be used as a remote ON/OFF input.

For the P and G package the VOLTAGE-MONITOR and EXTERNAL CURRENT LIMIT pin functions are combined on one MULTI-FUNCTION (M) pin. However, some of the functions become mutually exclusive.

The FREQUENCY (F) pin in the TOP254-258 Y and E/L packages set the switching frequency in the full frequency PWM mode to the default value of 132 kHz when connected to SOURCE pin. A half frequency option of 66 kHz can be chosen by connecting this pin to the CONTROL pin instead. Leaving this pin open is not recommended. In the P, G and M packages and the TOP259-261 Y packages, the frequency is set internally at 66 kHz in the full frequency PWM mode.

CONTROL (C) Pin Operation

The CONTROL pin is a low impedance node that is capable of receiving a combined supply and feedback current. During normal operation, a shunt regulator is used to separate the feedback signal from the supply current. CONTROL pin voltage V

is the supply voltage for the control circuitry including the

MOSFET gate driver. An external bypass capacitor closely connected between the CONTROL and SOURCE pins is required to supply the instantaneous gate drive current. The total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation. When rectiﬁed DC high voltage is applied to the DRAIN pin during start-up, the MOSFET is initially off, and the CONTROL pin capacitor is charged through a switched high voltage

current source connected internally between the DRAIN and CONTROL pins. When the CONTROL pin voltage V

reaches

approximately 5.8 V, the control circuitry is activated and the soft-start begins. The soft-start circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. If no external feedback/supply current is fed into the CONTROL pin by the end of the soft-start, the high voltage current source is turned off and the CONTROL pin will start discharging in response to the supply current drawn by the control circuitry. If the power supply is designed properly, and no fault condition such as open loop or shorted output exists, the feedback loop will close, providing external CONTROL pin current, before the CONTROL pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 V (internal supply undervoltage lockout threshold). When the externally fed current charges the CONTROL pin to the shunt regulator voltage of 5.8 V, current in excess of the consumption of the chip is shunted to SOURCE through an NMOS current mirror as shown in Figure 3. The output current of that NMOS current mirror controls the duty cycle of the power MOSFET to provide closed loop regulation. The shunt regulator has a ﬁnite low output impedance Z

that

sets the gain of the error ampliﬁer when used in a primary feedback conﬁguration. The dynamic impedance Z

of the

CONTROL pin together with the external CONTROL pin capacitance sets the dominant pole for the control loop.

When a fault condition such as an open loop or shorted output prevents the ﬂow of an external current into the CONTROL pin, the capacitor on the CONTROL pin discharges towards 4.8 V. At 4.8 V, auto-restart is activated, which turns the output MOSFET off and puts the control circuitry in a low current standby mode. The high-voltage current source turns on and charges the external capacitance again. A hysteretic internal supply undervoltage comparator keeps V

within a window of

typically 4.8 V to 5.8 V by turning the high-voltage current source on and off as shown in Figure 11. The auto-restart circuit has a divide-by-sixteen counter, which prevents the output MOSFET from turning on again until sixteen discharge/ charge cycles have elapsed. This is accomplished by enabling the output MOSFET only when the divide-by-sixteen counter reaches the full count (S15). The counter effectively limits TOPSwitch-HX power dissipation by reducing the auto-restart duty cycle to typically 2%. Auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop.

Oscillator and Switching Frequency

The internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a triangular waveform for the timing of the pulse width modulator. This oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle.

The nominal full switching frequency of 132 kHz was chosen to minimize transformer size while keeping the fundamental EMI frequency below 150 kHz. The FREQUENCY pin (available only in TOP254-258 Y and E, L packages), when shorted to the CONTROL pin, lowers the full switching frequency to 66 kHz

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TOP252-262

PI-4530-041107

Switching

Frequency

DRAIN

Figure 10. Switching Frequency Jitter (Idealized V

OSC

4 ms

Time

Waveforms).

DRAIN

(half frequency), which may be preferable in some cases such as noise sensitive video applications or a high efﬁciency standby mode. Otherwise, the FREQUENCY pin should be connected to the SOURCE pin for the default 132 kHz. In the M, P and G packages and the TOP259-261 Y package option, the full frequency PWM mode is set at 66 kHz, for higher efﬁciency and increased output power in all applications.

To further reduce the EMI level, the switching frequency in the full frequency PWM mode is jittered (frequency modulated) by approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for 132 kHz operation at a 250 Hz (typical) rate as shown in Figure 10. The jitter is turned off gradually as the system is entering the variable frequency mode with a ﬁxed peak drain current.

Pulse Width Modulator

The pulse width modulator implements multi-mode control by driving the output MOSFET with a duty cycle inversely proportional to the current into the CONTROL pin that is in excess of the internal supply current of the chip (see Figure 9). The feedback error signal, in the form of the excess current, is ﬁltered by an RC network with a typical corner frequency of 7 kHz to reduce the effect of switching noise in the chip supply current generated by the MOSFET gate driver.

To optimize power supply efﬁciency, four different control modes are implemented. At maximum load, the modulator operates in full frequency PWM mode; as load decreases, the modulator automatically transitions, ﬁrst to variable frequency PWM mode, then to low frequency PWM mode. At light load, the control operation switches from PWM control to multi-cyclemodulation control, and the modulator operates in multi-cyclemodulation mode. Although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess CONTROL pin current shown in Figure 9 is maintained through all three PWM modes. Please see the following sections for the details of the operation of each mode and the transitions between modes.

Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the CONTROL pin current (I reaches I kept constant at f

. In this mode, the average switching frequency is

(66 kHz for P, G and M packages and

OSC

)

TOP259-261 Y, pin selectable 132 kHz or 66 kHz for Y and E/L

packages). Duty cycle is reduced from DC reduction of the on-time when I

is increased beyond IB. This

through the

MAX

operation is identical to the PWM control of all other TOPSwitch families. TOPSwitch-HX only operates in this mode if the cycle-by-cycle peak drain current stays above k where k

is 55% (typical) and I

PS(UPPER)

(set) is the current limit

LIMIT

PS(UPPER)*ILIMIT

(set),

externally set via the X or M pin.

Variable Frequency PWM mode: When peak drain current is lowered to k

PS(UPPER)

* I

(set) as a result of power supply load

LIMIT

reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at k I

(set) while switching frequency drops from the initial full

LIMIT

frequency of f frequency of f

(132 kHz or 66 kHz) towards the minimum

OSC

(30 kHz typical). Duty cycle reduction is

MCM(MIN)

PS(UPPER)

accomplished by extending the off-time.

Low Frequency PWM mode: When switching frequency reaches f

(30 kHz typical), the PWM modulator starts to

MCM(MIN)

transition to low frequency mode. In this mode, switching frequency is held constant at f

and duty cycle is reduced,

MCM(MIN)

similar to the full frequency PWM mode, through the reduction of the on-time. Peak drain current decreases from the initial value of k k

PS(LOW ER)*ILIMIT

* I

PS(UPPER)

(set), where k

(set) towards the minimum value of

LIMIT

is 25% (typical) and I

PS(LOW ER)

LIMIT

(set) is

the current limit externally set via the X or M pin.

Multi-Cycle-Modulation mode: When peak drain current is lowered to k

PS(LOW ER)*ILIMIT

(set), the modulator transitions to multi-cycle-modulation mode. In this mode, at each turn-on, the modulator enables output switching for a period of T at the switching frequency of f at 30 kHz) with the peak drain current of k

(4 or 5 consecutive pulses

MCM(MIN)

PS(LOW ER)*ILIMIT

stays off until the CONTROL pin current falls below I

MCM(MIN)

(set), and

. This

C(OFF)

mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 kHz and 30 kHz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly suppressed.

Maximum Duty Cycle

The maximum duty cycle, DC

, is set at a default maximum

MAX

value of 78% (typical). However, by connecting the VOLTAGEMONITOR or MULTI-FUNCTION pin (depending on the package) to the rectiﬁed DC high voltage bus through a resistor with appropriate value (4 MW typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 V to 380 V, with dual gain slopes.

Error Ampliﬁer

The shunt regulator can also perform the function of an error ampliﬁer in primary side feedback applications. The shunt regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The CONTROL pin dynamic impedance Z CONTROL pin clamps external circuit signals to the V

sets the gain of the error ampliﬁer. The

voltage

level. The CONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current I

for the pulse width modulator.

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Rev. J 08/16

Page 10

TOP252-262

LINE

0 V

S14

S15

0 V

DRAIN

0 V

OUT

0 V

Note: S0 through S15 are the output states of the auto-restart counter

Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.

On-Chip Current Limit with External Programmability

The cycle-by-cycle peak drain current limit circuit uses the output MOSFET ON-resistance as a sense resistor. A current limit comparator compares the output MOSFET on-state drain to source voltage V current causes V

with a threshold voltage. High drain

DS(ON)

to exceed the threshold voltage and turns

DS(ON)

the output MOSFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in R The default current limit of TOPSwitch-HX is preset internally.

S13 S12 S0 S15 S13 S12 S0 S15S14

of the output MOSFET.

DS(ON)

on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectiﬁer reverse recovery time should not cause premature termination of the switching pulse.

The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOSFET. During startup and fault conditions the controller prevents excessive drain currents by reducing the switching frequency.

However, with a resistor connected between EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTIFUNCTION (M) pin (P and G package) and SOURCE pin (for TOP259-261 Y, the X pin is connected to the SIGNAL GROUND (G) pin), current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. By setting current limit low, a larger TOPSwitch-HX than necessary for the power required can be used to take advantage of the lower R

for higher efﬁciency/smaller heat sinking

DS(ON)

requirements. TOPSwitch-HX current limit reduction initial tolerance through the X pin (or M pin) has been improved signiﬁcantly compare with previous TOPSwitch-GX. With a second resistor connected between the EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M) pin (P and G package) and the rectiﬁed DC high voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an RCD clamp, this power limiting technique reduces maximum clamp voltage at high line. This allows for higher reﬂected voltage designs as well as reducing clamp dissipation.

Line Undervoltage Detection (UV)

At power up, UV keeps TOPSwitch-HX off until the input line voltage reaches the undervoltage threshold. At power down, UV prevents auto-restart attempts after the output goes out of regulation. This eliminates power down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. A single resistor connected from the VOLTAGE-MONITOR pin (Y, E/L and M packages) or MULTI-FUNCTION pin (P and G packages) to the rectiﬁed DC high voltage bus sets UV threshold during power up. Once the power supply is successfully turned on, the UV threshold is lowered to 44% of the initial UV threshold to allow extended input voltage operating range (UV low threshold). If the UV low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until UV (high threshold) has been reached again. If the power supply loses regulation before reaching the UV low threshold, the device will enter auto-restart. At the end of each auto-restart cycle (S15), the UV comparator is enabled. If the UV high threshold is not exceeded, the MOSFET will be disabled during the next cycle (see Figure 11). The UV feature

The leading edge blanking circuit inhibits the current limit

can be disabled independent of the OV feature.

comparator for a short time after the output MOSFET is turned

S14

S13

S12

S0 S15

S15

5.8 V

4.8 V

PI-4531-121206

Rev. J 08/16

www.power.com

Page 11

TOP252-262

Line Overvoltage Shutdown (OV)

The same resistor used for UV also sets an overvoltage threshold, which, once exceeded, will force TOPSwitch-HX to stop switching instantaneously (after completion of the current switching cycle). If this condition lasts for at least 100 ms, the TOPSwitch-HX output will be forced into off state. Unlike with TOPSwitch-GX, however, when the line voltage is back to

clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 10 mm of the V-pin to minimize the V-pin node area. The DC bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the V-pin as this may cause misoperation of the V pin related functions.

normal with a small amount of hysteresis provided on the OV threshold to prevent noise triggering, the state machine sets to S13 and forces TOPSwitch-HX to go through the entire autorestart sequence before attempting to switch again. The ratio of OV and UV thresholds is preset at 4.5, as can be seen in Figure 12. When the MOSFET is off, the rectiﬁed DC high voltage surge capability is increased to the voltage rating of the MOSFET (700 V), due to the absence of the reﬂected voltage and leakage spikes on the drain. The OV feature can be disabled independent of the UV feature.

Hysteretic or Latching Output Overvoltage Protection (OVP)

The detection of the hysteretic or latching output overvoltage protection (OVP) is through the trigger of the line overvoltage threshold. The V-pin or M-pin voltage will drop by 0.5 V, and the controller measures the external attached impedance immediately after this voltage drops. If I

or IM exceeds I

OV(LS)

(336 mA typical) longer than 100 ms, TOPSwitch-HX will latch into a permanent off state for the latching OVP. It only can be reset if V up-reset threshold (V

or VM goes below 1 V or VC goes below the power-

) and then back to normal.

C(RESET )

In order to reduce the no-load input power of TOPSwitch-HX designs, the V-pin (or M-pin for P Package) operates at very low currents. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V-pin should not be adjacent to any traces carrying switching currents. These include the drain,

or IM does not exceed I

100 ms, TOPSwitch-HX will initiate the line overvoltage and the hysteretic OVP. Their behavior will be identical to the line overvoltage shutdown (OV) that has been described in detail in the previous section.

or exceeds no longer than

OV(LS)

If I

Voltage Monitor and External Current Limit Pin Table*

Figure Number 16 17 18 19 20 21 22 23 24 25 26 27 28

Three Terminal Operation

Line Undervoltage

Line Overvoltage

Line Feed-Forward (DC

Output Overvoltage Protection

Overload Power Limiting

External Current Limit

Remote ON/OFF

Device Reset

*This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Conﬁgurations that are possible.

MAX

)

3 3 3 3 3 3

3 3 3 3 3

3 3

3 3 3 3 3

3 3 3

Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Conﬁguration Options.

Multi-Function Pin Table*

Figure Number 29 30 31 32 33 34 35 36 37 38 39 40

Three Terminal Operation

Line Undervoltage

Line Overvoltage

Line Feed-Forward (DC

Output Overvoltage Protection

Overload Power Limiting

External Current Limit

Remote ON/OFF

Device Reset

*This table is only a partial list of many MULTI-FUNCTIONAL Pin Conﬁgurations that are possible.

Table 3. MULTI-FUNCTION (M) Pin Conﬁguration Options.

MAX

)

3 3 3 3

3 3 3

3 3

3 3 3 3

3 3 3

www.power.com

Rev. J 08/16

Page 12

TOP252-262

M Pin

V Pin X Pin

Output

MOSFET

Switching

Current

Limit

Maximum

Duty Cycle

(Enabled)

(Disabled)

(Default)

LIMIT

(78%)

MAX

REM(N)

Disabled when supply output goes out of regulation

OV(LS)

(Non-Latching) (Latching)

Pin Voltage

-250 -200 -150 -100 -50 0 25 50 75 100 125 336

X and V Pins (Y, E, L and M Packages) and M Pin (P and G Packages) Current (µA)

Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of each functional pin operation refer to the Functional Description section of the data sheet.

Figure 12. MULTI-FUNCTION (P and G package). VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT (Y, E/L and M package) Pin Characteristics.

The circuit examples shown in Figures 41, 42 and 43 show a simple method for implementing the primary sensed overvoltage protection.

The primary sensed OVP protection circuit shown in Figures 41, 42 and 43 is triggered by a signiﬁcant rise in output voltage (and therefore bias winding voltage). If the power supply is operating under heavy load or low input line conditions when an open

During a fault condition resulting from loss of feedback, output voltage will rapidly rise above the nominal voltage. The increase in output voltage will also result in an increase in the voltage at the output of the bias winding. A voltage at the output of the bias winding that exceeds of the sum of the voltage rating of the Zener diode connected from the bias winding output to the V-pin (or M-pin) and V-pin (or M-pin) voltage, will cause a current in excess of I

or IM to be injected into the V-pin

(or M-pin), which will trigger the OVP feature.

loop occurs, the output voltage may not rise signiﬁcantly. Under these conditions, a latching shutdown will not occur until load or line conditions change. Nevertheless, the operation provides the desired protection by preventing signiﬁcant rise in the output voltage when the line or load conditions do change. Primary side OVP protection with the TOPSwitch-HX in a typical application will prevent a nominal 12 V output from rising above approximately 20 V under open loop conditions. If greater accuracy is required, a secondary sensed OVP circuit is recommended.

PI-4646-071708

Rev. J 08/16

www.power.com

Page 13

TOP252-262

Line Feed-Forward with DC

Reduction

MAX

The same resistor used for UV and OV also implements line voltage feed-forward, which minimizes output line ripple and reduces power supply output sensitivity to line transients. Note that for the same CONTROL pin current, higher line voltage results in smaller operating duty cycle. As an added feature, the maximum duty cycle DC

is also reduced from 78% (typical) at a voltage slightly

MAX

lower than the UV threshold to 36% (typical) at the OV threshold. DC

of 36% at high line was chosen to ensure that the power

MAX

capability of the TOPSwitch-HX is not restricted by this feature under normal operation. TOPSwitch-HX provides a better ﬁt to the ideal feed-forward by using two reduction slopes: -1% per mA for all bus voltage less than 195 V (typical for 4 MW line impedance) and

-0.25% per mA for all bus voltage more than 195 V. This dual slope line feed-forward improves the line ripple rejection signiﬁcantly compared with the TOPSwitch-GX.

Remote ON/OFF

TOPSwitch-HX can be turned on or off by controlling the current into the VOLTAGE-MONITOR pin or out from the EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) and into or out from the MULTI-FUNCTION pin (P and G package, see Figure 12). In addition, the VOLTAGE-MONITOR pin has a 1 V threshold comparator connected at its input. This voltage threshold can also be used to perform remote ON/OFF control.

When a signal is received at the VOLTAGE-MONITOR pin or the EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) or the MULTI-FUNCTION pin (P and G package) to disable the output through any of the pin functions such as OV, UV and remote ON/OFF, TOPSwitch-HX always completes its current switching cycle before the output is forced off.

As seen above, the remote ON/OFF feature can also be used as a standby or power switch to turn off the TOPSwitch-HX and keep it in a very low power consumption state for indeﬁnitely long periods. If the TOPSwitch-HX is held in remote off state for long enough time to allow the CONTROL pin to discharge to the internal supply undervoltage threshold of 4.8 V (approximately 32 ms for a 47

mF CONTROL pin capacitance), the CONTROL pin goes into the hysteretic mode of regulation. In this mode, the CONTROL pin goes through alternate charge and discharge cycles between 4.8 V and 5.8 V (see CONTROL pin operation section above) and runs entirely off the high voltage DC input, but with very low power consumption (160 mW typical at 230 VAC with M or X pins open). When the TOPSwitch-HX is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the CONTROL pin reaches 5.8 V. In the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the CONTROL pin, which is approximately 125 ms for a 47

mF CONTROL pin capacitor. This reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. It also allows for microprocessor controlled turn-on and turn-off sequences that may be required in certain applications such as inkjet and laser printers.

Soft-Start

The 17 ms soft-start sweeps the peak drain current and switching frequency linearly from minimum to maximum value by operating through the low frequency PWM mode and the variable frequency mode before entering the full frequency mode. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after being in hysteretic regulation of CONTROL pin voltage (V

), due

to remote OFF or thermal shutdown conditions. This effectively minimizes current and voltage stresses on the output MOSFET, the clamp circuit and the output rectiﬁer during start-up. This feature also helps minimize output overshoot and prevents saturation of the transformer during start-up.

Shutdown/Auto-Restart

To minimize TOPSwitch-HX power dissipation under fault conditions, the shutdown/auto-restart circuit turns the power supply on and off at an auto-restart duty cycle of typically 2% if an out of regulation condition persists. Loss of regulation interrupts the external current into the CONTROL pin. V

regulation changes from shunt mode to the hysteretic autorestart mode as described in CONTROL pin operation section. When the fault condition is removed, the power supply output becomes regulated, V

regulation returns to shunt mode, and

normal operation of the power supply resumes.

Hysteretic Over-Temperature Protection

Temperature protection is provided by a precision analog circuit that turns the output MOSFET off when the junction temperature exceeds the thermal shutdown temperature (142 °C typical). When the junction temperature cools to below the lower hysteretic temperature point, normal operation resumes, thus providing automatic recovery. A large hysteresis of 75 °C (typical) is provided to prevent overheating of the PC board due to a continuous fault condition. V

is regulated in hysteretic

mode, and a 4.8 V to 5.8 V (typical) triangular waveform is present on the CONTROL pin while in thermal shutdown.

Bandgap Reference

All critical TOPSwitch-HX internal voltages are derived from a temperature-compensated bandgap reference. This voltage reference is used to generate all other internal current references, which are trimmed to accurately set the switching frequency, MOSFET gate drive current, current limit, and the line OV/UV/OVP thresholds. TOPSwitch-HX has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances.

High-Voltage Bias Current Source

This high-voltage current source biases TOPSwitch-HX from the DRAIN pin and charges the CONTROL pin external capacitance during start-up or hysteretic operation. Hysteretic operation occurs during auto-restart, remote OFF and over-temperature shutdown. In this mode of operation, the current source is switched on and off, with an effective duty cycle of approximately 35%. This duty cycle is determined by the ratio of CONTROL pin charge (I

) and discharge currents (I

CD1

and I

CD2

). This current source is turned off during normal operation when the output MOSFET is switching. The effect of the current source switching will be seen on the DRAIN voltage waveform as small disturbances and is normal.

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Rev. J 08/16

Page 14

TOP252-262

CONTROL (C)

EXTERNAL CURRENT LIMIT (X)

Y, E/L and M Package

200 µA

VBG + V

TOPSwitch-HX

(Negative Current Sense - ON/OFF,

Current Limit Adjustment)

VOLTAGE MONITOR (V)

REF

400 µA

Figure 13a. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simpliﬁed Schematic.

P and G Package

CONTROL (C)

MULTI-FUNCTION (M)

200 µA

VBG + V

(Negative Current Sense - ON/OFF,

REF

TOPSwitch-HX

Current Limit Adjustment)

(Positive Current Sense - Undervoltage,

Overvoltage, Maximum Duty Cycle Reduction,

Output Overvoltage Protection)

(Voltage Sense)

1 V

(Positive Current Sense - Undervoltage,

Overvoltage, ON/OFF, Maximum Duty

Cycle Reduction, Output Over-

voltage Protection)

PI-4714-071408

Figure 13b. MULTI-FUNCTION (M) Pin Input Simpliﬁed Schematic.

Rev. J 08/16

400 µA

PI-4715-071408

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Page 15

Typical Uses of FREQUENCY (F) Pin

TOP252-262

Input

Voltage

CONTROL

PI-2654-071700

Figure 14. Full Frequency Operation (132 kHz). Figure 15. Half Frequency Operation (66 kHz).

Input

Voltage

CONTROL

PI-2655-071700

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Rev. J 08/16

Page 16

TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins

TOP254-258YTOP252-258M

D C X V

S SS S S

V X C S F D

Input

Voltage

CONTROL

X F

S C

C S D

PI-4716-020508

Figure 16a. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL

CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin) for TOP254-258 Y Packages.

eSIP E Package

V X C SF D

C S D

Input

Voltage

CONTROL

eSIP L Package

V X C SF D

C S D

Input

TOP259-261Y

V X C S G D

Voltage

CONTROL

X G

C S D

PI-4984-020708

Figure 16b. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL

CURRENT LIMIT Features Disabled for TOP259-261 Y Packages.

Input

Voltage

CONTROL

4 MΩR

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

DC DC

451 VDC

@100 VDC = 76%

MAX

@375 VDC = 41%

MAX

LS + VV

(IV = IUV)

(IV = IOV)

X F

PI-4956-071708

Figure 16c. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL

CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin) for TOP252-262 L and E Packages.

Reset

Input

Voltage

10 kΩ

D V

CONTROL

4 MΩ

VUV = IUV × R V

For R V

= 4 MΩ

= 102.8 VDC

451 VDC

LS + VV

Sense Output Voltage

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

(IV = IUV)

(IV = IOV)

PI-4756-121007

Figure 18. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Latched Output Overvoltage Protection.

PI-4717-120307

Figure 17. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.

VUV = IUV × R V

LS + VV

(IV = IUV)

(IV = IOV)

For RLS = 4 MΩ

= 102.8 VDC

Input

Voltage

4 MΩ

OVP

DC DC

451 VDC

Sense Output Voltage

OVP

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

D V

CONTROL

>3kΩ

OVP

PI-4719-120307

Figure 19. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Hysteretic Output Overvoltage Protection.

Rev. J 08/16

www.power.com

Page 17

TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)

Input

Voltage

6.2 V

D V

CONTROL

= RLS × I

4 MΩ

For Values Shown V

40 kΩ

UV + VV

= 103.8 VDC

PI-4720-120307

(IV = IUV)

Input

Voltage

4 MΩ

55 kΩ

CONTROL

= I

LS + VV

For Values Shown VOV = 457.2 VDC

1N4148

(IV = IOV)

PI-4721-120307

Figure 20. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 21. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum

Duty Cycle Reduced at Low Line and Further Reduction with Increasing Line Voltage.

Input

Voltage

Figure 22. External Set Current Limit.

CONTROL

For R

= 12 kΩ

= 61%

LIMIT

= 19 kΩ

For R

= 37%

LIMIT

See Figure 55b for other resistor values (R

TOP259-261YN would use the G pin as the return for R

PI-4722-021308

2.5 MΩR

Input

Voltage

Figure 23. Current Limit Reduction with Line Voltage.

CONTROL

R 6 kΩ

LIMIT

TOP259-261YN would use the G pin as the return for R

100% @ 100 VDC 53% @ 300 VDC

PI-4723-011008

Input

Voltage

Figure 24. Active-on (Fail Safe) Remote ON/OFF.

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CONTROL

47 KΩ

QR can be an optocoupler output or can be replaced by a manual switch.

TOP259-261YN would use the G pin as the return for Q

ON/OFF

PI-2625-011008

can be an optocoupler

output or can be replaced by a manual switch.

For R

Input

Voltage

CONTROL

For R

LIMIT

TOP259-261YN would

use the G pin as the return for Q

16 kΩ

ON/OFF

PI-4724-011008

Figure 25. Active-on Remote ON/OFF with Externally Set Current Limit.

12 kΩ

= 61%

19 kΩ

= 37%

Rev. J 08/16

Page 18

TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)

4 MΩ

VUV = IUV × R V

MAX

Q output or can be replaced

LS + VV

@100 VDC = 76% @375 VDC = 41%

can be an optocoupler

by a manual switch.

For R

16 kΩ

LIMIT

ON/OFF

PI-4725-011008

Input

Voltage

TOP259-261YN would use the G pin as the return for Q

CONTROL

Figure 26. Active-on Remote ON/OFF with Line-Sense and External

Current Limit.

Input

Voltage

10 kΩ

Reset

(IV = IUV) (IV = IoV)

12 kΩ

= 61%

D V

CONTROL

4 MΩ

VUV = IUV x R V

For RLS = 4 MΩ

Input

Voltage

TOP259-261YN would use the G pin as the return for R

CONTROL

12 kΩ

DC DC

Figure 27. Line Sensing and Externally Set Current Limit.

4 MΩ

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

451 VDC

LS + VV

(IV = IUV)

(IV = IOV)

Sense Output Voltage

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

(IV = IUV)

LS + VV

= 12 kΩ

= 61%

(IV = IoV)

= 102.8 VDC

= 451 VDC

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

For R

LIMIT

See Figure 55b for other resistor values

) to select different

values.

LIMIT

PI-4726-021308

Figure 28. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Latched Output Overvoltage Protection with Device Reset.

Typical Uses of MULTI-FUNCTION (M) Pin

S SS

Input

Voltage

CONTROL

D S

Figure 29. Three Terminal Operation (MULTI-FUNCTION Features Disabled).

PI-4727-061207

PI-4756-121007

Input

Voltage

D M

CONTROL

4 MΩ

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

DC DC

451 VDC

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

LS + VM

PI-4728-120307

(IM = IUV)

(IM = IOV)

Figure 30. Line Sensing for Undervoltage, Overvoltage and Line Feed-Forward.

Rev. J 08/16

www.power.com

Page 19

Typical Uses of MULTI-FUNCTION (M) Pin (cont.)

TOP252-262

Input

Voltage

D M

CONTROL

4 MΩ

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

451 VDC

Sense Output Voltage

@ 100 VDC = 76%

MAX

@ 375 VDC = 41%

MAX

(IM = IUV)

LS + VM

(IM = IOV)

LS + VM

PI-4729-120307

Figure 31. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Latched Output Overvoltage Protection.

Input

VUV = RLS × I

4 MΩ

For Values Shown V

40 kΩ

UV + VM

= 103.8 VDC

(IM = IUV)

Voltage

D M

6.2 V

CONTROL

VUV = IUV × R V

LS + VM

(IM = IUV)

(IM = IOV)

For RLS = 4 MΩ

= 102.8 VDC

Input

4 MΩ

OVP

451 VDC

Sense Output Voltage

OVP

Voltage

@ 100 VDC = 76%

D M

CONTROL

MAX

@ 375 VDC = 41%

>3kΩ

OVP

PI-4730-120307

Figure 32. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Hysteretic Output Overvoltage Protection.

Input

Voltage

4 MΩ

55 kΩ

D M

CONTROL

VOV = I

For Values Shown V

= 457.2 VDC

1N4148

LS + VM

(IM = IOV)

PI-4731-120307

Figure 33. Line Sensing for Undervoltage Only (Overvoltage Disabled).

Input

Voltage

D M

CONTROL

For R

= 12 kΩ

= 61%

LIMIT

For R

= 19 kΩ

= 37%

LIMIT

See Figures 55b for other resistor values (R select different I

) to

LIMIT

PI-4733-021308

values.

Figure 35. Externally Set Current Limit (Not Normally Required – See M Pin

Operation Description).

PI-4732-120307

Figure 34. Line Sensing for Overvoltage Only (Undervoltage Disabled). Maximum

Duty Cycle Reduced at Low Line and Further Reduction with Increasing Line Voltage.

RLS2.5 MΩ

100% @ 100 VDC

LIMIT

53% @ 300 VDC

LIMIT

Input

Voltage

D M

CONTROL

PI-4734-092107

6 kΩ

Figure 36. Current Limit Reduction with Line Voltage (Not Normally Required –

See M Pin Operation Description).

www.power.com

Rev. J 08/16

Page 20

TOP252-262

Typical Uses of MULTI-FUNCTION (M) Pin (cont.)

Input

Voltage

CONTROL

ON/OFF

47 kΩ

Figure 37. Active-on (Fail Safe) Remote ON/OFF.

Input

Voltage

ON/OFF

12 kΩ

7 kΩ

CONTROL

QR can be an optocoupler output or can be replaced by a manual switch.

PI-2519-040501

can be an optocoupler

output or can be replaced by a manual switch.

24 kΩ

can be an optocoupler

output or can be replaced by a manual switch.

For R

12 kΩ

Input

Voltage

CONTROL

ON/OFF

16 kΩ

Figure 38. Active-on Remote ON/OFF with Externally Set Current Limit

(see M Pin Operation Description).

4 MΩ

VUV = IUV × R V

= 4 MΩ

For R

= 102.8 VDC

Input

Reset

Voltage

10 kΩ

D M

CONTROL

DC DC

MAX

= 61%

LIMIT

For R

19 kΩ

= 37%

LIMIT

PI-4735-092107

LS + VM

451 VDC

Sense Output Voltage

@ 100 VDC = 76% @ 375 VDC = 41%

(IM = IUV)

(IM = IOV)

PI-4736-060607

Figure 39. Active-off Remote ON/OFF with Externally Set Current Limit

(see M Pin Operation Description).

PI-4757-120307

Figure 40. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and

Latched Output Overvoltage Protection with Device Reset.

Rev. J 08/16

www.power.com

Page 21

TOP252-262

Application Examples

A High Efﬁciency, 35 W, Dual Output - Universal Input Power Supply

The circuit in Figure 41 takes advantage of several of the TOPSwitch-HX features to reduce system cost and power supply size and to improve efﬁciency. This design delivers 35 W total continuous output power from a 90 VAC to 265 VAC input at an ambient of 50 ºC in an open frame conﬁguration. A nominal efﬁciency of 84% at full load is achieved using TOP258P. With a DIP-8 package, this design provides 35 W continuous output power using only the copper area on the circuit board underneath the part as a heat sink. The different operating modes of the TOPSwitch-HX provide signiﬁcant improvement in the no-load, standby, and light load performance of the power supply as compared to the previous generations of the TOPSwitch.

Resistors R3 and R4 provide line sensing, setting line UV at 100 VDC and line OV at 450 VDC.

Diode D5, together with resistors R6, R7, capacitor C6 and TVS VR1, forms a clamp network that limits the drain voltage of the TOPSwitch after the integrated MOSFET turns off. TVS VR1 provides a deﬁned maximum clamp voltage and typically only conducts during fault conditions such as overload. This allows the RCD clamp (R6, R7, C6 and D5) to be sized for normal operation, thereby maximizing efﬁciency at light load. Should the feedback circuit fail, the output of the power supply may exceed regulation limits. This increased voltage at output will also result in an increased voltage at the output of the bias

winding. Zener VR2 will break down and current will ﬂow into the “M” pin of the TOPSwitch initiating a hysteretic overvoltage protection with automatic restart attempts. Resistor R5 will limit the current into the M pin to < 336 mA, thus setting hysteretic OVP. If latching OVP is desired, the value of R5 can be reduced to 20 W.

The output voltage is controlled using the ampliﬁer TL431. Diode D9, capacitor C20 and resistor R16 form the soft ﬁnish circuit. At startup, capacitor C20 is discharged. As the output voltage starts rising, current ﬂows through the optocoupler diode inside U2A, resistor R13 and diode D9 to charge capacitor C20. This provides feedback to the circuit on the primary side. The current in the optocoupler diode U2A gradually decreases as the capacitor C20 becomes charged and the control ampliﬁer IC U3 becomes operational. This ensures that the output voltage increases gradually and settles to the ﬁnal value without any overshoot. Resistor R16 ensures that the capacitor C20 is maintained charged at all times after startup, which effectively isolates C20 from the feedback circuit after startup. Capacitor C20 discharges through R16 when the supply shuts down.

Resistors R20, R21 and R18 form a voltage divider network. The output of this divider network is primarily dependent on the divider circuit formed using R20 and R21 and will vary to some extent for changes in voltage at the 15 V output due to the connection of resistor R18 to the output of the divider network. Resistor R19 and Zener VR3 improve cross regulation in case only the 5 V output is loaded, which results in the 12 V output operating at the higher end of the speciﬁcation.

3.15 A

90 - 265

VAC

6.8 mH

1 MΩR21 MΩ

275 VAC

1N4937D21N4007

1N4937D41N4007

220 nF

RT1

10 Ω

3.9 nF 1 kV

22 kΩ

2 W

2.0 MΩ

100 µF

400 V

20 Ω

1/2 W

FR106

CONTROL

100 nF

50 V

P6KE200A

2.2 nF

250 VAC

EER28

VR1

VR2

1N5250B

20 V

5.1 kΩ

TOPSwitch-HX

TOP258PN

C16

470 pF

100 V

R10

4.7 Ω

FR106

PS2501-

6.8 Ω

47 µF

16 V

R11 33 Ω

U2B

1-H-A

SB560

SB530

C12

470 pF

100 V

C10

10 µF

50 V

33 Ω

R16

10 kΩ

C20

10 µF

50 V

R12

680 µF

C11

2.2 nF

250 VAC

C13

25 V

2200 µF

PS2501-

1N4148

C17

10 V

R13

330 Ω

U2A

1-H-A

TL431

C14

680 µF

25 V

10 kΩ

R17

3.3 µH

R14 22 Ω

C19

1.0 µF

50 V

R15

1 kΩ

C15

220 µF

25 V

VR3

BZX55B8V2

8.2 V 2%

196 kΩ

C21

220 nF

50 V

C18

220 µF

10 V

R18

R19

10 Ω

R20

12.4 kΩ

R21

10 kΩ

PI-4747-020508

+12 V,

2 A

RTN

+5 V,

2.2 A

RTN

Figure 41. 35 W Dual Output Power Supply using TOP258PN.

www.power.com

Rev. J 08/16

Page 22

TOP252-262

1N4148

C11

100 nF

50 V

+19 V,

7.7 A

RTN

RT1

5 Ω

R19

4.7 Ω

MBR20100CT

4.7 M

Ω

MBR20100CT

C15-C16

820 µF

25 V

C14

47 pF

1 kV

R20

1.5 kΩ

2 W

C10

47 µF 10 V

BYV26C

EI35

13,14

9,10

R15

4.75 kΩ

C20

1.0 µF

50 V

C17

47 pF

1 kV

10 µF

50 V

R23

15 kΩ

0.125 W

R14 22

Ω

0.5 W

8.06 kΩ

2.2 nF

250 VAC

R10

6.8 Ω

4.7 nF 1 kV

22 µF 400 V

R22

1.5 kΩ

2 W

1N4148

4.7

68 kΩ

2 W

4 A

C18

120 pF

1 kV

R16

31.6 kΩ

68 kΩ

2 W

VR2

1N5258B

36 V

R11

1 kΩ

0.125 W

C19

10 µF

50 V

R12

240 Ω

0.125 W

TOP258YN

R24

30 Ω

0.125 W

C5-C8

25 V

VR1, VR3

P6KE100A

R18

22 Ω

0.5 W

R21

2 W

1N4937

PC817A

TL431

C12

4.7 nF 50 V

R17

562 Ω

R13

56 kΩ

0.125 W

C13

100 nF

50 V

Ω

PC817B

3.3 µH

2.0 MΩ

2.0 ΜΩ

1.5 kΩ

TOPSwitch-HX

4.7 M

Ω

820 µF

250 - 380

VDC

PI-4795-092007

CONTROL

A High Efﬁciency, 150 W, 250 – 380 VDC Input Power Supply

The circuit shown in Figure 42 delivers 150 W (19 V @ 7.7 A) at 84% efﬁciency using a TOP258Y from a 250 VDC to 380 VDC input. A DC input is shown, as typically at this power level a power factor correction stage would precede this supply, providing the DC input. Capacitor C1 provides local decoupling, necessary when the supply is remote from the main PFC output capacitor.

The ﬂyback topology is still usable at this power level due to the high output voltage, keeping the secondary peak currents low enough so that the output diode and capacitors are reasonably sized. In this example, the TOP258YN is at the upper limit of its power capability.

Resistors R3, R6 and R7 provide output power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MW resistor from the V pin to the DC rail. Resistors R4 and R5 together form the 4 MW line sense resistor. If the DC input rail rises above 450 VDC, then TOPSwitch-HX will stop switching until the voltage returns to normal, preventing device damage.

Due to the high primary current, a low leakage inductance transformer is essential. Therefore, a sandwich winding with a copper foil secondary was used. Even with this technique, the leakage inductance energy is beyond the power capability of a simple Zener clamp. Therefore, R1, R2 and C3 are added in parallel to VR1 and VR3, two series TVS diodes being used to reduce dissipation. During normal operation, very little power is

dissipated by VR1 and VR3, the leakage energy instead being dissipated by R1 and R2. However, VR1 and VR3 are essential to limit the peak drain voltage during start-up and/or overload conditions to below the 700 V rating of the TOPSwitch-HX MOSFET. The schematic shows an additional turn-off snubber circuit consisting of R20, R21, R22, D5 and C18. This reduces turn-off losses in the TOPSwitch-HX.

The secondary is rectiﬁed and smoothed by D2, D3 and C5, C6, C7 and C8. Two windings are used and rectiﬁed with separate diodes D2 and D3 to limit diode dissipation. Four capacitors are used to ensure their maximum ripple current speciﬁcation is not exceeded. Inductor L1 and capacitors C15 and C16 provide switching noise ﬁltering.

Output voltage is controlled using a TL431 reference IC and R15, R16 and R17 to form a potential divider to sense the output voltage. Resistor R12 and R24 together limit the optocoupler LED current and set overall control loop DC gain. Control loop compensation is achieved using components C12, C13, C20 and R13. Diode D6, resistor R23 and capacitor C19 form a soft ﬁnish network. This feeds current into the control pin prior to output regulation, preventing output voltage overshoot and ensuring startup under low line, full load conditions.

Sufﬁcient heat sinking is required to keep the TOPSwitch-HX device below 110

°C when operating under full load, low line

and maximum ambient temperature. Airﬂow may also be required if a large heat sink area is not acceptable.

Figure 42. 150 W, 19 V Power Supply using TOP258YN.

Rev. J 08/16

www.power.com

Page 23

TOP252-262

1 nF

250 VAC

D6-D7

100 V

R17

1 k

Ω

0.5 W

VR7

BZY97C150

150 V

FR107

D13

1N4007

3.15 A

C30

100 nF

400 V

2N3904

R23

1 M

Ω

220 nF

275 VAC

90 - 264 VAC

R24

1 M

Ω

5.3 mH

68 k

Ω

D10

1N4007

120

400 V

R11

3.6 M

Ω

1N4007

RT1 10

Ω

2 M

Ω

R14

3.6 M

Ω

1N4007

2N3904

R18

39 k

Ω

2N3904

2 M

Ω

2 M

Ω

R15

1 k

Ω

R21

1 M

Ω

0.125 W

2 M

Ω

R26

R22

2 M

Ω

100 nF

50 V

TOP258MN

16 V

VR5

1N5250B

20 V

R25

C5 10 nF

1 kV

6.8

Ω

C10 1 nF

250 VAC

EF25

R20

130 k

Ω

LL4148

C13

50 V

U2A

PC817D

2 k

Ω

1.5 k

Ω

R10 56

Ω

VR3

1N5255B

28 V

C28

330 nF

50 V

R19 68

Ω

0.5 W

STPS3150

C26

100 pF

1 kV

3.3

C31

50 V

C20

330

50 V

R12

7.5 k

Ω

D11

1N4007

100

Ω

CONTROL

C29

220 nF

50 V

32 V

625 mA, 2.5 A

RTN

PI-4833-092007

TOPSwitch-HX

A High Efﬁciency, 20 W continuous – 80 W Peak, Universal Input Power Supply

The circuit shown in Figure 43 takes advantage of several of TOPSwitch-HX features to reduce system cost and power supply size and to improve power supply efﬁciency while delivering signiﬁcant peak power for a short duration. This design delivers continuous 20 W and peak 80 W at 32 V from an 90 VAC to 264 VAC input. A nominal efﬁciency of 82% at full load is achieved using TOP258MN. The M-package part has an optimized current limit to enable design of power supplies capable of delivering high power for a short duration.

Resistor R12 sets the current limit of the part. Resistors R11 and R14 provide line feed forward information that reduces the current limit with increasing DC bus voltage, thereby maintaining a constant overload power level with increasing line voltage. Resistors R1 and R2 implement the line undervoltage and overvoltage function and also provide feed forward compensation for reducing line frequency ripple at the output. The overvoltage feature inhibits TOPSwitch-HX switching during a line surge extending the high voltage withstand to 700 V without device damage.

The snubber circuit comprising of VR7, R17, R25, C5 and D2 limits the maximum drain voltage and dissipates energy stored in the leakage inductance of transformer T1. This clamp conﬁguration maximizes energy efﬁciency by preventing C5 from discharging below the value of VR7 during the lower frequency operating modes of TOPSwitch-HX. Resistor R25 damps high frequency ringing for reduced EMI.

A combined output overvoltage and over power protection circuit is provided via the latching shutdown feature of

TOPSwitch-HX and R20, C9, R22 and VR5. Should the bias winding output voltage across C13 rise due to output overload or an open loop fault (opto coupler failure), then VR5 conducts triggering the latching shutdown. To prevent false triggering due to short duration overload, a delay is provided by R20, R22 and C9.

To reset the supply following a latching shutdown, the V pin must fall below the reset threshold. To prevent the long reset delay associated with the input capacitor discharging, a fast AC reset circuit is used. The AC input is rectiﬁed and ﬁltered by D13 and C30. While the AC supply is present, Q3 is on and Q1 is off, allowing normal device operation. However when AC is removed, Q1 pulls down the V pin and resets the latch. The supply will then return to normal operation when AC is again applied.

Transistor Q2 provides an additional lower UV threshold to the level programmed via R1, R2 and the V pin. At low input AC voltage, Q2 turns off, allowing the X pin to ﬂoat and thereby disabling switching.

A simple feedback circuit automatically regulates the output voltage. Zener VR3 sets the output voltage together with the voltage drop across series resistor R8, which sets the DC gain of the circuit. Resistors R10 and C28 provide a phase boost to improve loop bandwidth.

Diodes D6 and D7 are low-loss Schottky rectiﬁers, and capacitor C20 is the output ﬁlter capacitor. Inductor L3 is a common mode choke to limit radiated EMI when long output cables are used and the output return is connected to safety earth ground. Example applications where this occurs include PC peripherals, such as inkjet printers.

Figure 43. 20 W Continuous, 80 W Peak, Universal Input Power Supply using TOP258MN.

www.power.com

Rev. J 08/16

Page 24

TOP252-262

PI-4998-021408

A High Efﬁciency, 65 W, Universal Input Power Supply

The circuit shown in Figure 44 delivers 65 W (19 V @ 3.42 A) at 88% efﬁciency using a TOP260EN operating over an input voltage range of 90 VAC to 265 VAC.

Capacitors C1 and C6 and inductors L1 and L2 provide common mode and differential mode EMI ﬁltering. Capacitor C2 is the bulk ﬁlter capacitor that ensures low ripple DC input to the ﬂyback converter stage. Capacitor C4 provides decoupling for switching currents reducing differential mode EMI.

In this example, the TOP260EN is used at reduced current limit to improve efﬁciency.

Resistors R5, R6 and R7 provide power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MW impedance from the V pin to the DC rail. Resistors R3 and R4 together form the 4 MW line sense resistor. If the DC input rail rises above 450 VDC, then TOPSwitch-HX will stop switching until the voltage returns to normal, preventing device damage.

This circuit features a high efﬁciency clamp network consisting of diode D1, zener VR1, capacitor C5 together with resistors R8 and R9. The snubber clamp is used to dissipate the energy of the leakage reactance of the transformer. At light load levels, very little power is dissipated by VR1 improving efﬁciency as compared to a conventional RCD clamp network.

The secondary output from the transformer is rectiﬁed by diode D2 and ﬁltered by capacitors C13 and C14. Ferrite Bead L3 and capacitors C15 form a second stage ﬁlter and effectively reduce the switching noise to the output.

Output voltage is controlled using a LM431 reference IC. Resistor R19 and R20 form a potential divider to sense the output voltage. Resistor R16 limits the optocoupler LED current and sets the overall control loop DC gain. Control loop compensation is achieved using C18 and R21. The components connected to the control pin on the primary side C8, C9 and R15 set the low frequency pole and zero to further shape the control loop response. Capacitor C17 provides a soft ﬁnish during startup. Optocoupler U2 is used for isolation of the feedback signal.

Diode D4 and capacitor C10 form the bias winding rectiﬁer and ﬁlter. Should the feedback loop break due to a defective component, a rising bias winding voltage will cause the Zener VR2 to break down and trigger the over voltage protection which will inhibit switching.

An optional secondary side over voltage protection feature which offers higher precision (as compared to sensing via the bias winding) is implemented using VR3, R18 and U3. Excess voltage at the output will cause current to ﬂow through the optocoupler U3 LED which in turn will inject current in the V-pin through resistor R13, thereby triggering the over voltage protection feature.

3KBP08M

BR1

2.0 MΩR55.1 MΩ

90 - 265

VAC

12 mH

2.2 MΩR22.2 MΩ

4 A

330 nF

275 VAC

Ferrite Bead

470 pF

250 VAC

120 µF

400 V

2.0 MΩ

15 kΩ

Figure 44. 65 W, 19 V Power Supply Using TOP260EN.

6.8 MΩ

100 nF

400 V

2.2 nF 1 kV

BZY97C180

100 Ω

DL4937

CONTROL

VR1

180 V

1 kΩ

BAV19WS

TOPSwitch-HX

TOP260EN

100 nF

50 V

2.2 nF

250 VAC

RM10

FL1

FL2

D4 BAV19WS

100 nF

25 V

R13

5.1 Ω

R14

100 Ω

R15

6.8 Ω

47 µF

16 V

22 µF

50 V

R12

5.1 kΩ

C10

C12 1 nF

100 V

MBR20100CT

R10

73.2 kΩ

U3B

PC357A

U2B

LTY817C

C16 1 µF 50 V

R16

33 Ω

VR2

1N5248B

18 V

R11

2 MΩ

33 µF

C17

35 V

C13

470 µF

25 V

U2A

LTY817C

C14

470 µF

25 V

C11

100 nF

50 V

R16

680 Ω

1N4148

LM431

C15

Ferrite

47 µF

Bead

25 V

R19

68.1 kΩ

C18

100 nF

R21

1 kΩ

R20

10 kΩ

VR3

BZX79-C22

22 V

R18

47 Ω

U3A

PC357A

19 V, 3.42 A

RTN

Rev. J 08/16

www.power.com

Page 25

TOP252-262

Key Application Considerations

TOPSwitch-HX vs. TOPSwitch-GX

features eliminate the need for additional discrete components. Table 4 compares the features and performance differences between TOPSwitch-HX and TOPSwitch-GX. Many of the new

TOPSwitch-HX vs. TOPSwitch-GX

Function TOPSwitch-GX TOPSwitch-HX TOPSwitch-HX Advantages

Other features increase the robustness of design, allowing cost

savings in the transformer and other power components.

EcoSmart Linear frequency reduction to

30 kHz (@ 132 kHz) for duty cycles < 10%

Multi-mode operation with linear frequency reduction to 30 kHz (@ 132 kHz) and multi-cycle modulation (virtually no audible noise)

Output Overvoltage Protection (OVP)

Not available User programmable primary

or secondary hysteretic or latching OVP

Line Feed-Forward with Duty Cycle Reduction

Linear reduction Dual slope reduction with

lower, more accurate onset point

Switching Frequency DIP-8

132 kHz 66 kHz

Package

Lowest MOSFET On

3.0 W (TOP246P) 1.8 W (TOP258P)

Resistance in DIP-8 Package

f Trimming Not available -10% / +20%

Auto-restart Duty Cycle 5.6% 2%

• Improved efﬁciency over load (e.g. at 25% load

point)

• Improved standby efﬁciency

• Improved no-load consumption

• Protects power supply output during open loop fault

• Maximum design ﬂexibility

• Improved line ripple rejection

• Smaller DC bus capacitor

• Increased output power for given MOSFET size due

to higher efﬁciency

• Increased output power in designs without external

heat sink

• Increased output power for given core size

• Reduced over-load power

• Reduced delivered average output power during

open loop faults

Frequency Jitter ±4 kHz @ 132 kHz

±2 kHz @ 66 kHz

±5 kHz @ 132 kHz ±2.5 kHz @ 66 kHz

Thermal Shutdown 130 °C to 150 °C 135 °C to 150 °C

External Current Limit 30%-100% of I

LIMIT

Line UV Detection Threshold 50 mA (2 MW sense

impedance)

Soft-Start 10 ms duty cycle and current

limit ramp

Table 4. Comparison Between TOPSwitch-GX and TOPSwitch-HX.

www.power.com

30%-100% of I trim at 0.7 × I

25 mA (4 MW sense impedance)

17 ms sweep through multi-mode characteristic

LIMIT

, additional

• Reduced EMI ﬁlter cost

• Increased design margin

• Reduced tolerances when current limit is set

externally

• Reduced dissipation for lower no-load consumption

• Reduced peak current and voltage component

stress at startup

• Smooth output voltage rise

Rev. J 08/16

Page 26

TOP252-262

TOPSwitch-HX Design Considerations

Power Table

The data sheet power table (Table 1) represents the maximum practical continuous output power based on the following conditions:

1. 12 V output.

2. Schottky or high efﬁciency output diode.

3. 135 V reﬂected voltage (VOR) and efﬁciency estimates.

4. A 100 VDC minimum for 85-265 VAC and 250 VDC mini-

mum for 230 VAC.

5. Sufﬁcient heat sinking to keep device temperature ≤100 °C.

6. Power levels shown in the power table for the M/P package

device assume 6.45 cm in an enclosed adapter, or 19.4 cm

of 610 g/m2 copper heat sink area

in an open frame.

The provided peak power depends on the current limit for the respective device.

TOPSwitch-HX Selection

Selecting the optimum TOPSwitch-HX depends upon required maximum output power, efﬁciency, heat sinking constraints, system requirements and cost goals. With the option to externally reduce current limit, an Y, E/L or M package TOPSwitch-HX may be used for lower power applications where higher efﬁciency is needed or minimal heat sinking is available.

Input Capacitor

The input capacitor must be chosen to provide the minimum DC voltage required for the TOPSwitch-HX converter to maintain regulation at the lowest speciﬁed input voltage and maximum output power. Since TOPSwitch-HX has a high DC

limit and an optimized dual slope line feed forward for

MAX

ripple rejection, it is possible to use a smaller input capacitor. For TOPSwitch-HX, a capacitance of 2 mF per watt is possible for universal input with an appropriately designed transformer.

Primary Clamp and Output Reﬂected Voltage V

A primary clamp is necessary to limit the peak TOPSwitch-HX drain to source voltage. A Zener clamp requires few parts and takes up little board space. For good efﬁciency, the clamp Zener should be selected to be at least 1.5 times the output reﬂected voltage V

, as this keeps the leakage spike conduction

time short. When using a Zener clamp in a universal input application, a V

of less than 135 V is recommended to allow

for the absolute tolerances and temperature variations of the Zener. This will ensure efﬁcient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the TOPSwitch-HX MOSFET. A high V is required to take full advantage of the wider DC

MAX

TOPSwitch-HX. An RCD clamp provides tighter clamp voltage tolerance than a Zener clamp and allows a VOR as high as 150 V. RCD clamp dissipation can be minimized by reducing the external current limit as a function of input line voltage (see Figures 23 and 36). The RCD clamp is more cost effective than the Zener clamp but requires more careful design (see Quick Design Checklist).

Output Diode

The output diode is selected for peak inverse voltage, output current, and thermal conditions in the application (including heat

sinking, air circulation, etc.). The higher DC

of TOPSwitch-HX,

MAX

along with an appropriate transformer turns ratio, can allow the

use of a 80 V Schottky diode for higher efﬁciency on output

voltages as high as 15 V (see Figure 41).

Bias Winding Capacitor

Due to the low frequency operation at no-load, a 10 mF bias

winding capacitor is recommended.

Soft-Start

Generally, a power supply experiences maximum stress at

start-up before the feedback loop achieves regulation. For a

period of 17 ms, the on-chip soft-start linearly increases the

drain peak current and switching frequency from their low

starting values to their respective maximum values. This

causes the output voltage to rise in an orderly manner, allowing

time for the feedback loop to take control of the duty cycle.

This reduces the stress on the TOPSwitch-HX MOSFET, clamp

circuit and output diode(s), and helps prevent transformer

saturation during start-up. Also, soft-start limits the amount of

output voltage overshoot and, in many applications, eliminates

the need for a soft-ﬁnish capacitor.

EMI

The frequency jitter feature modulates the switching frequency

over a narrow band as a means to reduce conducted EMI peaks

associated with the harmonics of the fundamental switching

frequency. This is particularly beneﬁcial for average detection

mode. As can be seen in Figure 45, the beneﬁts of jitter increase

with the order of the switching harmonic due to an increase in

frequency deviation. Devices in the P, G or M package and

TOP259-261YN operate at a nominal switching frequency of

66 kHz. The FREQUENCY pin of devices in the TOP254-258 Y

and E packages offer a switching frequency option of 132 kHz or

66 kHz. In applications that require heavy snubber on the drain

node for reducing high frequency radiated noise (for example,

video noise sensitive applications such as VCRs, DVDs, monitors,

TVs, etc.), operating at 66 kHz will reduce snubber loss, resulting

in better efﬁciency. Also, in applications where transformer size is

not a concern, use of the 66 kHz option will provide lower EMI

and higher efﬁciency. Note that the second harmonic of 66 kHz

is still below 150 kHz, above which the conducted EMI

speciﬁcations get much tighter. For 10 W or below, it is possible

to use a simple inductor in place of a more costly AC input

common mode choke to meet worldwide conducted EMI limits.

Transformer Design

It is recommended that the transformer be designed for

maximum operating ﬂux density of 3000 Gauss and a peak ﬂux

density of 4200 Gauss at maximum current limit. The turns

ratio should be chosen for a reﬂected voltage (V

) no greater

than 135 V when using a Zener clamp or 150 V (max) when

using an RCD clamp with current limit reduction with line

voltage (overload protection). For designs where operating

current is signiﬁcantly lower than the default current limit, it is

recommended to use an externally set current limit close to the

operating peak current to reduce peak ﬂux density and peak

power (see Figures 22 and 35). In most applications, the tighter

current limit tolerance, higher switching frequency and soft-start

features of TOPSwitch-HX contribute to a smaller transformer

when compared to TOPSwitch-GX.

Rev. J 08/16

www.power.com

Page 27

TOP252-262

-10

Amplitude (dBµV)

-10

-20

0.15 1 10 30

EN55022B (QP) EN55022B (AV)

Frequency (MHz)

Figure 45a. Fixed Frequency Operation Without Jitter.

-10

Amplitude (dBµV)

-10

-20

0.15 1 10 30

TOPSwitch-HX (with jitter)

EN55022B (QP) EN55022B (AV)

Frequency (MHz)

Figure 45b. TOPSwitch-HX Full Range EMI Scan (132 kHz With Jitter) With

Identical Circuitry and Conditions.

Standby Consumption

Frequency reduction can signiﬁcantly reduce power loss at light or no load, especially when a Zener clamp is used. For very low secondary power consumption, use a TL431 regulator for feedback control. A typical TOPSwitch-HX circuit automatically enters MCM mode at no load and the low frequency mode at light load, which results in extremely low losses under no-load or standby conditions.

High Power Designs

The TOPSwitch-HX family contains parts that can deliver up to 333 W. High power designs need special considerations. Guidance for high power designs can be found in the Design Guide for TOPSwitch-HX (AN-43).

TOPSwitch-HX Layout Considerations

The TOPSwitch-HX has multiple pins and may operate at high power levels. The following guidelines should be carefully followed.

Primary Side Connections

Use a single point (Kelvin) connection at the negative terminal of

the input ﬁlter capacitor for the TOPSwitch-HX SOURCE pin

PI-2576-010600

and bias winding return. This improves surge capabilities by

returning surge currents from the bias winding directly to the

input ﬁlter capacitor. The CONTROL pin bypass capacitor

should be located as close as possible to the SOURCE and

CONTROL pins, and its SOURCE connection trace should not

be shared by the main MOSFET switching currents. All

SOURCE pin referenced components connected to the

MULTI-FUNCTION (M-pin), VOLTAGE MONITOR (V-pin) or

EXTERNAL CURRENT LIMIT (X-pin) pins should also be located

closely between their respective pin and SOURCE. Once again,

the SOURCE connection trace of these components should not

be shared by the main MOSFET switching currents. It is very

critical that SOURCE pin switching currents are returned to the

input capacitor negative terminal through a separate trace that

is not shared by the components connected to CONTROL,

MULTI-FUNCTION, VOLTAGE MONITOR or EXTERNAL

CURRENT LIMIT pins. This is because the SOURCE pin is also

the controller ground reference pin. Any traces to the M, V, X or

C pins should be kept as short as possible and away from the

DRAIN trace to prevent noise coupling. VOLTAGE MONITOR

PI-2577-010600

resistors (R1 and R2 in Figures 46, 47, 48, R3 and R4 in

Figure 49, and R14 in Figure 50) should be located close to the

M or V pin to minimize the trace length on the M or V pin side.

Resistors connected to the M, V or X pin should be connected

as close to the bulk cap positive terminal as possible while

routing these connections away from the power switching

circuitry. In addition to the 47 μF CONTROL pin capacitor, a

high frequency bypass capacitor in parallel may be used for

better noise immunity. The feedback optocoupler output

should also be located close to the CONTROL and SOURCE

pins of TOPSwitch-HX and away from the drain and clamp

component traces.

Y Capacitor

The Y capacitor should be connected close to the secondary

output return pin(s) and the positive primary DC input pin of the

transformer.

Heat Sinking

The tab of the Y package (TO-220C) and E package (eSIP-7C)

and L package (eSIP-7F) are internally electrically tied to the

SOURCE pin. To avoid circulating currents, a heat sink

attached to the tab should not be electrically tied to any primary

ground/source nodes on the PC board. When using a P (DIP-8),

G (SMD-8) or M (DIP-10) package, a copper area underneath

the package connected to the SOURCE pins will act as an

effective heat sink. On double sided boards, topside and bottom

side areas connected with vias can be used to increase the

effective heat sinking area. In addition, sufﬁcient copper area

should be provided at the anode and cathode leads of the

output diode(s) for heat sinking. In Figures 46 to 50 a narrow

trace is shown between the output rectiﬁer and output ﬁlter

capacitor. This trace acts as a thermal relief between the rectiﬁer

and ﬁlter capacitor to prevent excessive heating of the capacitor.

www.power.com

Rev. J 08/16

Page 28

TOP252-262

Isolation Barrier

Optional PCB slot for external

heatsink in contact with

SOURCE pins

Input Filter

Capacitor

Optional slot for

insertion of heat sink

JP1

R1 R2

Simplied PCB layout

VR1

improves heat sinking

Electrically quiet

copper area

Maximize hatched copper areas ( ) for optimum heat sinking

Figure 46. Layout Considerations for TOPSwitch-HX Using P Package.

VR2

>3.5 mm

JP2

Y1-

Capacitor

Transformer

R13

R14

R12

C10

R11

R10

Output Filter

Capacitor

Out

Output

Rectier

PI-4753-090407

Optional PCB slot for external

heatsink in contact with

SOURCE pins

VR1

S S

S S S

VR2

Input Filter

Capacitor

JP1

Maximize hatched copper areas ( ) for optimum heat sinking

Figure 47. Layout Considerations for TOPSwitch-HX Using M Package.

Isolation Barrier

Y1-

Capacitor

R12

Output

Rectier

Out

Output Filter

Capacitor

PI-4752-070307

Transformer

C X

R10

R11

JP2

R15

R16

R17

R13

R14

Rev. J 08/16

www.power.com

Page 29

Input Filter

Capacitor

JP1

HS1

R1 R2

R3 R4

VR1

TOP252-262

Isolation Barrier

R10

VR2

R11

Y1-

Capacitor

Transformer

C5 C9

JP2

R16

R12

R15

R17

R12

C10

R14

Output

Rectier

Output Filter

Capacitor

R13

Figure 48. Layout Considerations for TOPSwitch-HX Using TOP254-258 Y Package.

Input Filter

Capacitor

JP1

HS1

R11

VR1

R14

VR2

G C

R22

Isolation Barrier

R10

JP2

Y1-

Capacitor

Transformer

C10

R15

C21

R17

R13

C16

R21

R12

C18

DC Out

C17

R20

PI-4751-070307

Output Filter

Capacitor

Figure 49. Layout Considerations for TOPSwitch-HX Using TOP259-261 Y Package.

www.power.com

Out

PI-4977-021408

Rev. J 08/16

Page 30

Input Filter

TOP252-262

Capacitor

R11

Isolation Barrier

Y1-

JP2

Capacitor

Transformer

R15

R17

R13

C21

C16

R21

C17

C18

R20

R12

C19

Output

H52

Rectier

Output Filter

Capacitor

HS1

F X

R22

R14

VR2

VR1

C10

R10

Figure 50a. Layout Considerations for TOPSwitch-HX Using E Package and Operating at 66 kHz.

Isolation Barrier

Input Filter

Capacitor

R11

HS1

R14

VR2

VR1

R22

Transformer

C10

R10

JP2

Y1-

Capacitor

R15

R17

R13

C21

R21

Out

C16 R12

C17

C18

R20

C19

PI-4975-022108

H52

Output Filter

Capacitor

Output

Rectier

Figure 50b. Layout Considerations for TOPSwitch-HX Using E Package and Operating at 132 kHz.

Rev. J 08/16

Out

PI-4976-091608

www.power.com

Page 31

Input Filter

Capacitor

HS1

R22

JP1

R11

R3R4R5

Note: Components U1, R8, C8, C9 and R22 are under heat sink HS1.

R14

F D

VR1

VR2

C10

R10

JP2

Isolation Barrier

Y1-

Capacitor

Transformer

R15

R17

R13

C21

TOP252-262

R12

C16

C17

C18

R20

R21

HS2

Output

Rectier

Output Filter

Capacitor

C19

Figure 50c. Layout Considerations for TOPSwitch-HX Using L Package and Operating at 132 kHz.

Quick Design Checklist

In order to reduce the no-load input power of TOPSwitch-HX designs, the V-pin (or M-pin for P Package) operates at very low current. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V-pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 10 mm of the V-pin to minimize the V pin node area. The DC bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the V-pin as this may cause misoperation of the V pin related functions.

As with any power supply design, all TOPSwitch-HX designs should be veriﬁed on the bench to make sure that components speciﬁcations are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended:

1. Maximum drain voltage – Verify that peak VDS does not

exceed 675 V at highest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just before the power supply goes into auto-restart (loss of regulation).

2. Maximum drain current – At maximum ambient temperature,

maximum input voltage and maximum output load, verify

drain current waveforms at start-up for any signs of transformer saturation and excessive leading edge current spikes. TOPSwitch-HX has a leading edge blanking time of 220 ns to prevent premature termination of the ON-cycle. Verify that the leading edge current spike is below the allowed current limit envelope (see Figure 53) for the drain current waveform at the end of the 220 ns blanking period.

3. Thermal check – At maximum output power, both minimum and maximum voltage and ambient temperature; verify that temperature speciﬁcations are not exceeded for TOPSwitch-HX, transformer, output diodes and output capacitors. Enough thermal margin should be allowed for the part-to-part variation of the R speciﬁed in the data sheet. The margin required can either be calculated from the values in the parameter table or it can be accounted for by connecting an external resistance in series with the DRAIN pin and attached to the same heat sink, having a resistance value that is equal to the difference between the measured R the worst case maximum speciﬁcation.

Design Tools

Up-to-date information on design tools can be found at the Power Integrations website: www.power.com

Out

of TOPSwitch-HX, as

DS(ON)

of the device under test and

DS(ON)

PI-5216-091508

www.power.com

Rev. J 08/16

Page 32

TOP252-262

Absolute Maximum Ratings

(2)

DRAIN Peak Voltage ...........................................-0.3 V to 700 V

DRAIN Peak Current: TOP252 DRAIN Peak Current: TOP253 DRAIN Peak Current: TOP254 DRAIN Peak Current: TOP255 DRAIN Peak Current: TOP256 DRAIN Peak Current: TOP257 DRAIN Peak Current: TOP258 DRAIN Peak Current: TOP259 DRAIN Peak Current: TOP260 DRAIN Peak Current: TOP261 DRAIN Peak Current: TOP262 CONTROL Voltage

CONTROL Current

................................................. -0.3 V to 9 V

........................................................ 100 mA

......................................... 0.68 A

......................................... 1.37 A

......................................... 2.08 A

......................................... 2.72 A

......................................... 4.08 A

......................................... 5.44 A

......................................... 6.88 A

......................................... 7.73 A

......................................... 9.00 A

....................................... 11.10 A

Thermal Resistance

Thermal Resistance: Y Package:

(qJA) ........................................... 80 °C/W

(qJC) ............................................. 2 °C/W

P, G and M Packages:

(qJA) ......................... .70 °C/W

(3)

; 60 °C/W

(qJC) .......................................... .11 °C/W

E/L Package:

) ............................................105 °C/W

(qJC) ............................................. 2 °C/W

Conditions

Parameter Symbol

SOURCE = 0 V; T

See Figure 54

(Unless Otherwise Speciﬁed)

Control Functions

FREQUENCY Pin

Connected to SOURCE

Switching Frequency in Full Frequency Mode (average)

OSC

TJ = 25 °C

FREQUENCY Pin

Connected to CONTROL

TOP252-258P/G/M

Frequency Jitter Deviation Frequency Jitter Modulation Rate

132 kHz Operation ±5

66 kHz Operation ±2.5

IV ≤ I

Maximum Duty Cycle DC

Soft-Start Time t

SOFT

PWM Gain DC

PWM Gain Temperature Drift

External Bias Current

MAX

reg

IC = I

CD1

TJ = 25 °C 17 ms

TJ = 25 °C

See Note A -0.01 %/mA/°C

66 kHz Operation

VOLTAGE MONITOR Pin Voltage ........................... -0.3 V to 9 V

CURRENT LIMIT Pin Voltage MULTI-FUNCTION Pin Voltage

FREQUENCY Pin Voltage ......................................

Storage Temperature ......................................

Operating Junction Temperature Lead Temperature

(1)

........................................................260 °C

.............................. -0.3 V to 4.5 V

............................... -0.3 V to 9 V

-0.3 V to 9 V

-65 °C to 150 °C

......................-40 °C to 150 °C

Notes:

1. 1/16 in. from case for 5 seconds.

2. Maximum ratings speciﬁed may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for

extended periods of time may affect product reliability.

Notes:

(1)

1. Free standing with no heat sink.

(2)

2. Measured at the back surface of tab.

3. Soldered to 0.36 sq. in. (232 mm

(4)

4. Soldered to 1 sq. in. (645 mm

(5)

5. Measured on the SOURCE pin close to plastic interface.

(1)

(2)

= -40 to 125 °C

TOP252-258Y

Min Typ Max Units

119 132 145

), 2 oz. (610 g/m2) copper clad.

TOP255-262L TOP252-262E

TOP252-258Y

59.4 66 72.6 TOP255-262L TOP252-262E

TOP259-261Y

59.4 66 72.6

250 Hz

or IM ≤ I

V(DC)

VV, VM = 0 V

or IM = 95 mA 30

M(DC) or

75 78 83

TOP252-255 -31 -25 -20

TOP259-262 -25 -20 -15

TOP252-255 0.9 1.5 2.1

TOP259-262 1.1 1.7 2.4

kHz

%/mATOP256-258 -27 -22 -17

mATOP256-258 1.0 1.6 2.2

Rev. J 08/16

www.power.com

Page 33

Conditions

Parameter Symbol

SOURCE = 0 V; TJ = -40 to 125 °C

(Unless Otherwise Speciﬁed)

Control Functions (cont.)

TOP252-255 1.0 1.6 2.2

External Bias Current I

132 kHz Operation

TOP259-262 1.6 2.2 2.9

TOP252-255 4.4 5.8

CONTROL Current at 0% Duty Cycle

C(OFF)

66 kHz Operation

132 kHz Operation

TOP256-258 4.7 6.1

TOP259-262 5.1 6.5

TOP252-255 4.6 6.0

TOP256-258 5.1 6.5

TOP259-262 6.0 7.4

Dynamic Impedance Z

IC = 4 mA; TJ = 25 °C, See Figure 52 10 18 22

Dynamic Impedance Temperature Drift

CONTROL Pin Internal Filter Pole

Upper Peak Current to Set Current Limit Ratio

Lower Peak Current to Set Current Limit Ratio

PS(UPPER)

PS(LOWER)

TJ = 25 °C

See Note B

TJ = 25 °C

See Note B

Multi-CycleModulation Switching Frequency

Minimum Multi-CycleModulation On Period

MCM(MIN)

TJ = 25 °C 30 kHz

TJ = 25 °C 135 ms

Shutdown/Auto-Restart

= 0 V

Control Pin Charging Current

Charging Current Temperature Drift

C(CH)

TJ = 25 °C

See Note A 0.5 %/°C

= 5 V

Auto-Restart Upper Threshold Voltage

Auto-Restart Lower Threshold Voltage

C(AR)U

C(AR)L

Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs

Auto-Restart Hysteresis Voltage

Auto-Restart Duty Cycle

Auto-Restart Frequency

Line Undervoltage Threshold Current and Hysteresis (M or V Pin)

Line Overvoltage Threshold Current and Hysteresis (M or V Pin)

C(AR)hyst

(AR)

Threshold 22 25 27 mA

TJ = 25 °C

Hysteresis 14 mA

Threshold 107 112 117 mA

TJ = 25 °C

Hysteresis 4 mA

TOP252-262

Min Typ Max Units

mATOP256-258 1.3 1.9 2.5

0.18 %/°C

7 kHz

50 55 60 %

25 %

-5.0 -3.5 -1.0

-3.0 -1.8 -0.6

5.8 V

4.5 4.8 5.1 V

0.8 1.0 V

2 4 %

0.5 Hz

www.power.com

Rev. J 08/16

Page 34

TOP252-262

Conditions

Parameter Symbol

SOURCE = 0 V; T

= -40 to 125 °C

(Unless Otherwise Speciﬁed)

Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs

Output Overvoltage Latching Shutdown Threshold Current

V or M Pin Reset Voltage

Remote ON/OFF Negative Threshold Current and Hysteresis (M or X Pin)

V or M Pin Short Circuit Current

X or M Pin Short Circuit Current

V or M Pin Voltage (Positive Current)

V or M Pin Voltage Hysteresis (Positive Current)

OV(LS)

V(TH)

M(TH)

REM (N)

V(SC) or

M(SC)

X(SC) or

M(SC)

VV or V

V(hyst)

M(hyst)

TJ = 25 °C 269 336 403 mA

TJ = 25 °C 0.8 1.0 1.6 V

Threshold -35 -27 -20

TJ = 25 °C

Hysteresis 5

TJ = 25 °C VV, VM = V

VX, VM = 0 V

Normal Mode -260 -200 -140

Auto-Restart Mode -95 -75 -55

IV or IM = I

TOP252-TOP257 2.79 3.0 3.21

TOP258-TOP262 2.83 3.0 3.25

IV or IM = I

Min Typ Max Units

300 400 500 mA

2.10 2.8 3.20

0.2 0.5 V

X or M Pin Voltage (Negative Current)

VX or V

Maximum Duty Cycle Reduction Onset Threshold Current

Maximum Duty Cycle Reduction Slope

Remote OFF DRAIN Supply Current

Remote ON Delay t

Remote OFF Setup Time

Frequency Input

FREQUENCY Pin Threshold Voltage

V(DC) or

M(DC)

D(RMT)

R(ON)

R(OFF)

IC ≥ IB, TJ = 25 °C 18.9 22.0 24.2 mA

TJ = 25 °C

= 150 V

DRAIN

From Remote ON to Drain

Turn-On

See Note B

Minimum Time Before Drain

Turn-On to Disable Cycle

See Note B

See Note B 2.9 V

IX or IM = -50 mA 1.23 1.30 1.37

IX or IM = -150 mA 1.15 1.22 1.29

< IV <48 mA or

V(DC)

< IM <48 mA

M(DC)

or IM ≥48 mA -0.25

X, V or M Pin

Floating

V or M Pin Shorted to

CONTROL

-1.0

0.6 1.0

1.0 1.6

66 kHz 3.0

132 kHz

1.5

66 kHz 3.0

132 kHz

1.5

%/mA

FREQUENCY Pin Input Current

Rev. J 08/16

TJ = 25 °C

= V

10 55 90 mA

www.power.com

Page 35

Parameter Symbol

Circuit Protection

Self Protection Current Limit (See Note C)

LIMIT

Conditions

SOURCE = 0 V; T

= -40 to 125 °C

(Unless Otherwise Speciﬁed)

TOP252PN/GN/MN

= 25 °C

TOP252EN

= 25 °C

TOP253PN/GN

= 25 °C

TOP253MN

= 25 °C

TOP253EN

= 25 °C

TOP254PN/GN

= 25 °C

TOP254MN

= 25 °C

TOP254YN/EN

= 25 °C

TOP255PN/GN

= 25 °C

TOP255MN

= 25 °C

TOP255LN

TJ = 25 °C

TOP255YN/EN

= 25 °C

TOP256PN/GN

= 25 °C

TOP256MN

= 25 °C

TOP256LN

= 25 °C

TOP256YN/EN

= 25 °C

TOP257PN/GN

= 25 °C

TOP257MN

= 25 °C

TOP257LN

= 25 °C

TOP257YN/EN

= 25 °C

TOP258PN/GN

= 25 °C

TOP258MN

= 25 °C

TOP258LN

= 25 °C

di/dt = 45 mA/ms 0.400 0.43 0.460

di/dt = 90 mA/ms 0.400 0.43 0.460

di/dt = 80 mA/ms 0.697 0.75 0.803

di/dt = 90 mA/ms 0.790 0.85 0.910

di/dt = 180 mA/ms 0.790 0.85 0.910

di/dt = 105 mA/ms 0.93 1.00 1.07

di/dt = 135 mA/ms 1.209 1.30 1.391

di/dt = 270 mA/ms 1.209 1.30 1.391

di/dt = 120 mA/ms 1.069 1.15 1.231

di/dt = 175 mA/ms 1.581 1.70 1.819

di/dt = 350 mA/ms 1.581 1.70 1.819

di/dt = 140 mA/ms 1.255 1.35 1.445

di/dt = 220 mA/ms 1.953 2.10 2.247

di/dt = 435 mA/ms 1.953 2.10 2.247

di/dt = 530 mA/ms 2.371 2.55 2.729

di/dt = 155 mA/ms 1.395 1.50 1.605

di/dt = 265 mA/ms 2.371 2.55 2.729

di/dt = 530 mA/ms 2.371 2.55 2.729

di/dt = 705 mA/ms 3.162 3.40 3.638

di/dt = 170 mA/ms 1.534 1.65 1.766

di/dt = 310 mA/ms 2.790 3.00 3.210

di/dt = 620 mA/ms 2.790 3.00 3.210

TOP252-262

Min Typ Max Units

www.power.com

Rev. J 08/16

Page 36

TOP252-262

Parameter Symbol

Circuit Protection (cont.)

Self Protection Current Limit (See Note C)

Initial Current Limit I

Power Coefﬁcient P

Leading Edge Blanking Time

Current Limit Delay t

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

Power-Up Reset Threshold Voltage

Output

ON-State Resistance

LIMIT

INIT

COEFF

LEB

IL(D)

C(RESET)

DS(ON)

Conditions

SOURCE = 0 V; T

= -40 to 125 °C

Min Typ Max Units

(Unless Otherwise Speciﬁed)

TOP258YN/EN

TJ = 25 °C

TOP259LN

= 25 °C

TOP259YN/EN

= 25 °C

TOP260LN

= 25 °C

TOP260YN/EN

= 25 °C

TOP261LN

= 25 °C

TOP261YN/EN

= 25 °C

TOP262LN

= 25 °C

TOP262EN

= 25 °C

TJ = 25 °C,

See Note D

See Note B

di/dt = 890 mA/ms 3.999 4.30 4.601

di/dt = 720 mA/ms 3.236 3.48 3.724

di/dt = 1065 mA/ms 4.790 5.15 5.511

di/dt = 870 mA/ms 3.906 4.20 4.494

di/dt = 1240 mA/ms 5.580 6.00 6.420

di/dt = 1065 mA/ms 4.808 5.17 5.532

di/dt = 1530 mA/ms 6.882 7.40 7.918

di/dt = 1065 mA/ms 4.808 5.17 5.532

di/dt = 1530 mA/ms 6.882 7.40 7.918

0.70 ×

LIMIT(MIN)

or IM ≤ - 165 mA 0.9 × I2f I2f 1.2 × I2f

IX or IM ≤ - 117 mA 0.9 × I2f I2f 1.2 × I2f

TJ = 25 °C, See Figure 53 220 ns

100 ns

135 142 150 °C

75 °C

Figure 54 (S1 Open Condition) 1.75 3.0 4.25 V

TOP252

= 50 mA

TOP253

= 100 mA

TOP254

= 150 mA

TOP255

= 200 mA

TOP256

= 300 mA

TOP257

= 400 mA

TOP258

= 500 mA

= 25 °C 19.1 22.00

= 100 °C 28.8 33.40

= 25 °C 8.8 10.10

= 100 °C 13.1 15.20

= 25 °C 5.4 6.25

= 100 °C 8.35 9.70

= 25 °C 4.1 4.70

= 100 °C 6.3 7.30

= 25 °C 2.8 3.20

= 100 °C 4.1 4.75

= 25 °C 2.0 2.30

= 100 °C 3.1 3.60

= 25 °C 1.7 1.95

= 100 °C 2.5 2.90

A2kHz

Rev. J 08/16

www.power.com

Page 37

Parameter Symbol

Output (cont.)

ON-State Resistance

DRAIN Supply Voltage

OFF-State Drain Leakage Current

Breakdown Voltage

DS(ON)

DSS

Conditions

SOURCE = 0 V; T

= -40 to 125 °C

(Unless Otherwise Speciﬁed)

TOP259

= 600 mA

TOP260

= 700 mA

TOP261

= 800 mA

TOP262

= 900 mA

≤ 85 °C, See Note E 18

= 25 °C 1.45 1.70

= 100 °C 2.25 2.60

= 25 °C 1.20 1.40

= 100 °C 1.80 2.10

= 25 °C 1.05 1.20

= 100 °C 1.55 1.80

= 25 °C 0.90 1.05

= 100 °C 1.35 1.55

VV, VM = Floating, IC = 4 mA,

= 560 V, TJ = 125 °C

VV, VM = Floating, IC = 4 mA,

= 25 °C

See Note F

TOP252-262

Min Typ Max Units

470 mA

700 V

Rise Time t

Fall Time t

Measured in a Typical Flyback

Converter Application

100 ns

50 ns

Supply Voltage Characteristics

TOP252-255 0.6 1.2 2.0

66 kHz

Operation

132 kHz

Operation

TOP256-258 0.9 1.4 2.3

TOP259-262 1.1 1.6 2.5

TOP252-255 0.8 1.3 2.2

TOP256-258 1.1 1.6 2.5

Control Supply/ Discharge Current

CD1

Output

MOSFET

Enabled

, VV, VM =

0 V

TOP259-262 1.5 2.2 2.9

CD2

Output MOSFET Disabled

, VV, VM = 0 V

0.3 0.6 1.3

NOTES: A. For speciﬁcations with negative values, a negative temperature coefﬁcient corresponds to an increase in magnitude with increas-

ing temperature, and a positive temperature coefﬁcient corresponds to a decrease in magnitude with increasing temperature.

B. Guaranteed by characterization. Not tested in production.

C. For externally adjusted current limit values, please refer to Figures 55a and 55b (Current Limit vs. External Current Limit Resis-

tance) in the Typical Performance Characteristics section. The tolerance speciﬁed is only valid at full current limit.

D. I2f calculation is based on typical values of I

/ F pin connection. See f

speciﬁcation for detail.

OSC

LIMIT

and f

OSC,

i.e. I

LIMIT(TYP)

× f

, where f

OSC

= 66 kHz or 132 kHz depending on package

OSC

E. The TOPSwitch-HX will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops signiﬁcantly at tempera-

tures below 0 °C. For reliable start up at 18 V in sub zero temperatures, designers must ensure that circuit capacitors meet recommended capacitance values.

F. Breakdown voltage may be checked against minimum BV

exceeding minimum BV

DSS

speciﬁcation by ramping the DRAIN pin voltage up to but not

DSS

www.power.com

Rev. J 08/16

Page 38

TOP252-262

CONTROL Pin Current (mA)

DRAIN Current (normalized)

90%

DRAIN

VOLTAGE

D =

10%

0 V

PI-2039-033001

Figure 51. Duty Cycle Measurement.

(Blanking Time)

120

1.3

1.2

100

Dynamic

Impedance

PI-4737-061207

Slope

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

5 6 7 8 9

CONTROL Pin Voltage (V)

Figure 52. CONTROL Pin I-V Characteristic. Figure 53. Drain Current Operating Envelope.

LEB

INIT(MIN)

0 1 2 6 83

4 5 7

Time (µs)

PI-4758-061407

40 V

0-15 V

NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.

2. For P, G and M packages, short all SOURCE pins together.

Figure 54. TOPSwitch-HX General Test Circuit.

Rev. J 08/16

TOP254-258 Y, all E, L or M Packages (X and V Pins)

470 Ω

5 W

0-300 kΩ

5-50 V

TOPSwitch-HX

0.1 µF47 µF

CONTROL

0-60 kΩ

P or G Package (M Pin)

0-300 kΩ

5-50 V

0-60 kΩ

SFX

TOP259-261 Y (X and V Pins)

0-300 kΩ

CONTROL

5-50 V

www.power.com

SGX

PI-4738-071408

Page 39

PI-4754-120307

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

-200 -150 -100 -50 0

or IM ( µA )

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

Typical

Notes:

1. Maximum and Minimum levels are based on characterization.

2. T

= 0 OC to 125 OC.

Minimum

Maximum

Normalized Current Limit

Normalized di/dt

PI-4755-120307

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

0510 15 20 25 30 35 40 45

( kΩ )

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

Notes:

1. Maximum and Minimum levels are based on characterization.

2. T

= 0 OC to 125 OC.

3. Includes the variation of X or M pin voltage

Typical

Maximum

Minimum

Normalized Current Limit

Normalized di/dt

Typical Performance Characteristics

Figure 55a. Normalized Current Limit vs. X or M Pin Current.

TOP252-262

Figure 55b. Normalized Current Limit vs. External Current Limit Resistance.

www.power.com

Rev. J 08/16

Page 40

TOP252-262

Breakdown Voltage

(Normalized to 25

Output Frequency

(Normalized to 25

1.2

PI-4760-061407

Current Limit

(Normalized to 25

Junction Temperature (°C)

(Normalized to 25

PI-4761-061407

Overvoltage Threshold

(Normalized to 25

Under-Voltage Threshold

(Normalized to 25

Typical Performance Characteristics (cont.)

1.1

PI-176B-033001

°C)

1.2

1.0

°C)

0.8

1.0

0.6

0.4

0.2

0.9

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Figure 56. Breakdown Voltage vs. Temperature. Figure 57. Frequency vs. Temperature.

1.0

°C)

0.8

0.6

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

1.2

1.0

°C)

0.8

0.6

PI-4759-061407

PI-4739-061507

0.4

0.2

Figure 58. Internal Current Limit vs. Temperature.

1.2

1.0

°C)

0.8

0.6

0.4

0.2

Figure 60. Overvoltage Threshold vs. Temperature.

Rev. J 08/16

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

0.4

Current Limit

0.2

-50 -25 0 25 50 75 100 125 150

Figure 59. External Current Limit vs. Temperature with RIL = 10.5 kW.

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50 -25 0 25 50 75 100 125 150

PI-4762-061407

Junction Temperature (°C)

Figure 61. Undervoltage Threshold vs. Temperature.

www.power.com

Page 41

Typical Performance Characteristics (cont.)

VOLTAGE MONITOR Pin Voltage (V)

EXTERNAL CURRENT LIMIT

MULTI-FUNCTION Pin Voltage (V)

Junction Temperature (°C)

PI-4763-072208

CONTROL Current

(Normalized to 25

Junction Temperature (°C)

PI-4764-061407

Onset Threshold Current

(Normalized to 25

TOP252-262

5.5

4.5

3.5

2.5

0 100 200 500400300

VOLTAGE-MONITOR Pin Current (µA)

Figure 62a. VOLTAGE-MONITOR Pin vs. Current.

PI-4740-060607

PI-4742-021308

1.6

VX = 1.354 - 1147.5 × IX + 1.759 × 106 ×

1.4

)2 with -180 µA < I

< -25 µA

1.2

1.0

0.8

0.6

Pin Voltage (V)

0.4

0.2

-200 -150 -50-100 0

EXTERNAL CURRENT LIMIT Pin Current (µA)

Figure 62b. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.

1.6

VM = 1.354 - 1147.5 × IM + 1.759 × 106 ×

1.4

1.2

1.0

0.8

)2 with -180 µA < I

< -25 µA

PI-4743-061407

PI-4741-110907

See expanded

version (Figure 63b)

-200 -100 0 100 200 300 400 500

MULTI-FUNCTION Pin Current (µA)

Figure 63a. MULTI-FUNCTION Pin Voltage vs. Current.

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50 -25 0 25 50 75 100 125 150

0.6

0.4

0.2

-200 -150 -50-100 0

MULTI-FUNCTION Pin Current (µA)

Figure 63b. MULTI-FUNCTION Pin Voltage vs. Current (Expanded).

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50 -25 0 25 50 75 100 125 150

Figure 64. Control Current Out at 0% Duty Cycle vs. Temperature.

www.power.com

Figure 65. Maximum Duty Cycle Reduction Onset Threshold

Current vs. Temperature.

Rev. J 08/16

Page 42

TOP252-262

CONTROL Pin Current (mA)

DRAIN Current (A)

DRAIN Capacitance (pF)

Remote OFF DRAIN Supply Current

(Normalized to 25

Typical Performance Characteristics (cont.)

VC = 5 V

PI-4748-071708

0.5

= 25 °C

CASE

= 100 °C

CASE

2 4 6 8 10 12 14 16 18 20

Drain Voltage (V)

Figure 66. Output Characteristics. Figure 67. IC vs. DRAIN Voltage.

10000

1000

100

Scaling Factors: TOP262 1.82 TOP261 1.62 TOP260 1.42 TOP259 1,17 TOP258 1.00 TOP257 0.85 TOP256 0.61 TOP255 0.42 TOP254 0.32 TOP253 0.20 TOP252 0.10

Scaling Factors: TOP262 1.82 TOP261 1.62 TOP260 1.42 TOP259 1.17 TOP258 1.00 TOP257 0.85 TOP256 0.61 TOP255 0.42 TOP254 0.32 TOP253 0.20 TOP252 0.10

PI-4749-071708

-0.5

-1

-1.5

-2

-2.5

0 20 40 60 80 100

Drain Pin Voltage (V)

500

Scaling Factors: TOP262 1.82 TOP261 1.62

400

TOP260 1.42 TOP259 1.17 TOP258 1.00

300

TOP257 0.85 TOP256 0.61 TOP255 0.42 TOP254 0.32

200

Power (mW)

TOP253 0.20 TOP252 0.10

100

PI-4744-072208

PI-4750-071708

132 kHz

66 kHz

0 100 200 300 400 500 600

Drain Pin Voltage (V)

Figure 68. C

Rev. J 08/16

vs. DRAIN Voltage. Figure 69. DRAIN Capacitance Power.

OSS

0 200100 400 500 600300 700

1.2

1.0

°C)

0.8

0.6

0.4

0.2

-50

0-25 5025 10075 125 150

Junction Temperature (°C)

Figure 70. Remote OFF DRAIN Supply Current vs. Temperature.

Drain Pin Voltage (V)

PI-4745-061407

www.power.com

Page 43

.146 (3.71) .156 (3.96)

.390 (9.91)

.420 (10.67)

TO-220-7C (Y Package)

.108 (2.74) REF

.165 (4.19) .185 (4.70)

.234 (5.94) .261 (6.63)

TOP252-262

.045 (1.14) .055 (1.40)

.860 (21.84) .880 (22.35)

PIN 1

.050 (1.27)

.200 (5.08)

.150 (3.81)

.050 (1.27)

PIN 1

.100 (2.54)

.461 (11.71) .495 (12.57)

.068 (1.73) MIN

.024 (.61) .034 (.86)

.050 (1.27) BSC

.150 (3.81) BSC

.180 (4.58)

.010 (.25) M

.050 (1.27)

PIN 7

.150 (3.81)

.570 (14.48) REF.

7° TYP.

.080 (2.03) .120 (3.05)

PIN 1 & 7

.012 (.30) .024 (.61)

.190 (4.83) .210 (5.33)

Notes:

1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses.

2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front.

3. Dimensions do not include mold ﬂash or other protrusions. Mold ﬂash or protrusions shall not exceed .006 (.15 mm) on any side.

4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm).

5. Position of terminals to be measured at a location .25 (6.35) below the package body.

6. All terminals are solder plated.

PIN 2 & 4

.040 (1.02) .060 (1.52)

.670 (17.02) REF.

Y07C

www.power.com

MOUNTING HOLE PATTERN

PI-2644-040110

Rev. J 08/16

Page 44

TOP252-262

-E-

.240 (6.10) .260 (6.60)

Pin 1

-D-

.125 (3.18) .145 (3.68)

-TSEATING PLANE

.100 (2.54) BSC

D S

⊕

.356 (9.05) .387 (9.83)

.014 (.36) .022 (.56)

.004 (.10)

.048 (1.22) .053 (1.35)

⊕

T E D S

PDIP-8C (P Package)

Notes:

1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing.

2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.

3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side.

4. Pin locations start with Pin 1, and continue counter-clock wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted.

5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm).

6. Lead width measured at package body.

7. Lead spacing measured with the leads constrained to be .057 (1.45) .068 (1.73)

(NOTE 6)

.015 (.38) MINIMUM

.118 (3.00) .140 (3.56)

.137 (3.48)

MINIMUM

.010 (.25) M

perpendicular to plane T.

.008 (.20) .015 (.38)

.300 (7.62) BSC

(NOTE 7)

.300 (7.62) .390 (9.91)

P08C

PI-3933-081716

.200 (5.08) Max

SEATING PLANE

.020 (.51) Min

.070 (1.78) BSC

SDIP-10C (M Package)

10 6

.367 (9.32) .387 (9.83)

.030 (.76)

.040 (1.02)

.014 (.36) .022 (.56)

-E-

.240 (6.10) .260 (6.60)

-D-

.125 (3.18) .145 (3.68)

.120 (3.05) .140 (3.56)

⊕

-F-

.010 (.25) M

Notes:

1. Package dimensions conform to JEDEC speciﬁcation MS-019.

2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.

3. Dimensions shown do not include mold ﬂash or other protrusions. Mold ﬂash or protrusions shall not exceed .006 (.15) on any side.

4. D, E and F are reference datums.

5. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

.300 (7.62)

.340 (8.64

.008 (.20) .015 (.38)

.300 BSC

F D E

.300 (7.62) .390 (9.91)

PI-4648-101507

P10C

Rev. J 08/16

www.power.com

Page 45

SMD-8C (G Package)

TOP252-262

-E-

.240 (6.10) .260 (6.60)

Pin 1

-D-

.125 (3.18) .145 (3.68)

.032 (.81) .037 (.94)

D S

.004 (.10)

⊕

.100 (2.54) (BSC)

.356 (9.05) .387 (9.83)

.048 (1.22) .053 (1.35)

.372 (9.45) .388 (9.86)

E S

⊕

.137 (3.48) MINIMUM

.057 (1.45) .068 (1.73)

(NOTE 5)

.009 (.23)

.010 (.25)

.046

.086

Pin 1

Solder Pad Dimensions

.004 (.10) .012 (.30)

.060

.186

.286

.004 (.10)

.036 (0.91) .044 (1.12)

.060

.046

.080

Notes:

1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.

2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side.

3. Pin locations start with Pin 1,

.420

and continue counter-clock wise to Pin 8 when viewed from the top. Pin 3 is omitted.

4. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm).

5. Lead width measured at package body.

6. D and E are referenced datums on the package body.

0 -

G08C

PI-4015-081716

www.power.com

Rev. J 08/16

Page 46

TOP252-262

eSIP-7C (E Package)

0.403 (10.24)

0.397 (10.08)

0.325 (8.25)

0.320 (8.13)

Pin #1

I.D.

0.070 (1.78) Ref.

0.050 (1.27)

FRONT VIEW

10° Ref.

All Around

0.378 (9.60) Ref.

END VIEW

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold ﬂash, tie bar burrs, gate burrs, and interlead ﬂash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead ﬂash or protrusions.

5. Controlling dimensions in inches (mm).

0.020 M 0.51 M C

0.021 (0.53)

0.019 (0.48)

0.048 (1.22)

0.046 (1.17)

0.019 (0.48) Ref.

Detail A

0.140 (3.56)

0.120 (3.05)

0.016 (0.41)

0.011 (0.28)

0.060 (1.52) Ref.

6×

0.016 (0.41)

0.118 (3.00)

SIDE VIEW

DETAIL A

0.081 (2.06)

0.077 (1.96)

0.290 (7.37)

Ref.

0.047 (1.19)

0.027 (0.70)

Ref.

0.519 (13.18)

0.020 (0.50)

0.023 (0.58)

Ref.

0.207 (5.26)

0.187 (4.75)

0.100 (2.54)

PIN 1

0.264 (6.70) Ref.

0.010 M 0.25 M C A B

BACK VIEW

0.100 (2.54)

0.059 (1.50)

0.100 (2.54) 0.100 (2.54)

MOUNTING HOLE PATTERN

(not to scale)

0.198 (5.04) Ref.

0.033 (0.84)

0.028 (0.71)

0.050 (1.27)

0.155 (3.93)

0.059 (1.50)

PI-4917-061510

6×

PIN 7

Rev. J 08/16

www.power.com

Page 47

eSIP-7F (L Package)

TOP252-262

0.325 (8.25)

0.320 (8.13)

Pin 1 I.D.

0.050 (1.27)

0.060 (1.52) Ref.

0.019 (0.48) Ref.

0.403 (10.24)

0.397 (10.08)

0.081 (2.06)

0.077 (1.96)

Detail A

0.290 (7.37) Ref.

0.047 (1.19) Ref.

0.129 (3.28)

0.490 (12.45) Ref.

0.084 (2.14)

0.173 (4.40)

0.163 (4.15)

0.100 (2.54)

1 7

0.016 (0.41)

0.011 (0.28)

0.020 M 0.51 M C

0.070 (1.78) Ref.

6×

0.122 (3.08)

0.010 M 0.25 M C A B

BOTTOM VIEW

SIDE VIEW

TOP VIEW

Exposed pad hidden Exposed pad up

Notes:

1 7

0.021 (0.53)

0.019 (0.48)

0.020 (0.50)

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

0.378 (9.60) Ref.

0.048 (1.22)

0.046 (1.17)

0.023 (0.58)

0.027 (0.70)

3. Dimensions noted are inclusive of plating

END VIEW

DETAIL A (Not drawn to scale)

thickness.

4. Does not include inter-lead ﬂash or protrusions.

5. Controlling dimensions in inches (mm).

0.264 (6.70) Ref.

0.198 (5.04) Ref.

0.089 (2.26)

0.079 (2.01)

0.033 (0.84)

0.028 (0.71)

6×

www.power.com

PI-5204-061510

Rev. J 08/16

Page 48

TOP252-262

Part Ordering Information

TOP 258 G N - TL

Rev. J 08/16

• TOPSwitch Product Family

• HX Series Number

• Package Identiﬁer

P Plastic DIP-8C

G Plastic SMD-8C

M Plastic SDIP-10C

Y Plastic TO-220-7C

E Plastic eSIP-7C

L Plastic eSIP-7F

• Pin Finish

N Pure Matte Tin (Pb-Free) (P, G, M, E, L and Y Packages)

G Green Mold Compound (Speciﬁc E Packages Only)

• Tape & Reel and Other Options

Blank Standard Conﬁgurations

TL G Package (1000 min/mult.)

www.power.com

Page 49

TOP252-262

Revision Notes Date

B Data sheet release. 02/08

C Added L package and TOP262. 07/08

D Changed eSIP-7E to eSIP-7F. Added detail to PI-4917 and PI-5204. 08/08

E Released TOP255-259LN and TOP262EN parts. 10/08

F Added note for TOP256E halogen free part availability. 01/09

Added note for TOP258P and TOP259E halogen free part availability. Updated E & L bend package drawings. Minor text

changes to page 27.

H Added EG parts. Removed Note 7 from Table 1 on page 2. 06/13

I Updated with new Brand Style. 05/15

Updated PDIP-8C (P Package) and SMD-8C (G Package) per PCN-16232.

01/10

08/16

www.power.com

Rev. J 08/16

Page 50

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant injury or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

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Via Milanese 20, 3rd. Fl. 20099 Sesto San Giovanni (MI) Italy Phone: +39-024-550-8701 Fax: +39-028-928-6009 e-mail: eurosales@power.com

Japan

Kosei Dai-3 Bldg. 2-12-11, Shin-Yokohama, Kohoku-ku Yokohama-shi, Kanagawa 222-0033 Japan Phone: +81-45-471-1021 Fax: +81-45-471-3717 e-mail: japansales@power.com

Korea

RM 602, 6FL Korea City Air Terminal B/D, 159-6 Samsung-Dong, Kangnam-Gu, Seoul, 135-728, Korea Phone: +82-2-2016-6610 Fax: +82-2-2016-6630 e-mail: koreasales@power.com

Singapore

51 Newton Road #19-01/05 Goldhill Plaza Singapore, 308900 Phone: +65-6358-2160 Fax: +65-6358-2015 e-mail: singaporesales@power. com

Taiwan

5F, No. 318, Nei Hu Rd., Sec. 1 Nei Hu Dist. Taipei 11493, Taiwan R.O.C. Phone: +886-2-2659-4570 Fax: +886-2-2659-4550 e-mail: taiwansales@power.com

Cambridge Semiconductor, a Power Integrations company Westbrook Centre, Block 5, 2nd Floor Milton Road Cambridge CB4 1YG Phone: +44 (0) 1223-446483 e-mail: eurosales@power.com