Datasheet TOP201YAI, TOP200YAI, TOP214YAI, TOP204YAI, TOP202YAI Datasheet (Power Integrations)

PI-1703-112995

AC

IN

DRAIN

SOURCE

CONTROL

TOPSwitch

TOP200-4/14

®

TOPSwitch

Three-terminal Off-line PWM Switch

Product Highlights

Low Cost Replacement for Discrete Switchers

• 20 to 50 fewer components - cuts cost, increases reliability

• Source-connected tab and Controlled MOSFET turn-on
reduce EMI and EMI filter costs

• Allows for a 50% smaller and lighter solution

• Cost competitive with linears above 5 W

Up to 90% Efficiency in Flyback Topology

• Built-in start-up and current limit reduce DC losses

• Low capacitance 700 V MOSFET cuts AC losses

• CMOS controller/gate driver consumes only 6 mW

• 70% maximum duty cycle minimizes conduction losses

Simplifies Design - Reduces Time to Market

• Supported by many reference design boards

• Integrated PWM Controller and 700 V MOSFET in a
industry standard three pin TO-220 package

• Only one external capacitor needed for compensation,
bypass and start-up/auto-restart functions

Family

Figure 1. Typical Application.

TOPSwitch

®

SELECTION GUIDE

System Level Fault Protection Features

• Auto-restart and cycle by cycle current limiting functions
handle both primary and secondary faults

• On-chip latching thermal shutdown protects the entire
system against overload

Highly Versatile

• Implements Buck, Boost, Flyback or Forward topology

• Easily interfaces with both opto and primary feedback

• Supports continuous or discontinuous mode of operation

Description

The TOPSwitch family implements, with only three pins, all
functions necessary for an off-line switched mode control
system: high voltage N-channel power MOSFET with controlled
turn-on gate driver, voltage mode PWM controller with
integrated 100 kHz oscillator, high voltage start-up bias circuit,
bandgap derived reference, bias shunt regulator/error amplifier
for loop compensation and fault protection circuitry. Compared
to discrete MOSFET and controller or self oscillating (RCC)
switching converter solutions, a TOPSwitch integrated circuit
can reduce total cost, component count, size, weight and at the
same time increase efficiency and system reliability. These

OUTPUT POWER RANGE

ORDER

PART

NUMBER

TOP200YAI* 0-25 W 0-12 W 0-25 W
TOP201YAI* 20-45 W 10-22 W 20-50 W
TOP202YAI* 30-60 W 15-30 W 30-75 W
TOP203YAI* 40-70 W 20-35 W 50-100 W
TOP214YAI* 50-85 W 25-42 W 60-125 W
TOP204YAI* 60-100 W 30-50 W 75-150 W

* Package Outline: Y03A

devices are intended for 100/110/230 VAC off-line Power
Supply applications in the 0 to 100 W (0 to 50 W universal)
range and 230/277 VAC off-line power factor correction (PFC)
applications in the 0 to 150 W range.

FLYBACK

230 VAC or

110 VAC

w/Doubler

85-265

VAC

PFC/

BOOST

230/277

VAC

July 1996

TOP200-4/14

CONTROL

Z

C

SHUNT REGULATOR/

ERROR AMPLIFIER

V

C

SHUTDOWN/

AUTO-RESTART

­+

5.7 V

5.7 V

4.7 V

+

-

POWER-UP

RESET

0

INTERNAL
SUPPLY

1

DRAIN

÷ 8

EXTERNALLY

TRIGGERED
SHUTDOWN

I

FB

OSCILLATOR

R

E

D

MAX

CLOCK

SAW

THERMAL

SHUTDOWN

COMPARATOR

Figure 2. Functional Block Diagram.

Pin Functional Description

­+

PWM

RSQ

Q

SRQ

+

-

V

I

LIMIT

CONTROLLED

TURN-ON

GATE

DRIVER

LEADING

Q

EDGE

BLANKING

MINIMUM

ON-TIME

DELAY

SOURCE

PI-1746-011796

DRAIN Pin:

Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched high­voltage current source. Internal current sense point.

CONTROL Pin:

Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. Trigger input for latching
shutdown. It is also used as the supply bypass and auto-restart/
compensation capacitor connection point.

SOURCE Pin:

Output MOSFET source connection. Primary-side circuit
common, power return, and reference point.

D

2

7/96

DRAIN
SOURCE (TAB)

CONTROL

TO-220/3 (YO3A)

PI-1065A-110194

Figure 3. Pin Configuration.

TOP200-4/14

TOPSwitch

Family Functional Description

TOPSwitch is a self biased and protected
linear control current-to-duty cycle
converter with an open drain output.
High efficiency is achieved through the
use of CMOS and integration of the
maximum number of functions possible.
CMOS significantly reduces bias
currents as compared to bipolar or
discrete solutions. Integration eliminates
external power resistors used for current
sensing and/or supplying initial start-up
bias current.

During normal operation, the internal
output MOSFET duty cycle linearly
decreases with increasing CONTROL
pin current as shown in Figure 4. To
implement all the required control, bias,
and protection functions, the DRAIN
and CONTROL pins each perform
several functions as described below.
Refer to Figure 2 for a block diagram
and Figure 6 for timing and voltage
waveforms of the TOPSwitch integrated
circuit.

Control Voltage Supply

CONTROL pin voltage VC is the supply
or bias voltage for the controller and
driver circuitry. An external bypass
capacitor closely connected between the
CONTROL and SOURCE pins is
required to supply the gate drive current.
The total amount of capacitance
connected to this pin (CT) also sets the
auto-restart timing as well as control
loop compensation. VC is regulated in
either of two modes of operation.
Hysteretic regulation is used for initial
start-up and overload operation. Shunt
regulation is used to separate the duty
cycle error signal from the control circuit
supply current. During start-up, V
current is supplied from a high-voltage
switched current source connected
internally between the DRAIN and
CONTROL pins. The current source
provides sufficient current to supply the
control circuitry as well as charge the
total external capacitance (CT).

Auto-restart

I

D

MAX

B

Duty Cycle (%)

D

MIN

I

2.5 6.5 45

CD1

Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.

IC

V

DRAIN

C

5.7 V



4.7 V

V

IN

Charging C

0

0

T

Off

(a)

IC

Charging C

5.7 V



4.7 V

V

C

0

C

DRAIN

V

IN

0

T

Off

Switching Switching

(b)

CT is the total external capacitance

connected to the CONTROL pin

Slope = PWM Gain

-16%/mA

IC (mA)

Switching

I



CD1

Discharging C

95%

Off

T

8 Cycles



Discharging C

5%

PI-1691-112895

I



CD2

T

Off

PI-1124A-060694

Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.

7/96

D

3

TOP200-4/14

TOPSwitch

Family Functional Description (cont.)

The first time VC reaches the upper
threshold, the high-voltage current
source is turned off and the PWM
modulator and output transistor are
activated, as shown in Figure 5(a).
During normal operation (when the
output voltage is regulated) feedback
control current supplies the VC supply
current. The shunt regulator keeps VC at
typically 5.7 V by shunting CONTROL
pin feedback current exceeding the
required DC supply current through the
PWM error signal sense resistor RE. The
low dynamic impedance of this pin (ZC)
sets the gain of the error amplifier when
used in a primary feedback
configuration. The dynamic impedance
of the CONTROL pin together with the
external resistance and capacitance
determines the control loop
compensation of the power system.

If the CONTROL pin external
capacitance (CT) should discharge to the
lower threshold, then the output
MOSFET is turned off and the control
circuit is placed in a low-current standby
mode. The high-voltage current source
is turned on and charges the external
capacitance again. Charging current is
shown with a negative polarity and
discharging current is shown with a
positive polarity in Figure 6. The
hysteretic auto-restart comparator keeps
VC within a window of typically 4.7 to

5.7 V by turning the high-voltage current

source on and off as shown in Figure
5(b). The auto-restart circuit has a divide­by-8 counter which prevents the output
MOSFET from turning on again until
eight discharge-charge cycles have
elapsed. The counter effectively limits
TOPSwitch power dissipation by
reducing the auto-restart duty cycle to
typically 5%. Auto-restart continues to
cycle until output voltage regulation is
again achieved.

Bandgap Reference

All critical TOPSwitch internal voltages
are derived from a temperature­compensated bandgap reference. This
reference is also used to generate a
temperature-compensated current source
which is trimmed to accurately set the
oscillator frequency and MOSFET gate
drive current.

Oscillator

The internal oscillator linearly charges
and discharges the internal capacitance
between two voltage levels to create a
sawtooth waveform for the pulse width
modulator. The oscillator sets the pulse
width modulator/current limit latch at
the beginning of each cycle. The nominal
frequency of 100 kHz was chosen to
minimize EMI and maximize efficiency
in power supply applications. Trimming
of the current reference improves
oscillator frequency accuracy.

Pulse Width Modulator

The pulse width modulator implements
a voltage-mode control loop by driving
the output MOSFET with a duty cycle
inversely proportional to the current
flowing into the CONTROL pin. The
error signal across RE is filtered by an
RC network with a typical corner
frequency of 7 kHz to reduce the effect
of switching noise. The filtered error
signal is compared with the internal
oscillator sawtooth waveform to generate
the duty cycle waveform. As the control
current increases, the duty cycle
decreases. A clock signal from the
oscillator sets a latch which turns on the
output MOSFET. The pulse width
modulator resets the latch, turning off
the output MOSFET. The maximum
duty cycle is set by the symmetry of the
internal oscillator. The modulator has a
minimum ON-time to keep the current
consumption of the TOPSwitch
independent of the error signal. Note
that a minimum current must be driven
into the CONTROL pin before the duty
cycle begins to change.

Gate Driver

The gate driver is designed to turn the
output MOSFET on at a controlled rate
to minimize common-mode EMI. The
gate drive current is trimmed for
improved accuracy.

Error Amplifier

The shunt regulator can also perform the
function of an error amplifier in primary
feedback applications. The shunt
regulator voltage is accurately derived
from the temperature compensated
bandgap reference. The gain of the error
amplifier is set by the CONTROL pin
dynamic impedance. The CONTROL
pin clamps external circuit signals to the
VC voltage level. The CONTROL pin
current in excess of the supply current is
separated by the shunt regulator and
flows through RE as the error signal.

Cycle-By-Cycle Current Limit

The cycle by cycle peak drain current
limit circuit uses the output MOSFET
ON-resistance as a sense resistor. A
current limit comparator compares the
output MOSFET ON-state drain-source
voltage, V
High drain current causes V

with a threshold voltage.

DS(ON),

DS(ON)

to
exceed the threshold voltage and turns
the output MOSFET off until the start of
the next clock cycle. The current limit
comparator threshold voltage is
temperature compensated to minimize
variation of the effective peak current
limit due to temperature related changes
in output MOSFET R

DS(ON)

.

The leading edge blanking circuit inhibits
the current limit comparator for a short
time after the output MOSFET is turned
on. The leading edge blanking time has
been set so that current spikes caused by
primary-side capacitances and
secondary-side rectifier reverse recovery
time will not cause premature
termination of the switching pulse.

D

4

7/96

V

IN

DRAIN

V

OUT

I

OUT

TOP200-4/14

V

IN

0

0

0

12 12 81

8

••• •••

V

C

0

12

I

0

C

1 2

Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, (3) Latching Shutdown, and (4) Power Down Reset.

Shutdown/Auto-restart

To minimize TOPSwitch power
dissipation, the shutdown/auto-restart
circuit turns the power supply on and off
at a duty cycle of typically 5% if an out
of regulation condition persists. Loss of
regulation interrupts the external current

812 81

••• •••

removing and restoring input power, or
momentarily pulling the CONTROL pin
below the power-up reset threshold resets
the latch and allows TOPSwitch to
resume normal power supply operation.
VC is regulated in hysteretic mode when

the power supply is latched off.
into the CONTROL pin. VC regulation
changes from shunt mode to the
hysteretic auto-restart mode described
above. When the fault condition is
removed, the power supply output
becomes regulated, VC regulation returns
to shunt mode, and normal operation of
the power supply resumes.

Overtemperature Protection

Temperature protection is provided by a

precision analog circuit that turns the

output MOSFET off when the junction

temperature exceeds the thermal

shutdown temperature (typically 145°C).

Activating the power-up reset circuit by

removing and restoring input power or

Latching Shutdown

The output overvoltage protection latch
is activated by a high-current pulse into
the CONTROL pin. When set, the latch
turns off the TOPSwitch output.
Activating the power-up reset circuit by

momentarily pulling the CONTROL pin

below the power-up reset threshold resets

the latch and allows TOPSwitch to

resume normal power supply operation.

VC is regulated in hysteretic mode when

the power supply is latched off.

45 mA

High-voltage Bias Current Source

This current source biases TOPSwitch
from the DRAIN pin and charges the
CONTROL pin external capacitance
(CT) during start-up or hysteretic
operation. Hysteretic operation occurs
during auto-restart and latched
shutdown. The current source is switched
on and off with an effective duty cycle of
approximately 35%. This duty cycle is
determined by the ratio of CONTROL
pin charge (IC) and discharge currents
(I

CD1

and I

). This current source is

CD2

turned off during normal operation when
the output MOSFET is switching.

V

C(reset)

143

PI-1119-110194

7/96

D

5

TOP200-4/14

General Circuit Operation

Primary Feedback Regulation

The circuit shown in Figure 7 is a simple
5 V, 5 W bias supply using the TOP200.
This universal input flyback power
supply employs primary-side regulation
from a transformer bias winding. This
approach is best for low-cost applications
requiring isolation and operation within
a narrow range of load variation. Line
and load regulation of ±5% or better can
be achieved from 10% to 100% of rated
load.

Voltage feedback is obtained from the
transformer (T1) bias winding, which
eliminates the need for optocoupler and
secondary-referenced error amplifier.
High-voltage DC is applied to the
primary winding of T1. The other side
of the transformer primary is driven by

the integrated high-voltage MOSFET

transistor within the TOP200 (U1). The

circuit operates at a switching frequency

of 100 kHz, set by the internal oscillator

of the TOP200. The clamp circuit

implemented by VR1 and D1 limits the

leading-edge voltage spike caused by

transformer leakage inductance to a safe

value. The 5 V power secondary winding

is rectified and filtered by D2, C2, C3,

and L1 to create the 5 V output voltage.

The output of the T1 bias winding is

rectified and filtered by D3, R1, and C5.

The voltage across C5 is regulated by

U1, and is determined by the 5.7 V

internal shunt regulator at the

CONTROL pin of U1. When the

rectified bias voltage on C5 begins to

exceed the shunt regulator voltage,

current will flow into the control pin.
Increasing control pin current decreases
the duty cycle until a stable operating
point is reached. The output voltage is
proportional to the bias voltage by the
turns ratio of the output to bias windings.
C5 is used to bypass the CONTROL pin.
C5 also provides loop compensation for
the power supply by shunting AC
currents around the CONTROL pin
dynamic impedance, and also determines
the auto-restart frequency during start­up and auto-restart conditions. See DN­8 for more information regarding the use
of the TOP200 in bias supplies.

D2

1N5822

VR1

1N4764

D1

UF4005

C2

330 µF

25 V

D3

1N4148

DC

INPUT

C5

47 µF

DRAIN

SOURCE

CONTROL

U1

TOP200YAI

Figure 7. Schematic Diagram of a Minimum Parts Count 5 V, 5 W Bias Supply Utilizing the TOP200.

D

6

7/96

T1

R1

22 Ω

L1

(Bead)

5 V

C3

150 µF

25 V

RTN

CIRCUIT PERFORMANCE:

Load Regulation - ±4%

(10% to 100%)

Line Regulation - ±1.5%

95 to 370 V DC

Ripple Voltage ±25 mV

PI-1749-012296

TOP200-4/14

22 mH

L



N

J1

L2

C6

0.1 µF
F1

3.15 A

BR1

400 V

DRAIN

SOURCE

CONTROL

U1

TOP202YAI

C1
33 µF
400 V

D2

UG8BT

VR1

P6KE150

D1

UF4005

C5

47µF

ST202A REFERENCE DESIGN BOARD

T1



C2

680 µF

25 V

D3

1N4148

R1

39 Ω

U2

NEC2501

C4

0.1 µF

R2

68 Ω

VR2

1N5234B

6.2 V

L1

3.3 µH

C3

120 µF

25 V

CIRCUIT PERFORMANCE:

Line Regulation - ±0.5%

C7

1 nF

Y1

(85-265 VAC)

Load Regulation - ±1%

(10 -100%)

Ripple Voltage ± 50 mV

Meets CISPR-22 Class B

7.5 V

RTN

PI-1695-112895

Figure 8. Schematic Diagram of a 15 W Universal Input Power Supply Utilizing the TOP202 and Simple Optocoupler Feedback.

Simple Optocoupler Feedback

The circuit shown in Figure 8 is a 7.5 V,
15 W secondary regulated flyback power
supply using the TOP202 that will
operate from 85 to 265 VAC input
voltage. Improved output voltage
accuracy and regulation over the circuit
of Figure 7 is achieved by using an
optocoupler and secondary referenced
Zener diode. The general operation of
the power stage of this circuit is the same
as that described for Figure 7.

The input voltage is rectified and filtered
by BR1 and C1. L2, C6 and C7 reduce
conducted emission currents. The bias
winding is rectified and filtered by D3
and C4 to create a typical 11 V bias
voltage. Zener diode (VR2) voltage
together with the forward voltage of the
LED in the optocoupler U2 determine
the output voltage. R1, the optocoupler

current transfer ratio, and the TOPSwitch
control current to duty cycle transfer
function set the DC control loop gain.
C5 together with the control pin dynamic
impedance and capacitor ESR establish
a control loop pole-zero pair. C5 also
determines the auto-restart frequency
and filters internal gate drive switching
currents. R2 and VR2 provide minimum
current loading when output current is
low. See DN-11 for more information
regarding the use of the TOP202 in a
low-cost, 15 W universal power supply.

Accurate Optocoupler Feedback

The circuit shown in Figure 9 is a highly
accurate, 15 V, 30 W secondary­regulated flyback power supply that will
operate from 85 to 265 VAC input
voltage. A TL431 shunt regulator
directly senses and accurately regulates
the output voltage. The effective output

voltage can be fine tuned by adjusting
the resistor divider formed by R4 and
R5. Other output voltages are possible
by adjusting the transformer turns ratios
as well as the divider ratio.

The general operation of the input and
power stages of this circuit are the same
as that described for Figures 7 and 8. R3
and C5 tailor frequency response. The
TL431 (U2) regulates the output voltage
by controlling optocoupler LED current
(and TOPSwitch duty cycle) to maintain
an average voltage of 2.5 V at the TL431
input pin. Divider R4 and R5 determine
the actual output voltage. C9 rolls off
the high frequency gain of the TL431 for
stable operation. R1 limits optocoupler
LED current and determines high
frequency loop gain. For more
information, refer to application note
AN-14.

7/96

D

7

TOP200-4/14

33 mH

L



N

J1

L2

C6

0.1 µF
F1

3.15 A

BR1

400 V

P6KE200

C1
47 µF
400 V

BYV26C

CIRCUIT PERFORMANCE:

Line Regulation - ±0.2%

(85-265 VAC)

Load Regulation - ±0.2%

(10-100%)

Ripple Voltage ±150 mV

Meets CISPR-22 Class B

DRAIN

SOURCE

CONTROL

U1

TOP204YAI

VR1

D1

D2

MUR610CT

L1

3.3 µH

15 V

C2

1000 µF



35 V

R2
200 Ω
1/2 W

C3

120 µF

25 V

RTN

D3

1N4148

U2

NEC2501

C4

0.1 µF

T1

R1

510 Ω

R4

49.9 kΩ
C9

0.1 µF

C5

47 µF

R3

6.2 Ω

U3

TL431

R5

10 kΩ

C7

1 nF

Y1

ST204A REFERENCE DESIGN BOARD

Figure 9. Schematic Diagram of a 30 W Universal Input Power Supply Utilizing the TOP204 and Accurate Optocoupler Feedback.

V

o

C4

47 µF

RTN

AC

IN

EMI

FILTER

BR1

400 V

TYPICAL PERFORMANCE:

Power Factor = 0.98

THD = 8%



C1

220 nF

400 V

DRAIN

SOURCE

CONTROL

U1

TOP202YAI

R1

200 kΩ

L1

500 µH

D2

1N4935

C2

4.7 µF

MUR460

IN5386B

IN5386B

R2

200 Ω

R10

6.8 kΩ

D1

VR1

VR2



R3

3 kΩ

C3

220 µF

PI-1696-112895

PI-1750-012296

Figure 10. Schematic Diagram of a 65 W 230 VAC Input Boost Power Factor Correction Circuit Utilizing the TOP202.

D

8

7/96

General Circuit Operation (cont.)

TOP200-4/14

Boost PFC Pre-regulator

TOPSwitch can also be used as a fixed
frequency, discontinuous mode boost
pre-regulator to improve Power Factor
and reduce Total Harmonic Distortion
(THD) for applications such as power
supplies and electronic ballasts. The
circuit shown in Figure 10 operates from
230 VAC and delivers 65 W at 410 VDC
with typical Power Factor over 0.98 and
THD of 8%. Bridge Rectifier BR1 full
wave rectifies the AC input voltage. L1,
D1, C4, and TOPSwitch make up the
boost power stage. D2 prevents reverse
current through the TOPSwitch body
diode due to ringing voltages generated

Key Application Issues

Keep the SOURCE pin length very short.
Use a Kelvin connection to the SOURCE
pin for the CONTROL pin bypass
capacitor. Use single point grounding
techniques at the SOURCE pin as shown
in Figure 11.

Minimize peak voltage and ringing on
the DRAIN voltage at turn-off. Use a
Zener or TVS Zener diode to clamp the
DRAIN voltage.

Do not plug the TOPSwitch device into
a “hot” IC socket during test. External
CONTROL pin capacitance may deliver
a surge current sufficient to trigger the
shutdown latch which turns the
TOPSwitch off.

by the boost inductance and parasitic
capacitance. R1 generates a pre­compensation current proportional to
the instantaneous rectified AC input
voltage which directly varies the duty
cycle. C2 filters high frequency
switching currents while having no
filtering effect on the line frequency pre­compensation current. R2 decouples
the pre-compensation current from the
large filter capacitor C3 to prevent an
averaging effect which would increase
total harmonic distortion. C1 filters
high frequency noise currents which
could cause errors in the pre­compensation current.

Under some conditions, externally
provided bias or supply current driven
into the CONTROL pin can hold the
TOPSwitch in one of the 8 auto-restart
cycles indefinitely and prevent starting.
Shorting the CONTROL pin to the
SOURCE pin will reset the TOPSwitch.
To avoid this problem when doing bench
evaluations, it is recommended that the
VC power supply be turned on before the
DRAIN voltage is applied.

CONTROL pin currents during auto­restart operation are much lower at low
input voltages (< 20 V) which increases
the auto-restart cycle period (see the I
vs. Drain Voltage Characteristic curve).

When power is first applied, C3 charges
to typically 5.7 volts before TOPSwitch
starts. C3 then provides TOPSwitch
bias current until the output voltage
becomes regulated. When the output
voltage becomes regulated, series
connected Zener diodes VR1 and VR2
begin to conduct, drive current into the
TOPSwitch control pin, and directly
control the duty cycle. C3 together with
R3 perform low pass filtering on the
feedback signal to prevent output line
frequency ripple voltage from varying
the duty cycle. For more information,
refer to Design Note DN-7.

Short interruptions of AC power may
cause TOPSwitch to enter the 8-count
auto-restart cycle before starting again.
This is because the input energy storage
capacitors are not completely discharged
and the CONTROL pin capacitance has
not discharged below the pin internal
power-up reset voltage.

In some cases, minimum loading may
be necessary to keep a lightly loaded or
unloaded output voltage within the
desired range due to the minimum ON­time.

For additional applications information

C

regarding the TOPSwitch family, refer
to AN-14.

Bias/Feedback

Return

C

Bias/Feedback 

Input

TOP VIEW

Figure 11. Recommended TOPSwitch Layout.

S

D

Capacitor

High Voltage 

Return

Bypass

Kelvin-connected

bypass capacitor

and/or compensation network

PC Board

Bias/Feedback Input

Bias/Feedback Return

CONTROL

SOURCE

Do not bend SOURCE pin
Keep it short

DRAIN

Bend DRAIN pin
forward if needed
for creepage

High-voltage Return

PI-1240-110194

D

9

7/96

TOP200-4/14

ABSOLUTE MAXIMUM RATINGS

DRAIN Voltage ............................................ -0.3 to 700 V

CONTROL Voltage ..................................... - 0.3 V to 9 V

Storage Temperature ......................................-65 to 125°C

Operating Junction Temperature
Lead Temperature

(3)

................................................. 260°C

(2)

.................-40 to 150°C

Thermal Impedance (θJA) ...................................... 70°C/W

Thermal Impedance (θJC)

1. Unless noted, all voltages referenced to SOURCE,
TA = 25°C.

2. Normally limited by internal circuitry.

3. 1/16" from case for 5 seconds.

4. Measured at tab closest to plastic interface.

(1)

(4)

.................................... 2 °C/W

Conditions

(Unless Otherwise Specified)

Parameter Symbol See Figure 14 Units

SOURCE = 0 V

Tj = -40 to 125°C

Min Typ Max

CONTROL FUNCTIONS

Output
Frequency

Maximum
Duty Cycle

f

DC

OSC

MAX

IC = 4 mA, Tj = 25˚C

IC = I

+ 0.5 mA, See Figure 12

CD1

90 100 110

64 67 70

kHz

%

Minimum
Duty Cycle

DC

MIN

PWM
Gain

PWM Gain
Temperature Drift

External
Bias Current

Dynamic
Impedance

Dynamic Impedance

I

B

Z

C

Temperature Drift

SHUTDOWN/AUTO-RESTART

CONTROL Pin
Charging Current

I

C

Charging Current
Temperature Drift

IC = 10 mA, TOP200/1/2
See Figure 12 TOP203/4/14

IC = 4 mA, Tj = 25˚C

See Figure 4

See Note 1

See Figure 4

IC = 4 mA, Tj = 25˚C

See Figure 13

VC = 0 V

Tj = 25˚C

VC = 5 V

See Note 1

1.0 1.8 3.0

1.0 2.0 3.5

-11 -16 -21

-0.05

1.5 2.5 4

10 15 22

0.18

-2.4 -1.9 -1.2

-2 -1.5 -0.8

0.4

%

%/mA

%/mA/˚C

mA

Ω

%/˚C

mA

%/˚C

Auto-restart
Threshold Voltage

D

10

7/96

V

C(AR)

S1 open

5.7

V

TOP200-4/14

Conditions

(Unless Otherwise Specified)

Parameter Symbol See Figure 14 Units

SOURCE = 0 V

Tj = -40 to 125°C

SHUTDOWN/AUTO-RESTART (cont.)

Min Typ Max

UV Lockout
Threshold Voltage

Auto-restart
Hysteresis Voltage

Auto-restart
Duty Cycle

Auto-restart
Frequency

CIRCUIT PROTECTION

Self-protection
Current Limit

I

LIMIT

S1 open

S1 open

S1 open

S1 open

TOP200

di/dt = 80 mA/µs, Tj = 25˚C

TOP201

di/dt = 170 mA/µs, Tj = 25˚C

TOP202

di/dt = 250 mA/µs, Tj = 25˚C

TOP203

di/dt = 330 mA/µs, Tj = 25˚C

4.7

0.6 1.0

58

1.2

0.415 0.585

0.830 1.17

1.25 1.75

1.50 2.10

V

V

%

Hz

A

Leading Edge
Blanking Time

Current Limit
Delay

Thermal Shutdown
Temperature

Latched Shutdown
Trigger Current

Power-up Reset
Threshold Voltage

t

t

I

V

C(RESET)

LEB

ILD

SD

TOP214

di/dt = 420 mA/µs, Tj = 25˚C

TOP204

di/dt = 500 mA/µs, Tj = 25˚C

IC = 4 mA

IC = 4 mA

IC = 4 mA

See Figure 13

S2 open

1.88 2.63

2.25 3.15

150

100

125 145

25 45 75

2.0 3.3 4.2

7/96

ns

ns

°C

mA

V

D

11

TOP200-4/14

Conditions

(Unless Otherwise Specified)

Parameter Symbol See Figure 14 Units

SOURCE = 0 V

Tj = -40 to 125°C

OUTPUT

Min Typ Max

ON-State
Resistance

OFF-State
Current

Breakdown
Voltage

Rise
Time

R

I

BV

DS(ON)

DSS

DSS

t

r

TOP200 Tj = 25°C

ID = 50 mA Tj = 100°C

TOP201 Tj = 25°C

ID = 100 mA Tj = 100°C

TOP202 Tj = 25°C

ID = 150 mA Tj = 100°C

TOP203 Tj = 25°C

ID = 200 mA Tj = 100°C

TOP214 Tj = 25°C

ID = 250 mA Tj = 100°C

TOP204 Tj = 25°C

ID = 300 mA Tj = 100°C

Device in Latched Shutdown

IC = 4 mA, VDS = 560 V, TA = 125°C

Device in Latched Shutdown

IC = 4 mA, ID = 500 µA, TA = 25°C

Measured With

Figure 8 Schematic

700

15.6 18.0

25.7 29.7

7.8 9.0

12.9 14.9

5.2 6.0

8.6 9.9

3.9 4.5

6.4 7.5

3.1 3.6

5.2 6.0

2.6 3.0

4.3 5.0

500

100

Ω

µA

V

ns

Fall
Time

SUPPLY

DRAIN Supply
Voltage

Shunt Regulator
Voltage

Shunt Regulator
Temperature Drift

CONTROL Supply/
Discharge Current

D

12

7/96

t

V

C(SHUNT)

I

CD1

I

CD2

Measured With

f

Output TOP200/1/2
MOSFET enabled TOP203/4/14

Figure 8 Schematic

See Note 2

IC = 4 mA

Output MOSFET Disabled

50

36

5.5 5.8 6.1

±50

0.6 1.2 1.6

0.7 1.4 1.8

0.5 0.8 1.1

ns

V

V

ppm/˚C

mA

TOP200-4/14

NOTES:

1. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.

2. It is possible to start up and operate

TOPSwitch

at DRAIN voltages well below 36 V. However, the CONTROL pin
charging current is reduced, which affects start-up time and auto-restart frequency and duty cycle. Refer to the
characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low voltage operation
characteristics.

TYPICAL CONTROL PIN I-V CHARACTERISTIC

120

100

t

HV

DRAIN

VOLTAGE

0 V

90%

2

t

1

90%

t1

DC =

t

2

10%

PI-1215-091794

80

60

40

20

CONTROL Pin Current (mA)

0

Latched Shutdown

Dynamic



=

1

Slope

Trigger Current (45 mA)

Impedance

0246810

CONTROL Pin Voltage (V)

PI-1216-091794

Figure 12. TOPSwitch Duty Cycle Measurement. Figure 13. TOPSwitch CONTROL Pin I-V Characteristic.

DRAIN

SOURCE

CONTROL

TOPSwitch

0.1 µF

470 Ω

5 W

S1

47 µF 0-50 V

S2

470 Ω

40 V

NOTE: This test circuit is not applicable for current limit or output characteristic measurements.

PI-1126-041994

Figure 14. TOPSwitch General Test Circuit.

7/96

D

13

TOP200-4/14

1.2

1.0

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

FREQUENCY vs. TEMPERATURE

PI-1123A-060794

Output Frequency

(Normalized to 25°C)

BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS

The following precautions should be
followed when testing TOPSwitch by
itself outside of a power supply. The
schematic shown in Figure 14 is
suggested for laboratory testing of
TOPSwitch.

The control pin voltage will be oscillating
at a low frequency from 4.7 to 5.7 V and
the DRAIN is turned on every eighth
cycle of the CONTROL pin oscillation.
If the CONTROL pin power supply is
turned on while in this auto-restart mode,

there is only a 12.5% chance that the
When the DRAIN supply is turned on,
the part will be in the auto-restart mode.

control pin oscillation will be in the

correct state (DRAIN active state) so

Typical Performance Characteristics

BREAKDOWN vs. TEMPERATURE

1.1

PI-176B-051391

1.0

that the continuous DRAIN voltage
waveform may be observed. It is
recommended that the VC power supply be
turned on first and the DRAIN power supply
second if continuous drain voltage
waveforms are to be observed. The 12.5%
chance of being in the correct state is due to
the 8:1 counter.

(Normalized to 25°C)

Breakdown Voltage (V)

0.9

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

CURRENT LIMIT vs. TEMPERATURE

1.2

1.0

14

0.8

0.6

0.4

Current Limit

(Normalized to 25°C)

0.2

0

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

D
7/96

PI-1125-041494

IC vs. DRAIN VOLTAGE

2

VC = 5 V

1.6

1.2

0.8

CONTROL Pin

0.4

Charging Current (mA)

0

0 20406080100

Drain Voltage (V)

PI-1145-103194

Typical Performance Characteristics (cont.)

TOP200-4/14

OUTPUT CHARACTERISTICS

3

TCASE=25˚C
TCASE=100˚C


2

1

Drain Current (A)

0

0

246810

Drain Voltage (V)

Scaling Factors:

TOP204 1.00
TOP214 0.83
TOP203 0.67
TOP202 0.50
TOP201 0.33
TOP200 0.17

C



PI-1748-012296



1000

100

DRAIN Capacitance (pF)

10

DRAIN CAPACITANCE POWER

500

Scaling Factors:



400

300

TOP204 1.00
TOP214 0.83
TOP203 0.67
TOP202 0.50
TOP201 0.33
TOP200 0.17

vs. DRAIN VOLTAGE

OSS

Scaling Factors:



TOP204 1.00
TOP214 0.83
TOP203 0.67
TOP202 0.50
TOP201 0.33
TOP200 0.17

0 400200 600

DRAIN Voltage (V)

PI-1222-102194

PI-1223-110294

200

Power (mW)

100

0

0 200 400 600

DRAIN Voltage (V)

7/96

D

15

TOP200-4/14

Y03A Plastic TO-220/3

DIM

A
B
C
D
E

F
G
H

J
K

L
M
N
O
P

inches



* LEADS AND TAB ARE 
SOLDER PLATED


.460-.480
.400-.415
.236-.260

.240 - REF.

.520-.560
.028-.038
.045-.055
.090-.110
.165-.185
.045-.055
.095-.115
.015-.020
.705-.715
.146-.156
.103-.113





mm



11.68-12.19

10.16-10.54

5.99-6.60

6.10 - REF.

13.21-14.22
.71-.97

1.14-1.40

2.29-2.79

4.19-4.70

1.14-1.40

2.41-2.92
.38-.51

17.91-18.16

3.71-3.96

2.62-2.87

B

P

C

O

A

N

D

E

F

G

H

J

K

Notes:

1. Package dimensions conform to
JEDEC specification TO-220 AB for
standard flange mounted, peripheral
lead package; .100 inch lead spacing
(Plastic) 3 leads (issue J, March 1987) 

2. Controlling dimensions are inches. 

3. Pin numbers start with Pin 1, and
continue from left to right when 
viewed from the top.

4. Dimensions shown do not include

L

M

mold flash or other protrusions. Mold
flash or protrusions shall not exceed
.006 (.15 mm) on any side.

5. Position of terminals to be
measured at a position .25 (6.35 mm)
from the body.

6. All terminals are solder plated.

PI-1848-050696



Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.

PI Logo and

TOPSwitch

are registered trademarks of Power Integrations, Inc.

©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086

WORLD HEADQUARTERS

Power Integrations, Inc.
477 N. Mathilda Avenue
Sunnyvale, CA 94086
USA
Main: 408•523•9200
Customer Service:
Phone: 408•523•9265
Fax: 408•523•9365

JAPAN

Power Integrations, K.K.
Keihin-Tatemono 1st Bldg.
12-20 Shin-Yokohoma 2-Chome, Kohoku-ku
Yokohama-shi, Kanagawa 222 Japan
Phone: 81•(0)•45•471•1021
Fax: 81•(0)•45•471•3717

AMERICAS

For Your Nearest Sales/Rep Office
Please Contact Customer Service
Phone: 408•523•9265
Fax: 408•523•9365

ASIA & OCEANIA

For Your Nearest Sales/Rep Office
Please Contact Customer Service
Phone: 408•523•9265
Fax: 408•523•9365

EUROPE & AFRICA

Power Integrations (Europe) Ltd.
Mountbatten House
Fairacres
Windsor SL4 4LE
United Kingdom
Phone: 44•(0)•1753•622•208
Fax: 44•(0)•1753•622•209

APPLICATIONS HOTLINE

World Wide 408•523•9260

APPLICATIONS FAX

Americas 408•523•9361
Europe/Africa
44•(0)•1753•622•209
Japan 81•(0)•45•471•3717
Asia/Oceania 408•523•9364

16

D
7/96