Datasheet TNY275PG Specification

Page 1
TNY274-280 TinySwitch-III Family
Energy-Efcient, Off-Line Switcher with Enhanced Flexibility and Extended Power Range
Product Highlights
Lowest System Cost with Enhanced Flexibility
Simple ON/OFF control, no loop compensation needed
Selectable current limit through BP/M capacitor value
Higher current limit extends peak power or, in open
frame applications, maximum continuous power
Lower current limit improves efficiency in enclosed
adapters/chargers
Allows optimum TinySwitch-III choice by swapping
devices with no other circuit redesign
Tight I
ON-time extension – extends low line regulation range/hold-up
Self-biased: no bias winding or bias components
Frequency jittering reduces EMI filter costs
Pin-out simplifies heatsinking to the PCB
SOURCE pins are electrically quiet for low EMI
Enhanced Safety and Reliability Features
Accurate hysteretic thermal shutdown protection with
Improved auto-restart delivers <3% of maximum power in
Output overvoltage shutdown with optional Zener
Line undervoltage detect threshold set using a single optional
Very low component count enhances reliability and enables
High bandwidth provides fast turn on with no overshoot and
Extended creepage between DRAIN and all other pins improves
2
f parameter tolerance reduces system cost
Maximizes MOSFET and magnetics power delivery
Minimizes max overload power, reducing cost of
transformer, primary clamp & secondary components
time to reduce input bulk capacitance
automatic recovery eliminates need for manual reset
short-circuit and open loop fault conditions
resistor
single-sided printed circuit board layout
excellent transient load response
field reliability
++
DC
Output
Wide-Range
High-Voltage
DC Input
TinySwitch-III
Figure 1. Typical Standby Application.
D
EN/UV
BP/M
S
PI-4095-082205
Output Power Table
230 VAC ± 15% 85-265 VAC
Product
TNY274P/G 6 W 11 W 5 W 8.5 W
TNY275P/G 8.5 W 15 W 6 W 11.5 W
TNY276P/G 10 W 19 W 7 W 15 W
TNY277P/G 13 W 23.5 W 8 W 18 W
TNY278P/G 16 W 28 W 10 W 21.5 W
TNY279P/G 18 W 32 W 12 W 25 W
TNY280P/G 20 W 36.5 W 14 W 28.5 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient. Use of an external heat sink will increase power capability.
2. Minimum peak power capability in any design or minimum continuous power in an open frame design (see Key Applications Considerations).
3. Packages: P: DIP-8C, G: SMD-8C. See Part Ordering Information.
Adapter
Peak or
Open
Frame
Adapter
Peak or
Open
Frame
EcoSmart™– Extremely Energy Efficient
Easily meets all global energy efficiency regulations
No-load <150 mW at 265 VAC without bias winding, <50 mW
with bias winding
ON/OFF control provides constant efficiency down to very light
loads – ideal for mandatory CEC regulations and 1 W PC standby requirements
Description
TinySwitch™-III incorporates a 700 V power MOSFET, oscillator, high-voltage switched current source, current limit (user selectable) and thermal shutdown circuitry. The IC family uses an ON/OFF control scheme and offers a design flexible solution with a low system cost and extended power capability.
Applications
Chargers/adapters for cell/cordless phones, PDAs, digital
cameras, MP3/portable audio, shavers, etc.
PC Standby and other auxiliary supplies
DVD/PVR and other low power set top decoders
Supplies for appliances, industrial systems, metering, etc.
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This Product is Covered by Patents and/or Pending Patent Applications.
Page 2
TNY274-280
PI-4077-072115
CLOCK
OSCILLATOR
5.85 V
4.9 V
SOURCE
(S)
SRQ
DC
MAX
BYPASS/
MULTI-FUNCTION
(BP/M)
+
-
V
I
LIMIT
FAULT
PRESENT
CURRENT LIMIT COMPARATOR
ENABLE
LEADING
EDGE
BLANKING
THERMAL
SHUTDOWN
+
-
DRAIN
(D)
REGULATOR
5.85 V
BYPASS PIN UNDER-VOLTAGE
1.0 V + V
T
ENABLE/
UNDER-
VOLTAGE
(EN/UV)
Q
115 µA 25 µA
LINE UNDER-VOLTAGE
RESET
AUTO-
RESTART
COUNTER
JITTER
1.0 V
6.4 V
BYPASS
CAPACITOR
SELECT AND
CURRENT
LIMIT STATE
MACHINE
OVP
LATCH
PI-4078-080905
D
S
BP/M
S
S
EN/UV
P Package (DIP-8C)
G Package (SMD-8C)
8
5
7
1
4
2
S
6
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
This pin is the power MOSFET drain connection. It provides internal operating current for both start-up and steady-state operation.
BYPASS/MULTI-FUNCTION (BP/M) Pin:
This pin has multiple functions:
1. It is the connection point for an external bypass capacitor for
2. It is a mode selector for the current limit value, depending on
3. It provides a shutdown function. When the current into the
the internally generated 5.85 V supply.
the value of the capacitance added. Use of a 0.1 mF capacitor results in the standard current limit value. Use of a 1 mF capacitor results in the current limit being reduced to that of the next smaller device size. Use of a 10 mF capacitor results in the current limit being increased to that of the next larger device size for TNY275-280.
bypass pin exceeds I BP/M voltage drops below 4.9 V, during a power down. This can be used to provide an output overvoltage function with a Zener connected from the BP/M pin to a bias winding supply.
, the device latches off until the
SD
Figure 3. Pin Configuration.
ENABLE/UNDERVOLTAGE (EN/UV) Pin:
This pin has dual functions: enable input and line undervoltage sense. During normal operation, switching of the power MOSFET is controlled by this pin. MOSFET switching is terminated when a current greater than a threshold current is drawn from this pin. Switching resumes when the current being
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TNY274-280
600
Time (µs)
PI-2741-041901
50
40
30
20
10
pulled from the pin drops to less than a threshold current. A modulation of the threshold current reduces group pulsing. The threshold current is between 75 mA and 115 mA.
The EN/UV pin also senses line undervoltage conditions through an external resistor connected to the DC line voltage. If there is no external resistor connected to this pin, TinySwitch-III detects its absence and disables the line undervoltage function.
SOURCE (S) Pin:
This pin is internally connected to the output MOSFET source for high-voltage power return and control circuit common.
TinySwitch-III Functional Description
TinySwitch-III combines a high-voltage power MOSFET switch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, it uses a simple ON/OFF control to regulate the output voltage.
The controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.85 V regulator, BYPASS/ MULTI-FUNCTION pin undervoltage, overvoltage circuit, and current limit selection circuitry, over-temperature protection, current limit circuit, leading edge blanking, and a 700 V power MOSFET. TinySwitch-III incorporates additional circuitry for line undervoltage sense, auto-restart, adaptive switching cycle on­time extension, and frequency jitter. Figure 2 shows the functional block diagram with the most important features.
Oscillator
The typical oscillator frequency is internally set to an average of 132 kHz. Two signals are generated from the oscillator: the maximum duty cycle signal (DC indicates the beginning of each cycle.
The oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 8 kHz peak-to-peak, to minimize EMI emission. The modulation rate of the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter should be
0
0
0
0
0
0
0510
Figure 4. Frequency Jitter.
) and the clock signal that
MAX
V
DRAIN
136 kHz 128 kHz
measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 4 illustrates the frequency jitter.
Enable Input and Current Limit State Machine
The enable input circuit at the EN/UV pin consists of a low impedance source follower output set at 1.2 V. The current through the source follower is limited to 115 mA. When the current out of this pin exceeds the threshold current, a low logic level (disable) is generated at the output of the enable circuit, until the current out of this pin is reduced to less than the threshold current. This enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled). If low, the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the EN/UV pin voltage or current during the remainder of the cycle are ignored.
The current limit state machine reduces the current limit by discrete amounts at light loads when TinySwitch-III is likely to switch in the audible frequency range. The lower current limit raises the effective switching frequency above the audio range and reduces the transformer flux density, including the associated audible noise. The state machine monitors the sequence of enable events to determine the load condition and adjusts the current limit level accordingly in discrete amounts.
Under most operating conditions (except when close to no­load), the low impedance of the source follower keeps the voltage on the EN/UV pin from going much below 1.2 V in the disabled state. This improves the response time of the optocoupler that is usually connected to this pin.
5.85 V Regulator and 6.4 V Shunt Voltage Clamp
The 5.85 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.85 V by drawing a current from the voltage on the DRAIN pin whenever the MOSFET is off. The BYPASS/MULTI-FUNCTION pin is the internal supply voltage node. When the MOSFET is on, the device operates from the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows TinySwitch-III to operate continuously from current it takes from the DRAIN pin. A bypass capacitor value of 0.1 mF is sufficient for both high frequency decoupling and energy storage.
In addition, there is a 6.4 V shunt regulator clamping the BYPASS/MULTI-FUNCTION pin at 6.4 V when current is provided to the BYPASS/MULTI-FUNCTION pin through an external resistor. This facilitates powering of TinySwitch-III externally through a bias winding to decrease the no-load consumption to well below 50 mW.
BYPASS/MULTI-FUNCTION Pin Undervoltage
The BYPASS/MULTI-FUNCTION pin undervoltage circuitry disables the power MOSFET when the BYPASS/MULTI­FUNCTION pin voltage drops below 4.9 V in steady state operation. Once the BYPASS/MULTI-FUNCTION pin voltage drops below 4.9 V in steady state operation, it must rise back to
5.85 V to enable (turn-on) the power MOSFET.
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TNY274-280
PI-4098-082305
0
2500 5000
Time (ms)
0
5
0
10
100
200
300
V
DRAIN
V
DC-OUTPUT
Over Temperature Protection
The thermal shutdown circuitry senses the die temperature. The threshold is typically set at 142 °C with 75 °C hysteresis. When the die temperature rises above this threshold the power MOSFET is disabled and remains disabled until the die temperature falls by 75 °C, at which point it is re-enabled. A large hysteresis of 75 °C (typical) is provided to prevent over­heating of the PC board due to a continuous fault condition.
Current Limit
The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (I
), the power MOSFET is turned off for the remainder of that
LIMIT
cycle. The current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads.
The leading edge blanking circuit inhibits the current limit comparator for a short time (t
) after the power MOSFET is
LEB
turned on. This leading edge blanking time has been set so that current spikes caused by capacitance and secondary-side rectifier reverse recovery time will not cause premature termination of the switching pulse.
Auto-Restart
In the event of a fault condition such as output overload, output short-circuit, or an open loop condition, TinySwitch-III enters into auto-restart operation. An internal counter clocked by the oscillator is reset every time the EN/UV pin is pulled low. If the EN/UV pin is not pulled low for 64 ms, the power MOSFET switching is normally disabled for 2.5 seconds (except in the case of line undervoltage condition, in which case it is disabled until the condition is removed). The auto-restart alternately enables and disables the switching of the power MOSFET until the fault condition is removed. Figure 5 illustrates auto-restart circuit operation in the presence of an output short-circuit.
In the event of a line undervoltage condition, the switching of the power MOSFET is disabled beyond its normal 2.5 seconds until the line undervoltage condition ends.
Adaptive Switching Cycle On-Time Extension
Adaptive switching cycle on-time extension keeps the cycle on until current limit is reached, instead of prematurely terminating after the DC
signal goes low. This feature reduces the
MAX
minimum input voltage required to maintain regulation, extending hold-up time and minimizing the size of bulk capacitor required. The on-time extension is disabled during the start-up of the power supply, until the power supply output reaches regulation.
Line Undervoltage Sense Circuit
The DC line voltage can be monitored by connecting an external resistor from the DC line to the EN/UV pin. During power up or when the switching of the power MOSFET is disabled in auto-restart, the current into the EN/UV pin must exceed 25 mA to initiate switching of the power MOSFET. During power up, this is accomplished by holding the BYPASS/MULTI­FUNCTION pin to 4.9 V while the line undervoltage condition exists. The BYPASS/MULTI-FUNCTION pin then rises from
4.9 V to 5.85 V when the line undervoltage condition goes away. When the switching of the power MOSFET is disabled in auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. This stretches the disable time beyond its normal 2.5 seconds until the line undervoltage condition ends.
The line undervoltage circuit also detects when there is no external resistor connected to the EN/UV pin (less than ~2 mA into the pin). In this case the line undervoltage function is disabled.
TinySwitch-III Operation
TinySwitch-III devices operate in the current limit mode. When enabled, the oscillator turns the power MOSFET on at the beginning of each cycle. The MOSFET is turned off when the current ramps up to the current limit or when the DC reached. Since the highest current limit level and frequency of a TinySwitch-III design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. If the TinySwitch-III is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the DC
limit is reached.
MAX
MAX
limit is
Enable Function
TinySwitch-III senses the EN/UV pin to determine whether or not to proceed with the next switching cycle. The sequence of cycles is used to determine the current limit. Once a cycle is started, it always completes the cycle (even when the EN/UV pin changes state half way through the cycle). This operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback.
The EN/UV pin signal is generated on the secondary by comparing the power supply output voltage with a reference
Figure 5. Auto-Restart Operation.
voltage. The EN/UV pin signal is high when the power supply output voltage is less than the reference voltage.
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TNY274-280
V
DRAIN
V
EN
CLOCK
DC
DRAIN
I
MAX
PI-2749-082305
V
DRAIN
V
EN
CLOCK
DC
DRAIN
I
MAX
PI-2667-082305
PI-2661-082305
V
DRAIN
V
EN
CLOCK
DC
DRAIN
I
MAX
In a typical implementation, the EN/UV pin is driven by an optocoupler. The collector of the optocoupler transistor is connected to the EN/UV pin and the emitter is connected to the SOURCE pin. The optocoupler LED is connected in series with a Zener diode across the DC output voltage to be regulated. When the output voltage exceeds the target regulation voltage level (optocoupler LED voltage drop plus Zener voltage), the optocoupler LED will start to conduct, pulling the EN/UV pin low. The Zener diode can be replaced by a TL431 reference circuit for improved accuracy.
ON/OFF Operation with Current Limit State Machine
The internal clock of the TinySwitch-III runs all the time. At the beginning of each clock cycle, it samples the EN/UV pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. At high loads, the state machine sets the current limit to its highest value. At lighter loads, the state machine sets the current limit to reduced values.
Figure 6. Operation at Near Maximum Loading.
V
EN
CLOCK
DC
MAX
I
DRAIN
V
DRAIN
Figure 8. Operation at Medium Loading.
Figure 7. Operation at Moderately Heavy Loading.
PI-2377-082305
Figure 9. Operation at Very Light Load.
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TNY274-280
Time (s)
12
Time (ms)
100
200
PI-2383-030801
Time (ms)
PI-2348-021015
1
At near maximum load, TinySwitch-III will conduct during nearly all of its clock cycles (Figure 6). At slightly lower load, it will “skip” additional cycles in order to maintain voltage regulation at the power supply output (Figure 7). At medium loads, cycles will be skipped and the current limit will be reduced (Figure 8). At very light loads, the current limit will be reduced even further
V
DC-INPUT
0
10
5
0
400
200
0
Figure 10. Power Up with Optional External UV Resistor (4 MW)
V
BYPASS
V
DRAIN
0
Connected to EN/UV Pin.
(Figure 9). Only a small percentage of cycles will occur to satisfy the power consumption of the power supply.
The response time of the ON/OFF control scheme is very fast compared to PWM control. This provides tight regulation and excellent transient response.
200
V
100
10
400
200
Figure 11. Power Up Without Optional External UV Resistor
Connected to EN/UV Pin.
DC-INPUT
0
V
5
BYPASS
0
V
DRAIN
0
0
1 2
PI-2381-021015
200
100
V
0
400
300
200
100
0
0
.5
Time (s)
Figure 12. Normal Power Down Timing (without UV).
DC-INPUT
V
DRAIN
200
100
V
DC-INPUT
0
400
300
200
V
DRAIN
100
0
0
Figure 13. Slow Power Down Timing with Optional External (4 MW) UV Resistor
Connected to EN/UV Pin.
2.5 5
PI-2395-101014
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TNY274-280
Power Up/Down
The TinySwitch-III requires only a 0.1 mF capacitor on the BYPASS/MULTI-FUNCTION pin to operate with standard current limit. Because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. The time to charge will vary in proportion to the BYPASS/MULTI­FUNCTION pin capacitor value when selecting different current limits. Due to the high bandwidth of the ON/OFF feedback, there is no overshoot at the power supply output. When an external resistor (4 MW) is connected from the positive DC input to the EN/UV pin, the power MOSFET switching will be delayed during power up until the DC line voltage exceeds the threshold (100 V). Figures 10 and 11 show the power up timing waveform in applications with and without an external resistor (4 MW) connected to the EN/UV pin.
Under start-up and overload conditions, when the conduction time is less than 400 ns, the device reduces the switching frequency to maintain control of the peak drain current.
During power down, when an external resistor is used, the power MOSFET will switch for 64 ms after the output loses regulation. The power MOSFET will then remain off without any glitches since the undervoltage function prohibits restart when the line voltage is low.
Figure 12 illustrates a typical power down timing waveform. Figure 13 illustrates a very slow power down timing waveform as in standby applications. The external resistor (4 MW) is connected to the EN/UV pin in this case to prevent unwanted restarts.
No bias winding is needed to provide power to the chip because it draws the power directly from the DRAIN pin (see
Functional Description). This has two main benefits. First, for a nominal application, this eliminates the cost of a bias winding and associated components. Secondly, for battery charger applications, the current-voltage characteristic often allows the output voltage to fall close to zero volts while still delivering power. TinySwitch-III accomplishes this without a forward bias winding and its many associated components. For applications that require very low no-load power consumption (50 mW), a resistor from a bias winding to the BYPASS/MULTI-FUNCTION pin can provide the power to the chip. The minimum recommended current supplied is 1 mA. The BYPASS/MULTI­FUNCTION pin in this case will be clamped at 6.4 V. This method will eliminate the power draw from the DRAIN pin, thereby reducing the no-load power consumption and improving full-load efficiency.
Current Limit Operation
Each switching cycle is terminated when the DRAIN current reaches the current limit of the device. Current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage.
BYPASS/MULTI-FUNCTION Pin Capacitor
The BYPASS/MULTI-FUNCTION pin can use a ceramic capacitor as small as 0.1 mF for decoupling the internal power supply of the device. A larger capacitor size can be used to adjust the current limit. For TNY275-280, a 1 mF BP/M pin capacitor will select a lower current limit equal to the standard current limit of the next smaller device and a 10 mF BP/M pin capacitor will select a higher current limit equal to the standard current limit of the next larger device. The higher current limit level of the TNY280 is set to 850 mA typical. The TNY274 MOSFET does not have the capability for increased current limit so this feature is not available in this device.
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C5
A
85 - 265
VAC
PI-4244-111708
TNY274-280
D1
1N4007
F1
3.15 A
RV1
275 VAC
D3
1N4007
D2
1N4007
C1
6.8 µF 400 V
D4
1N4007
*R5 and R8 are optional components
C7 is used to adjust U1 current limit. See circuit description
L1
1 mH
C2 22 µF 400 V
R5*
3.6 M
TinySwitch-III
U1
TNY278PN
VR1
P6KE150A
R1
1 k
D
S
S
D5
1N4007GP
EN/UV
BP/M
C7
100 nF
50 V
R2
100
C4
10 nF
1 kV
1N5255B
VR2
28 V
R8*
21 k
1%
2.2 nF
250 VAC
T1
NC 8
1
3
R3
47
1/8 W
D7
BYV28-200
C6 1 µF 60 V
PC817A
UF4003
U2
D6
C10
1000 µF
25 V
VR3
BZX79-C11
11 V
R6 390 1/8 W
R4
2 k
1/8 W
6
R7
20
4
2
5
L2
Ferrite Bead
3.5 × 7.6 mm
C11
100 µF
25 V
12 V, 1
RTN
Figure 14. TNY278P, 12 V, 1 A Universal Input Power Supply.
Applications Example
The circuit shown in Figure 14 is a low cost, high efficiency, flyback power supply designed for 12 V, 1 A output from universal input using the TNY278.
The supply features undervoltage lockout, primary sensed output overvoltage latching shutdown protection, high efficiency (>80%), and very low no-load consumption (<50 mW at 265 VAC). Output regulation is accomplished using a simple Zener reference and optocoupler feedback.
The rectified and filtered input voltage is applied to the primary winding of T1. The other side of the transformer primary is driven by the integrated MOSFET in U1. Diode D5, C2, R1, R2, and VR1 comprise the clamp circuit, limiting the leakage inductance turn-off voltage spike on the DRAIN pin to a safe value. The use of a combination a Zener clamp and parallel RC optimizes both EMI and energy efficiency. Resistor R2 allows the use of a slow recovery, low cost, rectifier diode by limiting the reverse current through D5. The selection of a slow diode also improves efficiency and conducted EMI but should be a glass passivated type, with a specified recovery time of 2 ms.
The output voltage is regulated by the Zener diode VR3. When the output voltage exceeds the sum of the Zener and opto­coupler LED forward drop, current will flow in the optocoupler LED. This will cause the transistor of the optocoupler to sink current.When this current exceeds the ENABLE pin threshold current the next switching cycle is inhibited. When the output
voltage falls below the feedback threshold, a conduction cycle is allowed to occur and, by adjusting the number of enabled cycles, output regulation is maintained. As the load reduces, the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. This provides almost constant efficiency down to very light loads, ideal for meeting energy efficiency requirements.
As the TinySwitch-III devices are completely self-powered, there is no requirement for an auxiliary or bias winding on the transformer. However by adding a bias winding, the output overvoltage protection feature can be configured, protecting the load against open feedback loop faults.
When an overvoltage condition occurs, such that bias voltage exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION (BP/M) pin voltage (28 V+5.85 V), current begins to flow into the BP/M pin. When this current exceeds I
the internal latching
SD
shutdown circuit in TinySwitch-III is activated. This condition is reset when the BP/M pin voltage drops below 4.9 V after removal of the AC input. In the example shown, on opening the loop, the OVP trips at an output of 17 V.
For lower no-load input power consumption, the bias winding may also be used to supply the TinySwitch-III device. Resistor R8 feeds current into the BP/M pin, inhibiting the internal high-voltage current source that normally maintains the BP/M pin capacitor voltage (C7) during the internal MOSFET off time. This reduces the no-load consumption of this design from 140 mW to 40 mW at 265 VAC.
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TNY274-280
Undervoltage lockout is configured by R5 connected between the DC bus and EN/UV pin of U1. When present, switching is inhibited until the current in the EN/UV pin exceeds 25
mA. This allows the start-up voltage to be programmed within the normal operating input voltage range, preventing glitching of the output under abnormal low voltage conditions and also on removal of the AC input.
In addition to the simple input pi filter (C1, L1, C2) for differential mode EMI, this design makes use of E-Shield™ shielding techniques in the transformer to reduce common mode EMI displacement currents, and R2 and C4 as a damping network to reduce high frequency transformer ringing. These techniques, combined with the frequency jitter of TNY278, give excellent conducted and radiated EMI performance with this design achieving >12 dB
mV of margin to EN55022 Class B
conducted EMI limits.
For design flexibility the value of C7 can be selected to pick one of the 3 current limits options in U1. This allows the designer to select the current limit appropriate for the application.
Standard current limit (I
) is selected with a 0.1 mF BP/M pin
LIMIT
capacitor and is the normal choice for typical enclosed adapter applications.
When a 1 mF BP/M pin capacitor is used, the current limit is
reduced (I
LIMITred
or I
-1) offering reduced RMS device
LIMIT
currents and therefore improved efficiency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized.
When a 10 mF BP/M pin capacitor is used, the current limit is
increased (I
LIMITinc
or I
+1), extending the power capability for
LIMIT
applications requiring higher peak power or continuous power where the thermal conditions allow.
Further flexibility comes from the current limits between adjacent TinySwitch-III family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device and the increased current limit is equal to the standard current limit of the next larger device.
Key Application Considerations
TinySwitch-lll Design Considerations
Output Power Table
The data sheet output power table (Table 1) represents the minimum practical continuous output power level that can be obtained under the following assumed conditions:
1. The minimum DC input voltage is 100 V or higher for 85 VAC
input, or 220 V or higher for 230 VAC input or 115 VAC with a voltage doubler. The value of the input capacitance should be sized to meet these criteria for AC input designs.
2. Efficiency of 75%.
3. Minimum data sheet value of I2f.
4. Transformer primary inductance tolerance of ±10%.
5. Reflected output voltage (VOR) of 135 V.
6. Voltage only output of 12 V with a fast PN rectifier diode.
7. Continuous conduction mode operation with transient KP*
value of 0.25.
8. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns.
9. The part is board mounted with SOURCE pins soldered to a sufficient area of copper and/or a heatsink is used to keep the SOURCE pin temperature at or below 110 °C.
10. Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters.
*Below a value of 1, K
is the ratio of ripple to peak primary
P
current. To prevent reduced power capability due to premature termination of switching cycles a transient K recommended. This prevents the initial current limit (I
limit of ≥0.25 is
P
INIT
) from
being exceeded at MOSFET turn on.
For reference, Table 2 provides the minimum practical power delivered from each family member at the three selectable current limit values. This assumes open frame operation (not thermally limited) and otherwise the same conditions as listed above. These numbers are useful to identify the correct current limit to select for a given device and output power requirement.
Overvoltage Protection
The output overvoltage protection provided by TinySwitch-III uses an internal latch that is triggered by a threshold current of approximately 5.5 mA into the BP/M pin. In addition to an internal filter, the BP/M pin capacitor forms an external filter providing noise immunity from inadvertent triggering. For the bypass capacitor to be effective as a high frequency filter, the capacitor should be located as close as possible to the SOURCE and BP/M pins of the device.
Peak Output Power Table
230 VAC ± 15% 85-265 VAC
Product
TNY274P/G 9.1 W 10.9 W 9.1 W 7.1 W 8.5 W 7.1 W
TNY275P/G 10.8 W 12 W 15.1 W 8.4 W 9.3 W 11.8 W
TNY276P/G 11.8 W 15.3 W 19.4 W 9.2 W 11.9 W 15.1 W
TNY277P/G 15.1 W 19.6 W 23.7 W 11.8 W 15.3 W 18.5 W
TNY278P/G 19.4 W 24 W 28 W 15.1 W 18.6 W 21.8 W
TNY279P/G 23.7 W 28.4 W 32.2 W 18.5 W 22 W 25.2 W
TNY280P/G 28 W 32.7 W 36.6 W 21.8 W 25.4 W 28.5 W
Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.
I
LIMIT
-1 I
LIMITILIMIT
+1 I
LIMIT
-1 I
LIMITILIMIT
+1
For best performance of the OVP function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 V – 30 V. This minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the BP/M pin for reduced no-load consumption.
Selecting the Zener diode voltage to be approximately 6 V above the bias winding voltage (28 V for 22 V bias winding) gives good OVP performance for most designs, but can be adjusted to compensate for variations in leakage inductance. Adding additional filtering can be achieved by inserting a low
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9
Rev. K 03/17
Page 10
TNY274-280
value (10 W to 47 W) resistor in series with the bias winding diode and/or the OVP Zener as shown by R7 and R3 in Figure 14. The resistor in series with the OVP Zener also limits the maximum current into the BP/M pin.
Reducing No-load Consumption
As TinySwitch-III is self-powered from the BP/M pin capacitor, there is no need for an auxiliary or bias winding to be provided on the transformer for this purpose. Typical no-load consumption when self-powered is <150 mW at 265 VAC input. The addition of a bias winding can reduce this down to <50 mW by supplying the TinySwitch-III from the lower bias voltage and inhibiting the internal high-voltage current source. To achieve this, select the value of the resistor (R8 in Figure 14) to provide the data sheet DRAIN supply current. In practice, due to the reduction of the bias voltage at low load, start with a value equal to 40% greater than the data sheet maximum current, and then increase the value of the resistor to give the lowest no­load consumption.
Audible Noise
The cycle skipping mode of operation used in TinySwitch-III can generate audio frequency components in the transformer. To limit this audible noise generation the transformer should be designed such that the peak core flux density is below 3000 Gauss (300 mT). Following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. Vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that result. Higher flux densities are possible, however careful evaluation of the audible noise performance should be made using production transformer samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits, may also generate audio noise. If this is the case, try replacing them with a capacitor having a different dielectric or construction, for example a film type.
TinySwitch-lll Layout Considerations
Layout
See Figure 15 for a recommended circuit board layout for TinySwitch-III.
capacitor, transformer primary and TinySwitch-III together should be kept as small as possible.
Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp or a Zener (~200 V) and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the circuit path from the clamp components to the transformer and TinySwitch-III.
Thermal Considerations
The four SOURCE pins are internally connected to the IC lead frame and provide the main path to remove heat from the device. Therefore all the SOURCE pins should be connected to a copper area underneath the TinySwitch-III to act not only as a single point ground, but also as a heat sink. As this area is connected to the quiet source node, this area should be maximized for good heat sinking. Similarly for axial output diodes, maximize the PCB area connected to the cathode.
Y-Capacitor
The placement of the Y capacitor should be directly from the primary input filter capacitor positive terminal to the common/ return terminal of the transformer secondary. Such a placement will route high magnitude common mode surge currents away from the TinySwitch-III device. Note – if an input π (C, L, C) EMI filter is used then the inductor in the filter should be placed between the negative terminals of the input filter capacitors.
Optocoupler
Place the optocoupler physically close to the TinySwitch-III to minimizing the primary-side trace lengths. Keep the high current, high-voltage drain and clamp traces away from the optocoupler to prevent noise pick up.
Output Diode
For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter capacitor, should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI.
Single Point Grounding
Use a single point ground connection from the input filter capacitor to the area of copper connected to the SOURCE pins.
Bypass Capacitor (C
)
BP
The BP/M pin capacitor should be located as near as possible to the BP/M and SOURCE pins.
EN/UV Pin
Keep traces connected to the EN/UV pin short and, as far as is practical, away from all other traces and nodes above source potential including, but not limited to, the BYPASS and DRAIN pins.
Primary Loop Area
The area of the primary loop that connects the input filter
10
Rev. K 03/17
PC Board Leakage Currents
TinySwitch-III is designed to optimize energy efficiency across the power range and particularly in standby/no-load conditions. Current consumption has therefore been minimized to achieve this performance. The EN/UV pin undervoltage feature for example has a low threshold (~1 mA) to detect whether an undervoltage resistor is present.
Parasitic leakage currents into the EN/UV pin are normally well below this 1 mA threshold when PC board assembly is in a well controlled production facility. However, high humidity conditions together with board and/or package contamination, either from no-clean flux or other contaminants, can reduce the surface resistivity enough to allow parasitic currents >1 mA to flow into the EN/UV pin. These currents can flow from higher voltage exposed solder pads close to the EN/UV pin such as
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Page 11
TNY274-280
Safety Spacing
Y1-
Capacitor
+
HV
-
Input Filter Capacitor
PRI
BIAS
D
PRI
S
S
BP/M
BIAS
S
TOP VIEW
S
TinySwitch-III
EN/UV
C
BP
Opto-
coupler
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Undervoltage Lock Out Resistor.
T
r a n s
f o
r
m
e
r
Maximize hatched copper areas ( ) for optimum heatsinking
Output
Rectifier
Output Filter
SEC
DC
+ -
OUT
Capacitor
PI-4368-042506
the BP/M pin solder pad preventing the design from starting up. Designs that make use of the undervoltage lockout feature by connecting a resistor from the high-voltage rail to the EN/UV pin are not affected.
If the contamination levels in the PC board assembly facility are unknown, the application is open frame or operates in a high pollution degree environment and the design does not make use of the undervoltage lockout feature, then an optional 390 kW resistor should be added from EN/UV pin to SOURCE pin to ensure that the parasitic leakage current into the EN/UV pin is well below 1 mA.
Note that typical values for surface insulation resistance (SIR) where no-clean flux has been applied according to the suppliers’ guidelines are >>10 MW and do not cause this issue.
Quick Design Checklist
As with any power supply design, all TinySwitch-III designs should be verified on the bench to make sure that component specifications are not exceeded under worst case conditions. The following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that VDS does not exceed 650 V at highest input voltage and peak (overload) output power. The 50 V margin to the 700 V BV
specification
DSS
gives margin for design variation.
2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at start-up. Repeat under steady state conditions and verify that the leading edge current spike event is below I the end of the t
. Under all conditions, the maximum
LEB(MIN)
LIMIT(MIN)
at
drain current should be below the specified absolute maximum ratings.
3. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for TinySwitch-III, transformer, output diode, and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the R
of TinySwitch-III as
DS(ON)
specified in the data sheet. Under low line, maximum power, a maximum TinySwitch-III SOURCE pin temperature of 110 °C is recommended to allow for these variations.
Design Tools
Up-to-date information on design tools is available at the Power Integrations website: www.power.com.
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11
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Page 12
TNY274-280
Absolute Maximum Ratings
(1,5)
DRAIN Voltage ................................................... -0.3 V to 700 V
DRAIN Peak Current: TNY274 ......................... 400 (750) mA
TNY275 ....................... 560 (1050) mA
TNY276 ....................... 720 (1350) mA
TNY277 ....................... 880 (1650) mA
EN/UV Voltage .....................................................
EN/UV Current ...........................................................
BP/M Voltage ..................................................
Storage Temperature ......................................
Operating Junction Temperature
TNY278 ..................... 1040 (1950) mA
TNY279 ..................... 1200 (2250) mA
TNY280 ..................... 1360 (2550) mA
.. -0.3 V to 9 V
... 100 mA
...... -0.3 V to 9 V
-65 °C to 150 °C
(3)
................... -40 °C to 150 °C
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Thermal Resistance
Thermal Resistance: P or G Package:
(qJA) ............................ .... 70 °C/W
(1)
(qJC)
............................................... ..11 °C/W
(2)
; 60 °C/W
Conditions
Parameter Symbol
SOURCE = 0 V; T
J
See Figure 16
(Unless Otherwise Specified)
Control Functions
Output Frequency in Standard Mode
Maximum Duty Cycle DC
f
OSC
MAX
TJ = 25 °C
See Figure 4
Peak-to-peak Jitter 8
S1 Open 62 65 %
Lead Temperature
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
(4)
........................................................260 °C
2. The higher peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V.
3. Normally limited by internal circuitry.
4. 1/16 in. from case for 5 seconds.
5. Maximum ratings specified may be applied one at a time, without causing permanent damage to the product. Exposure to Absolute Rating conditions for extended periods of time may affect product reliability.
Notes:
(3)
1. Measured on the SOURCE pin close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm
= -40 to 125 °C
Min Typ Max Units
2
), 2 oz. (610 g/m2) copper clad.
Average 124 132 140
kHz
EN/UV Pin Upper Turnoff Threshold Current
EN/UV Pin Voltage
DRAIN Supply Current
I
DIS
I
= 25 mA 1.8 2.2 2.6
V
EN
I
S1
EN/UV Current > I
EN/UV
I
= -25 mA 0.8 1.2 1.6
EN/UV
(MOSFET Not
DIS
Switching) See Note A
-150 -115 -90 mA
V
290 mA
TNY274 275 360
TNY275 295 400
EN/UV Open
I
S2
(MOSFET
Switching at f
OSC
)
See Note B
TNY276 310 430
TNY277 365 460
TNY278 445 540
mA
TNY279 510 640
TNY280 630 760
12
Rev. K 03/17
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Page 13
Parameter Symbol
Control Functions (cont.)
BP/M Pin Charge Current
I
I
CH1
CH2
Conditions
SOURCE = 0 V; T
= -40 to 125 °C
J
See Figure 16
(Unless Otherwise Specified)
V
= 0 V,
BP/M
T
= 25 °C
J
TNY275-278 -8.3 -5.4 -2.5
See Note C, D
TNY279-280 -9.7 -6.8 -3.9
V
= 4 V,
BP/M
T
= 25 °C
J
TNY275-278 -5 -3.5 -1.5
See Note C, D
TNY279-280 -6.6 -4.6 -2.1
TNY274-280
Min Typ Max Units
TNY274 -6 -3.8 -1.8
mA
TNY274 -4.1 -2.3 -1
BP/M Pin Voltage V
BP/M Pin Voltage Hysteresis
BP/M Pin Shunt Voltage
EN/UV Pin Line Under­voltage Threshold
Circuit Protection
Standard Current Limit (BP/M Capacitor =
0.1 mF) See Note D
V
V
SHUNT
I
I
BP/M
BP/MH
LUV
LIMIT
See Note C 5.6 5.85 6.15 V
IBP = 2 mA 6.0 6.4 6.7 V
TJ = 25 °C 22.5 25 27.5 mA
di/dt = 50 mA/ms
T
= 25 °C
J
See Note E
di/dt = 55 mA/ms
TJ = 25 °C
See Note E
di/dt = 70 mA/ms
TJ = 25 °C
See Note E
di/dt = 90 mA/ms
TJ = 25 °C
See Note E
di/dt = 110 mA/ms
TJ = 25 °C
See Note E
0.80 0.95 1.20 V
TNY274P 233 250 267
TNY274G 233 250 273
TNY275P 256 275 294
TNY275G 256 275 300
TNY276P 326 350 374
TNY276G 326 350 382
TNY277P 419 450 481
mA
TNY277G 419 450 491
TNY278P 512 550 588
TNY278G 512 550 600
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di/dt = 130 mA/ms
TJ = 25 °C
See Note E
di/dt = 150 mA/ms
TJ = 25 °C
See Note E
TNY279P 605 650 695
TNY279G 605 650 709
TNY280P 698 750 802
TNY280G 698 750 818
13
Rev. K 03/17
Page 14
TNY274-280
Parameter Symbol
Circuit Protection (cont.)
Conditions
SOURCE = 0 V; T
= -40 to 125 °C
J
See Figure 16
(Unless Otherwise Specified)
di/dt = 50 mA/ms
T
= 25 °C
J
See Note E
Min Typ Max Units
TNY274P
196 210 233
TNY274G 196 210 237
Reduced Current Limit (BP/M Capacitor = 1 mF) See Note D
I
LIMITred
di/dt = 55 mA/ms
TJ = 25 °C
See Note E
di/dt = 70 mA/ms
TJ = 25 °C
See Notes E
di/dt = 90 mA/ms
TJ = 25 °C
See Notes E
di/dt = 110 mA/ms
TJ = 25 °C
See Notes E
di/dt = 130 mA/ms
TJ = 25 °C
See Notes E
di/dt = 150 mA/ms
TJ = 25 °C
See Notes E
di/dt = 50 mA/ms
T
= 25 °C
J
See Notes E, F
di/dt = 55 mA/ms
TJ = 25 °C
See Notes E
TNY275P 233 250 277
TNY275G 233 250 283
TNY276P 256 275 305
TNY276G 256 275 311
TNY277P 326 350 388
mA
TNY277G 326 350 396
TNY278P 419 450 499
TNY278G 419 450 509
TNY279P 512 550 610
TNY279G 512 550 622
TNY280P 605 650 721
TNY280G 605 650 735
TNY274P 196 210 233
TNY274G 196 210 237
TNY275P 326 350 388
TNY275G 326 350 396
Increased Current Limit (BP/M Capacitor = 10 mF) See Note D
14
Rev. K 03/17
I
LIMITinc
di/dt = 70 mA/ms
TJ = 25 °C
See Notes E
di/dt = 90 mA/ms
TJ = 25 °C
See Notes E
di/dt = 110 mA/ms
TJ = 25 °C
See Notes E
di/dt = 130 mA/ms
TJ = 25 °C
See Notes E
di/dt = 150 mA/ms
TJ = 25 °C
See Notes E
TNY276P 419 450 499
TNY276G 419 450 509
TNY277P 512 550 610
TNY277G 512 550 622
TNY278P 605 650 721
TNY278G 605 650 735
TNY279P 698 750 833
TNY279G 698 750 848
TNY280P 791 850 943
TNY280G
791 850 961
mA
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Page 15
Parameter Symbol
Circuit Protection (cont.)
Power Coefficient I
TNY274-280
Conditions
SOURCE = 0 V; T
See Figure 16
(Unless Otherwise Specified)
Standard Current
2
Limit, I
f = I
LIMIT(TYP)
× f
OSC(TYP)
TJ = 25 °C
Reduced Current
2
Limit, I
f = I
2
f
× f
LIMITred(TYP)
OSC(TYP)
TJ = 25 °C
Increased Current
2
Limit, I
f = I
LIMITinc(TYP)
× f
OSC(TYP)
TJ = 25 °C
= -40 to 125 °C
J
TNY274-280P
2
TNY274-280G
TNY274-280P
2
TNY274-280G
TNY274-280P
2
TNY274-280G
Min Typ Max Units
0.9 ×
2
I
f
0.9 ×
2
I
f
0.9 ×
2
I
f
0.9 ×
2
I
f
0.9 ×
2
I
f
0.9 × I2f
2
f
I
2
f
I
2
f
I
2
f
I
2
f
I
2
f
I
1.12 ×
2
I
f
1.16 ×
2
I
f
1.16 ×
2
I
f
1.20 ×
2
I
f
1.16 ×
2
I
f
1.20 ×
2
I
f
2
A
Hz
Initial Current Limit I
Leading Edge Blanking Time
Current Limit Delay
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
BP/M Pin Shutdown Threshold Current
BP/M Pin Power up Reset Threshold
V
BP/M(RESET)
Voltage
Output
INIT
t
LEB
t
ILD
T
SD
T
SDH
I
SD
T
= 25 °C, See Note G
J
TJ = 25 °C
See Note G
TJ = 25 °C
See Note G, H
See Figure 19
0.75 × I
LIMIT(MIN)
170 215 ns
150 ns
135 142 150 °C
75 °C
4 6.5 9 mA
mA
1.6 2.6 3.6 V
= 25 °C 28 32
T
TNY274
I
= 25 mA
D
J
TJ = 100 °C 42 48
ON-State Resistance
www.power.com
R
DS(ON)
TNY275
I
= 28 mA
D
TNY276
I
= 35 mA
D
= 25 °C 19 22
T
J
TJ = 100 °C 29 33
= 25 °C 14 16
T
J
TJ = 100 °C 21 24
W
15
Rev. K 03/17
Page 16
TNY274-280
Parameter Symbol
Output (cont.)
ON-State Resistance
R
DS(ON)
Conditions
SOURCE = 0 V; T
= -40 to 125 °C
J
See Figure 16
(Unless Otherwise Specified)
TNY277
I
= 45 mA
D
TNY278
I
= 55 mA
D
TNY279
I
= 65 mA
D
TNY280
I
= 75 mA
D
T
TJ = 100 °C 11.7 13.5
T
TJ = 100 °C 7.8 9.0
T
TJ = 100 °C 5.8 6.7
T
TJ = 100 °C 3.9 4.5
Min Typ Max Units
= 25 °C 7.8 9.0
J
= 25 °C 5.2 6.0
J
= 25 °C 3.9 4.5
J
= 25 °C 2.6 3.0
J
W
OFF-State Drain Leakage Current
Breakdown Voltage
DRAIN Supply Voltage
Auto-Restart ON-Time at f
OSC
Auto-Restart Duty Cycle
BV
DC
I
DSS1
I
DSS2
t
TNY274-276 50
TNY279-280 200
= 375 V,
V
DS
T
= 50 °C
J
15
See Note G, I
= 0 V,
EN/UV
= 25 °C
J
700 V
mATNY277-278 100
DSS
V
= 6.2 V
BP/M
V
= 0 V
EN/UV
V
= 560 V
DS
T
= 125 °C
J
See Note I
V
= 6.2 V
BP/M
V
= 0 V
EN/UV
VBP = 6.2 V, V
See Note J, T
50 V
AR
AR
See Note K
TJ = 25 °C 3 %
TJ = 25 °C
64 ms
16
Rev. K 03/17
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Page 17
TNY274-280
NOTES: A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these
conditions. Total device consumption at no-load is the sum of I
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN.
An alternative is to measure the BP/M pin current at 6.1 V.
C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M
capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization.
Nominal BP/M
Pin Cap Value
0.1 mF -60% +100%
1 mF -50% +100%
10 mF -50% NA
Tolerance Relative to Nominal
Capacitor Value
Min Max
E. For current limit at other di/dt values, refer to Figure 23.
F. TNY274 does not set an increased current limit value, but with a 10 mF BP/M pin capacitor the current limit is the same as with a
1 mF BP/M pin capacitor (reduced current limit value).
G. This parameter is derived from characterization.
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I
I. I
is the worst-case OFF-state leakage specification at 80% of BV
DSS1
typical specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations.
J. Breakdown voltage may be checked against minimum BV
exceeding minimum BV
DSS
.
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
and I
S1
specification by ramping the DRAIN pin voltage up to but not
DSS
.
DSS2
specification.
LIMIT
and maximum operating junction temperature. I
DSS
DSS2
is a
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17
Rev. K 03/17
Page 18
TNY274-280
0.8
PI-4279-013006
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
Figure 16. General Test Circuit.
S D
S
BP/M
S
EN/UV
S
0.1 µF
2 M
470
5 W
S1
150 V
DC
MAX
(internal signal)
EN/UV
470
10 V
S2
50 V
PI-4079-080905
t
P
Figure 17. Duty Cycle Measurement.
t
V
DRAIN
1
tP =
f
OSC
Figure 18. Output Enable Timing.
EN/UV
PI-2364-012699
18
Rev. K 03/17
Figure 19. Current Limit Envelope.
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Page 19
Breakdown Voltage
(Normalized to 25
PI-4102-010906
1.2
Standard Current Limit
(Normalized to 25
1.2
Junction Temperature (°C)
PI-4280-012306
Output Frequency
(Normalized to 25
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1234
Normalized di/dt
PI-4081-082305
Normalized Current Limit
TNY274 50 mA/µs TNY275 55 mA/µs TNY276 70 mA/µs TNY277 90 mA/µs TNY278 110 mA/µs TNY279 130 mA/µs TNY280 150 mA/µs
Normalized
di/dt = 1
Note: For the normalized current limit value, use the typical current limit specified for the appropriate BP/M capacitor.
DRAIN Voltage (V)
Drain Current (mA)
300
250
200
100
50
150
0
0 2 4 6 8 10
T
CASE
=25 °C
T
CASE
=100 °C
PI-4082-082305
TNY274 1.0 TNY275 1.5 TNY276 2.0 TNY277 3.5 TNY278 5.5 TNY279 7.3 TNY280 11
Scaling Factors:
Drain Voltage (V)
Drain Capacitance (pF)
PI-4083-082305
0 100 200 300 400 500 600
1
10
100
1000
TNY274 1.0 TNY275 1.5 TNY276 2.0 TNY277 3.5 TNY278 5.5 TNY279 7.3 TNY280 11
Scaling Factors:
Typical Performance Characteristics
1.1
TNY274-280
°C)
1.0
0.9
-50 -25 0255075 100 125 150
Junction Temperature (°C)
Figure 20. Breakdown vs. Temperature.
1
°C)
0.8
0.6
PI-2213-012301
1.0
°C)
0.8
0.6
0.4
0.2
0
-50 -25025 50 75 100 125
Figure 21. Frequency vs. Temperature.
0.4
0.2
0
-50 050 100 150
Temperature (°C)
Figure 22. Standard Current Limit vs. Temperature.
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Figure 24. Output Characteristic.
Figure 23. Current Limit vs. di/dt.
Figure 25. C
vs. Drain Voltage.
OSS
19
Rev. K 03/17
Page 20
TNY274-280
50
30
40
10
20
0
0 200 400 600
DRAIN Voltage (V)
Power (mW)
PI-4084-032516
TNY274 1.0 TNY275 1.5 TNY276 2.0 TNY277 3.5 TNY278 5.5 TNY279 7.3 TNY280 11
Scaling Factors:
1.2
Under-Voltage Threshold
(Normalized to 25
Typical Performance Characteristics (cont.)
Figure 26. Drain Capacitance Power.
1.0
°C)
PI-4281-012306
0.8
0.6
0.4
0.2
0
-50 -25 0255075 100 125
Figure 27. Undervoltage Threshold vs. Temperature.
Junction Temperature (°C)
20
Rev. K 03/17
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Page 21
-E-
.240 (6.10) .260 (6.60)
Pin 1
-D-
.125 (3.18) .145 (3.68)
-T­SEATING PLANE
.100 (2.54) BSC
D S
.356 (9.05) .387 (9.83)
.014 (.36) .022 (.56)
.004 (.10)
.048 (1.22) .053 (1.35)
T E D S
PDIP-8C (P Package)
Notes:
1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.
3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock­ wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted.
5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm).
6. Lead width measured at package body.
7. Lead spacing measured with the leads constrained to be .057 (1.45) .068 (1.73)
(NOTE 6)
.015 (.38) MINIMUM
.118 (3.00) .140 (3.56)
.137 (3.48)
MINIMUM
.010 (.25) M
perpendicular to plane T.
.008 (.20) .015 (.38)
.300 (7.62) BSC
(NOTE 7)
.300 (7.62) .390 (9.91)
TNY274-280
P08C
PI-3933-081716
-E-
.240 (6.10) .260 (6.60)
Pin 1
-D-
.125 (3.18) .145 (3.68)
.032 (.81) .037 (.94)
D S
.004 (.10)
.100 (2.54) (BSC)
.356 (9.05) .387 (9.83)
.048 (1.22) .053 (1.35)
SMD-8C (G Package)
.046
.086
.372 (9.45) .388 (9.86)
.010 (.25)
E S
.137 (3.48) MINIMUM
.057 (1.45) .068 (1.73)
(NOTE 5)
.009 (.23)
Pin 1
Solder Pad Dimensions
.004 (.10) .012 (.30)
.060
.186
.286
.004 (.10)
.036 (0.91) .044 (1.12)
.060
.046
.080
Notes:
1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.
2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side.
3. Pin locations start with Pin 1,
.420
and continue counter-clock­ wise to Pin 8 when viewed from the top. Pin 3 is omitted.
4. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm).
5. Lead width measured at package body.
6. D and E are referenced datums on the package body.
°
°
8
0 -
G08C
PI-4015-081716
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21
Rev. K 03/17
Page 22
TNY274-280
Part Ordering Information
TNY 278 G N - TL
22
Rev. K 03/17
• TinySwitch Product Family
• Series Number
• Package Identifier
G Plastic Surface Mount SMD-8C
P Plastic DIP-8C
• Lead Finish
N Pure Matte Tin (Pb-Free)
G RoHS compliant and Halogen Free (P package only)
• Tape & Reel and Other Options
Blank Standard Configuration
TL Tape & Reel, 1000 pcs min./mult., G package only
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Page 23
TNY274-280
Revision Notes Date
D Release final data sheet. 1/06
E Corrected figure numbers and references. 2/06
Separated current limit and power coefficient values for G package and updated Figure 15. Added EN/UV and PC board
F
leakage currents in Key Applications Considerations section.
G Updated line undervoltage current threshold to 2 mA. 6/06
H Updated BP/M Pin Charge current and Power Coefficient sections of Parameter Tables. 9/08
I Updated Part Ordering Information section with Halogen Free. 1/09
I Updated TNY284P I
-1 to 9.1 W in Table 2. 09/12
LIMIT
J Updated with new Logo Brand Style. 06/15
J Minor correction made to Functional Block Diagram. 07/15
K Updated PDIP-8C (P Package) and SMD-8C (G Package) per PCN-16232. 08/16
K Minor text change on page 8. 03/17
4/06
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23
Rev. K 03/17
Page 24
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.
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