Datasheet TNY176PN Specification

TNY174-180

TinySwitch-LT Family

Energy Efcient, Ofine Switcher with Enhanced
Flexibility and Extended Power Range

Product Highlights

Lowest System Cost with Enhanced Flexibility

• 650 V rating optimized for non-active PFC applications

• Simple ON/OFF control, no loop compensation needed

• Selectable current limit through BP/M capacitor value

• Higher current limit extends peak power or, in open frame

applications, maximum continuous power

• Lower current limit improves efciency in enclosed adapters/

chargers

• Allows optimum TinySwitch-LT choice by swapping

devices with no other circuit redesign

• Tight I

• ON-time extension – extends low-line regulation range/hold-up time

• Self-biased: no bias winding or bias components

• Frequency jittering reduces EMI lter costs

• Pin-out simplies heat sinking to the PCB

• SOURCE pins are electrically quiet for low EMI

Enhanced Safety and Reliability Features

• Accurate hysteretic thermal shutdown protection with

• Auto-restart delivers <3% of maximum power in short-circuit and

• Output overvoltage shutdown with optional Zener

• Very low component count enhances reliability and enables

• High bandwidth provides fast turn on with no overshoot and

• Extended creepage between DRAIN and all other pins improves eld

EcoSmart™– Extremely Energy Efcient

• Easily meets all global energy efciency regulations

• No-load <150 mW at 265 VAC without bias winding,

• ON/OFF control provides constant efciency down to very light loads

Applications

• Chargers/adapters for cell/cordless phones, PDAs, digital cameras,

• DVD/PVR and other low power set top decoders

• Supplies for appliances, industrial systems, metering, etc.

Description

TinySwitch™-LT incorporates a 650 V power MOSFET, oscillator,
high-voltage switched current source, current limit (user selectable) and
thermal shutdown circuitry. The IC family uses an ON/OFF control

scheme and offers a design exible solution with a low system cost and

extended power capability.

2

f parameter tolerance reduces system cost

• Maximizes MOSFET and magnetics power delivery

• Minimizes max overload power, reducing cost of

transformer, primary clamp & secondary components

to reduce input bulk capacitance

automatic recovery eliminates need for manual reset

open loop fault conditions

single-sided printed circuit board layout

excellent transient load response

reliability

<50 mW with bias winding

– ideal for mandatory CEC regulations

MP3/portable audio, shavers, etc.

AC

Input

TinySwitch-LT

Figure 1. Typical Application.

D

EN

BP/M

S

PI-4770-010709

+

DC

Output

Output Power Table

230 VAC ± 15% 85-265 VAC

Product

TNY174P/D

TNY1 75P/D

TNY176P/D

TNY177P

3

Adapter

4

4

4

4

6 W 11 W 5 W 8.5 W

8.5 W 15 W 6 W 11. 5 W

10 W 19 W 7 W 15 W

13 W 23.5 W 8 W 18 W

TNY177D 11.5 W 23.5 W 7 W 18 W

TNY178P 16 W 28 W 10 W 21.5 W

TNY178D 14.5 W 26 W 9 W 19.5 W

TNY179P 18 W 32 W 12 W 25 W

TNY180P 20 W 36.5 W 14 W 28.5 W

Table 1. Output Power Table.

Note s:

1. Minimum continuous power in a typical non-ventilated enclosed adapter
measured at +50 °C ambient. Use of an external heat sink will increase
power capability.

2. Minimum peak power capability in any design or minimum continuous power
in an open frame design (see Key Applications Considerations).

3. Packages: P: DIP-8C, D: SO-8C. See Part Ordering Information.

4. See Key Application Considerations.

1

Peak or

Open

Frame

2

Adapter

1

Peak or

Open

Frame

2

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TNY174-180

PI-4771-090313

CLOCK

OSCILLATOR

5.85 V

4.9 V

SOURCE

(S)

SRQ

DC

MAX

BYPASS/

MULTI-FUNCTION

(BP/M)

+

-

V

I

LIMIT

FAULT

PRESENT

CURRENT LIMIT
COMPARATOR

ENABLE

LEADING

EDGE

BLANKING

THERMAL

SHUTDOWN

+

-

DRAIN

(D)

BYPASS PIN
UNDER-VOLTAGE

1.0 V + V

T

ENABLE

(EN)

Q

115 µA

RESET

AUTO-

RESTART

COUNTER

JITTER

BYPASS

CAPACITOR

SELECT AND

CURRENT

LIMIT STATE

MACHINE

OVP

LATCH

1.0 V

REGULATOR

5.85 V

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:

This pin is the power MOSFET drain connection. It provides internal

operating current for both start-up and steady-state operation.

BYPASS/MULTI-FUNCTION (BP/M) Pin:

This pin has multiple functions:

1. It is the connection point for an external bypass capacitor for the

2. It is a mode selector for the current limit value, depending on the

3. It provides a shutdown function. When the current into the

internally generated 5.85 V supply.

value of the capacitance added. Use of a 0.1 mF capacitor results
in the standard current limit value. Use of a 1 mF capacitor
results in the current limit being reduced to that of the next
smaller device size. Use of a 10 mF capacitor results in the
current limit being increased to that of the next larger device size
fo r T N Y 17 5 -180.

bypass pin exceeds ISD, the device latches off until the
BP/M voltage drops below 4.9 V, during a power-down. This can
be used to provide an output overvoltage function with a Zener
connected from the BP/M pin to a bias winding supply.

P Package (DIP-8C)

EN

1

2

4

D

BP/M

Figure 3. Pin Conguration.

8

7

6

5

S

S

S

S

EN 1

BP/M 2

D 4

D Package (SO-8C)

PI-4772-090313

8 S

7 S

6 S

5 S

2

Rev. G 08/16

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TNY174-180

600

Time (µs)

PI-2741-041901

ENABLE (EN) Pin:

The switching of the power MOSFET is controlled by this pin.
MOSFET switching is terminated when a current greater than a
threshold current is drawn from this pin. Switching resumes when the
current being pulled from the pin drops to less than a threshold current.
A modulation of the threshold current reduces group pulsing. The
threshold current is between 75 mA and 115 mA.

SOURCE (S) Pin:

This pin is internally connected to the output MOSFET source for
high-voltage power return and control circuit common.

TinySwitch-LT Functional Description

TinySwitch-LT combines a high-voltage power MOSFET switch with a
power supply controller in one device. Unlike conventional PWM
(pulse width modulator) controllers, it uses a simple ON/OFF control
to regulate the output voltage.

The controller consists of an oscillator, enable circuit (sense and
logic), current limit state machine, 5.85 V regulator, BYPASS/
MULTI-FUNCTION pin , overvoltage circuit, and current limit selection
circuitry, over-temperature protection, current limit circuit, leading
edge blanking, and a 650 V power MOSFET. TinySwitch-LT incorpo­rates additional circuitry for auto-restart, adaptive switching cycle
on-time extension, and frequency jitter. Figure 2 shows the func­tional block diagram with the most important features.

Oscillator

The typical oscillator frequency is internally set to an average of
132 kHz. Two signals are generated from the oscillator: the maximum
duty cycle signal (DC
beginning of each cycle.

The oscillator incorporates circuitry that introduces a small amount of
frequency jitter, typically 8 kHz peak-to-peak, to minimize EMI emission.
The modulation rate of the frequency jitter is set to 1 kHz to optimize
EMI reduction for both average and quasi-peak emissions. The
frequency jitter should be measured with the oscilloscope triggered
at the falling edge of the DRAIN waveform. The waveform in Figure
4 illustrates the frequency jitter.

500

400

300

200

100

0

0510

) and the clock signal that indicates the

MAX

V

DRAIN

136 kHz
128 kHz

Enable Input and Current Limit State Machine

The enable input circuit at the ENABLE pin consists of a low imped­ance source follower output set at 1.2 V. The current through the
source follower is limited to 115 mA. When the current out of this pin
exceeds the threshold current, a low logic level (disable) is generated
at the output of the enable circuit, until the current out of this pin is
reduced to less than the threshold current. This enable circuit output
is sampled at the beginning of each cycle on the rising edge of the
clock signal. If high, the power MOSFET is turned on for that cycle
(enabled). If low, the power MOSFET remains off (disabled). Since
the sampling is done only at the beginning of each cycle, subsequent
changes in the ENABLE pin voltage or current during the remainder of
the cycle are ignored.

The current limit state machine reduces the current limit by discrete
amounts at light loads when TinySwitch-LT is likely to switch in the
audible frequency range. The lower current limit raises the effective
switching frequency above the audio range and reduces the transform-

er ux density, including the associated audible noise. The state

machine monitors the sequence of enable events to determine the load
condition and adjusts the current limit level accordingly in discrete
amounts.

Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on the
ENABLE pin from going much below 1.2 V in the disabled state.
This improves the response time of the optocoupler that is usually
connected to this pin.

5.85 V Regulator and 6.4 V Shunt Voltage Clamp

The 5.85 V regulator charges the bypass capacitor connected to the
BYPASS pin to 5.85 V by drawing a current from the voltage on the
DRAIN pin whenever the MOSFET is off. The BYPASS/MULTI-FUNC­TION pin is the internal supply voltage node. When the MOSFET is
on, the device operates from the energy stored in the bypass
capacitor. Extremely low power consumption of the internal circuitry
allows TinySwitch-LT to operate continuously from current it takes
from the DRAIN pin. A bypass capacitor value of 0.1 mF is sufcient
for both high frequency decoupling and energy storage.

In addition, there is a 6.4 V shunt regulator clamping the BYPASS/
MULTI-FUNCTION pin at 6.4 V when current is provided to the
BYPASS/MULTI-FUNCTION pin through an external resistor. This
facilitates powering of TinySwitch-LT externally through a bias
winding to decrease the no-load consumption to well below 50 mW.

BYPASS/MULTI-FUNCTION Pin

The BYPASS/MULTI-FUNCTION pin circuitry disables the power
MOSFET when the BYPASS/MULTI-FUNCTION pin voltage drops
below 4.9 V in steady state operation. Once the BYPASS/MULTI­FUNCTION pin voltage drops below 4.9 V in steady state operation,
it must rise back to 5.85 V to enable (turn-on) the power MOSFET.

Over-Temperature Protection

The thermal shutdown circuitry senses the die temperature. The
threshold is typically set at 142 °C with 75 °C hysteresis. When the die
temperature rises above this threshold the power MOSFET is disabled
and remains disabled until the die temperature falls by 75 °C, at which
point it is re-enabled. A large hysteresis of 75 °C (typical) is provided
to prevent over-heating of the PC board due to a continuous fault
condition.

Figure 4. Frequency Jitter.

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3

Rev. G 08/16

TNY174-180

PI-4098-082305

0

2500 5000

Time (ms)

0

5

0

10

100

200

300

V

DRAIN

V

DC-OUTPUT

Current Limit

The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
MOSFET is turned off for the remainder of that cycle. The current limit

), the power

LIMIT

state machine reduces the current limit threshold by discrete amounts
under medium and light loads.

The leading edge blanking circuit inhibits the current limit comparator
for a short time (t
leading edge blanking time has been set so that current spikes

) after the power MOSFET is turned on. This

LEB

caused by capacitance and secondary-side rectier reverse recovery

time will not cause premature termination of the switching pulse.

Auto-Restart

In the event of a fault condition such as output overload, output
short-circuit, or an open loop condition, TinySwitch-LT enters into
auto-restart operation. An internal counter clocked by the oscillator
is reset every time the ENABLE pin is pulled low. If the ENABLE pin is
not pulled low for 64 ms, the power MOSFET switching is normally
disabled for 2.5 seconds. The auto-restart alternately enables and
disable s the switching of the power MOSFET until the fault condition is
removed. Figure 5 illustrates auto-restart circuit operation in the pres­ence of an output short-circuit.

Adaptive Switching Cycle On-Time Extension

Adaptive switching cycle on-time extension keeps the cycle on until
current limit is reached, instead of prematurely terminating after the
DC

signal goes low. This feature reduces the minimum input

MAX

voltage required to maintain regulation, extending hold-up time and
minimizing the size of bulk capacitor required. The on-time extension
is disabled during the start-up of the power supply, until the power
supply output reaches regulation.

TinySwitch-LT Operation

TinySwitch-LT devices operate in the current limit mode. When
enabled, the oscillator turns the power MOSFET on at the beginning
of each cycle. The MOSFET is turned off when the current ramps up
to the current limit or when the DC
highest current limit level and frequency of a TinySwitch-LT design
are constant, the power delivered to the load is proportional to the

Figure 5. Auto-Restar t Operation.

limit is reached. Since the

MAX

primary inductance of the transformer and peak primary current
squared. Hence, designing the supply involves calculating the primary
inductance of the transformer for the maximum output power
required. If the TinySwitch-LT is appropriately chosen for the power
level, the current in the calculated inductance will ramp up to current
limit before the DC

limit is reached.

MAX

Enable Function

TinySwitch-LT senses the ENABLE pin to determine whether or not to
proceed with the next switching cycle. The sequence of cycles is
used to determine the current limit. Once a cycle is started, it always
completes the cycle (even when the ENABLE pin changes state half
way through the cycle). This operation results in a power supply in
which the output voltage ripple is determined by the output capacitor,
amount of energy per switch cycle and the delay of the feedback.

The ENABLE pin signal is generated on the secondary by comparing
the power supply output voltage with a reference voltage. The
ENABLE pin signal is high when the power supply output voltage is
less than the reference voltage.

In a typical implementation, the ENABLE pin is driven by an
optocoupler. The collector of the optocoupler transistor is connected
to the ENABLE pin and the emitter is connected to the SOURCE pin.
The optocoupler LED is connected in series with a Zener diode across
the DC output voltage to be regulated. When the output voltage
exceeds the target regulation voltage level (optocoupler LED voltage
drop plus Zener voltage), the optocoupler LED will start to conduct,
pulling the ENABLE pin low. The Zener diode can be replaced by a
TL431 reference circuit for improved accuracy.

ON/OFF Operation with Current Limit State Machine

The internal clock of the TinySwitch-LT runs all the time. At the
beginning of each clock cycle, it samples the ENABLE pin to decide
whether or not to implement a switch cycle, and based on the
sequence of samples over multiple cycles, it determines the appropri­ate current limit. At high loads, the state machine sets the current
limit to its highest value. At lighter loads, the state machine sets the
current limit to reduced values.

At near maximum load, TinySwitch-LT will conduct during nearly all of
its clock cycles (Figure 6). At slightly lower load, it will “skip”
additional cycles in order to maintain voltage regulation at the power
supply output (Figure 7). At medium loads, cycles will be skipped and
the current limit will be reduced (Figure 8). At very light loads, the
current limit will be reduced even further (Figure 9). Only a small
percentage of cycles will occur to satisfy the power consumption of
the power supply.

The response time of the ON/OFF control scheme is very fast
compared to PWM control. This provides tight regulation and
excellent transient response.

Power-Up/Down

The TinySwitch-LT requires only a 0.1 mF capacitor on the BYPASS/
MULTI-FUNCTION pin to operate with standard current limit.
Because of its small size, the time to charge this capacitor is kept to
an absolute minimum, typically 0.6 ms. The time to charge will vary
in proportion to the BYPASS/MULTI-FUNCTION pin capacitor value
when selecting different current limits. Due to the high bandwidth of
the ON/OFF feedback, there is no overshoot at the power supply
output.

Figure 10 shows typical power-up timing waveforms.

4

Rev. G 08/16

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TNY174-180

V

DRAIN

V

EN

CLOCK

DC

DRAIN

I

MAX

PI-2749-082305

V

DRAIN

V

EN

CLOCK

DC

DRAIN

I

MAX

PI-2667-082305

Under start-up and overload conditions, when the conduction time is
less than 400 ns, the device reduces the switching frequency to main­tain control of the peak drain current.

During power-down, the power MOSFET will switch for 64 ms after
the output loses regulation.

Figure 11 illustrates a typical power-down timing waveform.

No bias winding is needed to provide power to the chip because it
draws the power directly from the DRAIN pin (see Functional

Description above). This has two main benets. First, for a nominal

application, this eliminates the cost of a bias winding and associated
components. Secondly, for battery charger applications, the
current-voltage characteristic often allows the output voltage to fall
close to zero volts while still delivering power. TinySwitch-LT
accomplishes this without a forward bias winding and its many associ­ated components. For applications that require very low no-load
power consumption (50 mW), a resistor from a bias winding to the
BYPASS/MULTI-FUNCTION pin can provide the power to the chip.
The minimum recommended current supplied is 1 mA. The BYPASS/
MULTI-FUNCTION pin in this case will be clamped at 6.4 V. This
method will eliminate the power draw from the DRAIN pin, thereby
reducing the no-load power consumption and improving full-load

efciency.

Current Limit Operation

Each switching cycle is terminated when the DRAIN current reaches
the current limit of the device. Current limit operation provides good
line ripple rejection and relatively constant power delivery indepen­dent of input voltage.

BYPASS/MULTI-FUNCTION Pin Capacitor

The BYPASS/MULTI-FUNCTION pin can use a ceramic capacitor as
small as 0.1 mF for decoupling the internal power supply of the
device. A larger capacitor size can be used to adjust the current limit.
For TNY175-180, a 1 mF BP/M pin capacitor will select a lower current
limit equal to the standard current limit of the next smaller device and
a 10 mF BP/M pin capacitor will select a higher current limit equal to
the standard current limit of the next larger device. The higher
current limit level of the TNY180 is set to 850 mA typical. The
TNY174 MOSFET does not have the capability for increased current
limit so this feature is not available in this device.

Figure 6. Operation at Near Maximum Loading.

Figure 7. Operation at Moderately Heavy Loading.

V

EN

CLOCK

DC

MAX

I

DRAIN

V

DRAIN

Figure 8. Operation at Medium Loading.

PI-2377-082305

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5

Rev. G 08/16

TNY174-180

PI-2661-082305

V

DRAIN

V

EN

CLOCK

DC

DRAIN

I

MAX

200

100

V

DC-INPUT

Figure 9. Operation at Very Light Load.

0

10

V

5

BYPASS

0

400

200

V

DRAIN

0

0

Figure 10. Power-Up.

200

100

0

400

300

1 2

Time (ms)

V

DC-INPUT

PI-2381-021015

PI-2348-021015

V

200

DRAIN

100

0

0

.5 1

Time (s)

Figure 11. Normal Power-Down Timing.

6

Rev. G 08/16

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J1

85-265

VAC

J2

F1

3.15 A

RV1

275 VAC

D1

1N4007

D3

1N4007

D2

1N4007

C1

6.8 µF
400 V

D4

1N4007

*R5 is optional

†

C7 is configurable to adjust
U1 current limit, see circuit
description

L1

1 mH

C2

1 kΩ

22 µF
400 V

TinySwitch-LT

U1

TNY178P

VR1

P6KE150A

R1

D

S

S

100 nF

D5

1N4007GP

EN

BP/M

†

C7

50 V

R2

100 Ω

C4

10 nF

1 kV

1N5255B

VR2

28 V

R8*

21 kΩ

1%

C5

2.2 nF

250 VAC

T1

NC 8

1

3

R3

47 Ω

1/8 W

TNY174-180

D7

BYV28-200

C10

1000 µF

6

R7

20 Ω

4

2

5

C6
1 µF
60 V

UF4003

U2

PC817A

25 V

D6

VR3

BZX79-C11

11 V

R6
390 Ω
1/8 W

R4

2 kΩ

1/8 W

L2

Ferrite Bead

3.5 × 7.6 mm

C11

100 µF

25 V

+12 V, 1 A

J3

J4

RTN

Figure 12. TNY178P, 12 V, 1 A Universal Input Power Supply.

Applications Example

The circuit shown in Figure 12 is a low cost, high efciency, yback

power supply designed for 12 V, 1 A output from universal input using
the TNY178.

The supply features primary sensed output overvoltage latching

shutdown protection, high efciency (>80%), and very low no-load

consumption (<50 mW at 265 VAC). Output regulation is accom­plished using a simple Zener reference and optocoupler feedback.

The rectied and ltered input voltage is applied to the primary

winding of T1. The other side of the transformer primary is driven by
the integrated MOSFET in U1. Diode D5, C2, R1, R2, and VR1
comprise the clamp circuit, limiting the leakage inductance turn-off
voltage spike on the DRAIN pin to a safe value. The use of a
combination a Zener clamp and parallel RC optimizes both EMI and

energy efciency. Resistor R2 allows the use of a slow recovery, low
cost, rectier diode by limiting the reverse current through D5. The
selection of a slow diode also improves efciency and conducted EMI
but should be a glass passivated type, with a specied recovery time
of ≤ 2 ms.

The output voltage is regulated by the Zener diode VR3. When the
output voltage exceeds the sum of the Zener and optocoupler LED

forward drop, current will ow in the optocoupler LED. This will cause

the transistor of the optocoupler to sink current. When this current
exceeds the ENABLE pin threshold current the next switching cycle is
inhibited. When the output voltage falls below the feedback

PI-4773-010709

threshold, a conduction cycle is allowed to occur and, by adjusting
the number of enabled cycles, output regulation is maintained. As
the load reduces, the number of enabled cycles decreases, lowering
the effective switching frequency and scaling switching losses with

load. This provides almost constant efciency down to very light
loads, ideal for meeting energy efciency requirements.

As the TinySwitch-LT devices are completely self-powered, there is no
requirement for an auxiliary or bias winding on the transformer.
However by adding a bias winding, the output overvoltage protection

feature can be congured, protecting the load against open feedback

loop faults.

When an overvoltage condition occurs, such that bias voltage
exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION (BP/M)

pin voltage (28 V+5.85 V), current begins to ow into the BP/M pin.

When this current exceeds ISD the internal latching shutdown circuit in
TinySwitch-LT is activated. This condition is reset when the BP/M pin
voltage drops below 2.6 V after removal of the AC input. In the
example shown, on opening the loop, the OVP trips at an output of 17 V.

For lower no-load input power consumption, the bias winding may
also be used to supply the TinySwitch-LT device. Resistor R8 feeds
current into the BP/M pin, inhibiting the internal high-voltage current
source that normally maintains the BP/M pin capacitor voltage (C7)
during the internal MOSFET off time. This reduces the no-load
consumption of this design from 140 mW to 40 mW at 265 VAC.

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7

Rev. G 08/16

TNY174-180

In addition to the simple input pi lter (C1, L1, C2) for differential

mode EMI, this design makes use of E-Shield™ shielding techniques
in the transformer to reduce common mode EMI displacement
currents, and R2 and C4 as a damping network to reduce high
frequency transformer ringing. These techniques, combined with the
frequency jitter of TNY178, give excellent conducted and radiated
EMI performance with this design achieving >12 dBmV of margin to
EN55022 Class B conducted EMI limits.

For design exibility the value of C7 can be selected to pick one of

the 3 current limits options in U1. This allows the designer to select
the current limit appropriate for the application:

• Standard current limit (I

capacitor and is the normal choice for typical enclosed adapter

) is selected with a 0.1 mF BP/M pin

LIMIT

applications.

• When a 1 mF BP/M pin capacitor is used, the current limit is reduced

(I

or I

LI MI Tred

therefore improved efciency, but at the expense of maximum

-1) offering reduced RMS device currents and

LIMIT

power capability. This is ideal for thermally challenging designs
where dissipation must be minimized.

• When a 10 mF BP/M pin capacitor is used, the current limit is

increased (I
applications requiring higher peak power or continuous power

LIMITinc

or I

+1), extending the power capability for

LIMIT

where the thermal conditions allow.

Further exibility comes from the current limits between adjacent

TinySwitch-LT family members being compatible. The reduced
current limit of a given device is equal to the standard current limit of
the next smaller device and the increased current limit is equal to the
standard current limit of the next larger device.

Key Application Considerations

TinySwitch-LT Design Considerations

Output Power Table

The data sheet output power table (Table 1) represents the minimum
practical continuous output power level that can be obtained under
the following assumed conditions:

1. The minimum DC input voltage is 100 V or higher for 85 VAC input,

or 220 V or higher for 230 VAC input or 115 VAC with a voltage
doubler. The value of the input capacitance should be sized to
meet these criteria for AC input designs.

2. Efciency of 75%.

3. Minimum data sheet value of I

4. Transformer primary inductance tolerance of ±10%.

5. Reected output voltage (V

6. Voltage only output of 12 V with a fast PN rectier diode.

7. Continuous conduction mode operation with transient K

of 0.25.

8. Increased current limit is selected for peak and open frame power

columns and standard current limit for adapter columns.

9. The part is board mounted with SOURCE pins soldered to

sufcient area of copper and/or a heat sink is used to keep the

SOURCE pin temperature at or below 110 °C for P and G package
and 100 °C for D packaged devices.

2

f.

) of 135 V.

OR

* value

P

10. Ambient temperature of 50 °C for open frame designs and

40 °C for sealed adapters.

*Below a value of 1, KP is the ratio of ripple to peak primary current.
To prevent reduced power capability due to premature termination of
switching cycles a transient KP limit of ≥0.25 is recommended. This
prevents the initial current limit (I
MOSFET turn-on.

For reference, Table 2 provides the minimum practical power
delivered from each family member at the three selectable current
limit values. This assumes open frame operation (not thermally
limited) and otherwise the same conditions as listed above. These
numbers are useful to identify the correct current limit to select for a
given device and output power requirement.

Overvoltage Protection

The output overvoltage protection provided by TinySwitch-LT uses an
internal latch that is triggered by a threshold current of approximately

5.5 mA into the BP/M pin. In addition to an internal lter, the BP/M
pin capacitor forms an external lter providing noise immunity from

inadvertent triggering. For the bypass capacitor to be effective as a

high frequency lter, the capacitor should be located as close as

possible to the SOURCE and BP/M pins of the device.

For best performance of the OVP function, it is recommended that a
relatively high bias winding voltage is used, in the range of 15 V-30 V.
This minimizes the error voltage on the bias winding due to leakage
inductance and also ensures adequate voltage during no-load
operation from which to supply the BP/M pin for reduced no-load
consumption.

Selecting the Zener diode voltage to be approximately 6 V above the
bias winding voltage (28 V for 22 V bias winding) gives good OVP
performance for most designs, but can be adjusted to compensate

for variations in leakage inductance. Adding additional ltering can

be achieved by inserting a low value (10 W to 47 W) resistor in series
with the bias winding diode and/or the OVP Zener as shown by R7
and R3 in Figure 12. The resistor in series with the OVP Zener also
limits the maximum current into the BP/M pin.

Reducing No-load Consumption

As TinySwitch-LT is self-powered from the BP/M pin capacitor, there is
no need for an auxiliary or bias winding to be provided on the
transformer for this purpose. Typical no-load consumption when
self-powered is <150 mW at 265 VAC input. The addition of a bias
winding can reduce this down to <50 mW by supplying the Ti­nySwitch-LT from the lower bias voltage and inhibiting the internal
high-voltage current source. To achieve this, select the value of the
resistor (R8 in Figure 12) to provide the data sheet DRAIN supply
current. In practice, due to the reduction of the bias voltage at low
load, start with a value equal to 40% greater than the data sheet
maximum current, and then increase the value of the resistor to give
the lowest no-load consumption.

) from being exceeded at

INIT

8

Rev. G 08/16

www.power.com

TNY174-180

Peak Output Power Table

Output Power Table

Product

I

-1 I

LIMIT

TNY174P 9.1 W 10.9 W 9.1 W 7.1 W 8.5 W 7.1 W
TNY175P 10.8 W 12 W 15.1 W 8.4 W 9.3 W 11.8 W
TNY176P 11.8 W 15.3 W 19.4 W 9.2 W 11.9 W 15.1 W
TNY177P 15.1 W 19.6 W 23.7 W 11.8 W 15.3 W 18.5 W
TNY178P 19.4 W 24 W 28 W 15.1 W 18.6 W 21.8 W
TNY179P 23.7 W 28.4 W 32.2 W 18.5 W 22 W 25.2 W
TNY180P 28 W 32.7 W 36.6 W 21.8 W 25.4 W 28.5 W

Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.

230 VAC ± 15% 85-265 VAC

I

LIMIT

+1 I

LIMIT

-1 I

LIMIT

LIMIT

I

LIMIT

+1

Audible Noise

The cycle skipping mode of operation used in TinySwitch-LT can
generate audio frequency components in the transformer. To limit
this audible noise generation the transformer should be designed

such that the peak core ux density is below 3000 Gauss (300 mT).

Following this guideline and using the standard transformer produc­tion technique of dip varnishing practically eliminates audible noise.
Vacuum impregnation of the transformer should not be used due to
the high primary capacitance and increased losses that result. Higher

ux densities are possible, however careful evaluation of the audible

noise performance should be made using production transformer
samples before approving the design.

Ceramic capacitors that use dielectrics such as Z5U, when used in
clamp circuits, may also generate audio noise. If this is the case, try
replacing them with a capacitor having a different dielectric or

construction, for example a lm type.

TinySwitch-LT Layout Considerations

Layout

See Figure 13 for a recommended circuit board layout for TinySwitch-LT.

Single Point Grounding

Use a single point ground connection from the input lter capacitor to

the area of copper connected to the SOURCE pins.

Bypass Capacitor (CBP)

The BP/M pin capacitor should be located as near as possible to the
BP/M and SOURCE pins.

ENABLE Pin

Keep traces connected to the EN pin short and, as far as is practical,
away from all other traces and nodes above source potential including,
but not limited to, the BYPASS and DRAIN pins.

Primary Loop Area

The area of the primary loop that connects the input lter capacitor,

transformer primary and TinySwitch-LT together should be kept as
small as possible.

Primary Clamp Circuit

A clamp is used to limit peak voltage on the DRAIN pin at turn off.
This can be achieved by using an RCD clamp or a Zener (~200 V) and
diode clamp across the primary winding. In all cases, to minimize
EMI, care should be taken to minimize the circuit path from the clamp
components to the transformer and TinySwitch-LT.

Thermal Considerations

The four SOURCE pins are internally connected to the IC lead frame
and provide the main path to remove heat from the device. There­fore all the SOURCE pins should be connected to a copper area
underneath the TinySwitch-LT to act not only as a single point
ground, but also as a heat sink. As this area is connected to the quiet
source node, this area should be maximized for good heat sinking.
Similarly for axial output diodes, maximize the PCB area connected to
the cathode.

Y Capacitor

The placement of the Y capacitor should be directly from the primary

input lter capacitor positive terminal to the common/return terminal

of the transformer secondary. Such a placement will route high
magnitude common mode surge currents away from the TinySwitch-LT

device. Note – if an input π (C, L, C) EMI lter is used then the
inductor in the lter should be placed between the negative terminals
of the input lter capacitors.

Optocoupler

Place the optocoupler physically close to the TinySwitch-LT to
minimizing the primary-side trace lengths. Keep the high current,
high-voltage drain and clamp traces away from the optocoupler to
prevent noise pick up.

Output Diode

For best performance, the area of the loop connecting the secondary

winding, the output diode and the output lter capacitor, should be
minimized. In addition, sufcient copper area should be provided at

the anode and cathode terminals of the diode for heat sinking. A
larger area is preferred at the quiet cathode terminal. A large anode
area can increase high frequency radiated EMI.

www.power.com

9

Rev. G 08/16

TNY174-180

+

HV

Input Filter Capacitor

-

D

S

S

BP/M

TOP VIEW

S

S

TinySwitch-LT

EN

Figure 13. Recommended Circuit Board Layout for TinySwitch-LT.

Safety Spacing

Capacitor

PRI

BIAS

Y1-

T

r

a

Maximize hatched copper
areas ( ) for optimum
heat sinking

Output

Rectier

Output Filter

SEC

Capacitor

n

PRI

s

f

o

r

m

BIAS

C

BP

e

r

Opto-

coupler

DC

OUT

+-

PI-4779-073107

PC Board Leakage Currents

TinySwitch-LT is designed to optimize energy efciency across the

power range and particularly in standby/no-load conditions. Current
consumption has therefore been minimized to achieve this perfor­mance. The EN pin for example operates with very low threshold
current levels and it is therefore recommended to limit parasitic
currents into and out of the EN pin to levels below 1 mA.

Parasitic leakage currents into the EN pin are normally well below
this 1mA level when PC board assembly is in a well controlled
production facility. However, high humidity conditions together with

board and/or package contamination, either from no-clean ux or

other contaminants, can reduce the surface resistivity enough to

allow parasitic currents >1 mA to ow into the EN pin. These
currents can ow from higher voltage exposed solder pads close to

the EN pin such as the BP/M pin solder pad.

If the contamination levels in the PC board assembly facility are
unknown, the application is open frame or operates in a high
pollution degree environment, then an optional 390 kW resistor
should be added from EN pin to SOURCE pin to ensure that the
parasitic leakage current into the EN pin is low.

Note that typical values for surface insulation resistance (SIR) where

no-clean ux has been applied according to the suppliers’ guidelines
are >>10 MW and do not cause this issue.

Quick Design Checklist

As with any power supply design, all TinySwitch-LT designs should

be veried on the bench to make sure that component specications

are not exceeded under worst case conditions. The following
minimum set of tests is strongly recommended:

1. Maximum drain voltage – Verify that the worst case V

exceed 650 V at highest input voltage and peak (overload)
output power.

2. Maximum drain current – At maximum ambient temperature,

maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer satu­ration and excessive leading edge current spikes at start-up.
Repeat under steady state conditions and verify that the leading
edge current spike event is below I
t

. Under all conditions, the maximum drain current should

LEB(Min)

be below the specied absolute maximum ratings.

at the end of the

LI MI T(M in)

3. Thermal Check – At specied maximum output power, minimum

input voltage and maximum ambient temperature, verify that the

temperature specications are not exceeded for TinySwitch-LT,

transformer, output diode, and output capacitors. Enough
thermal margin should be allowed for part-to-part variation of the
R

of TinySwitch-LT as specied in the data sheet. Under

DS(O N)

low-line, maximum power, a maximum TinySwitch-LT SOURCE pin
temperature of 110 °C is recommended to allow for these
variations.

does not

DS

10

Rev. G 08/16

www.power.com

TNY174-180

Absolute Maximum Ratings

DRAIN Voltage .................................. .......... .............-0.3 V to 650 V

DRAIN Peak Current: TNY174 ............................. 400 (750) mA

TNY175 ........................... 560 (1050) mA

TNY176 ........................... 720 (1350) mA

TNY177 ........................... 880 (1650) mA

TNY178 ..........................1040 (1950) mA

(1,5 )

TNY179 ..........................1200 (2250) mA

TNY180 ..........................1360 (2550) mA

(2)

(2)

(2)

(2)

(2)

(2)

(2)

ENABLE Voltage ........................................................... -0.3 V to 9 V

ENABLE Current ..................................................................100 mA

BP/M Voltage ....................................................-0.3 V to 9 V

Storage Temperature ...............................................-65 °C to 150 °C

Operating Junction Temperature

(3)

............................-40 °C to 150 °C

Thermal Impedance

Thermal Impedance: P Package:

(qJA) ................................... 70 °C/W

(1)

(qJC)

.................................................... 11 °C/W

D Package:

(qJA) ................................. 100 °C/W

(2)

(qJC)

..................................................... 30 °C/W

(2)

; 60 °C/W

(2)

; 80 °C/W

Lead Temperature

(4)

.............................................................. 260 °C

Notes:

1. All voltages referenced to SOURCE, TA = 25 °C.

2. The higher peak DRAIN current is allowed while the
DRAIN voltage is simultaneously less than 400 V.

3. Normally limited by internal circuitry.

4. 1/16 in. from case for 5 seconds.

5. Maximum ratings specied may be applied one at a time,

without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.

Notes:

1. Measured on the SOURCE pin close to plastic interface.

(3)

2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.

3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

(3)

Parameter Symbol

Control Functions

Output Frequency
in Standard Mode

Maximum Duty Cycle DC

ENABLE Pin
Upper Turn-Off
Threshold Current

ENABLE Pin Voltage V

DRAIN Supply Current

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 14

Min Typ Max Units

(Unless Otherwise Specied)

f

OSC

MAX

I

DIS

TJ = 25 °C

See Figure 4

S1 Open 62 65 %

IEN = 25 mA 1.8 2.2 2.6

EN

I

S1

EN Current > I

IEN = -25 mA 0.8 1.2 1.6

(MOSFET Not Switching)

DIS

See Note A

EN Open (MOSFET

I

S2

Switching at f

See Note B

OSC

)

Average 124 132 140

Peak-to-peak Jitter 8

-15 0 -115 -90 mA

290 mA

TNY174P/D 275 360

TNY175P/D 295 400

TNY176 P/D 310 430

TNY177P/D 365 460

TNY178P/D 445 595

TNY179P 510 640

TNY180P 630 760

kHz

V

mA

www.power.com

11

Rev. G 08/16

TNY174-180

Parameter Symbol

Control Functions (cont.)

BP/M Pin Charge
Current

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 14

Min Typ Max Units

(Unless Otherwise Specied)

V

= 0 V,

I

CH1

I

CH2

BP/M

TJ = 25 °C

See Note C, D

V

= 4 V,

BP/M

TJ = 25 °C

See Note C, D

TNY174 -6 -3.8 -1.8

TNY175-179 -8.3 -5.4 -2.5

TNY180 -9.7 -6.8 -3.9

mA

TNY174 -4.1 -2. 3 -1

TNY175-179 -5 -3.5 -1. 5

TNY180 -6.6 -4.6 -2 .1

BP/M Pin Voltage V

BP/M Pin Voltage
Hysteresis

BP/M Pin Shunt Voltage V

Circuit Protection

Standard Current Limit
(BP/M Capacitor =

0.1 mF) See Note D

V

I

BP/M

BP/M H

SHUNT

LIMIT

See Note C 5.6 5.85 6.15 V

IBP = 2 mA 6.0 6.4 6.7 V

di/dt = 50 mA/ms

TJ = 25 °C

See Note E

di/dt = 55 mA/ms

TJ = 25 °C

See Note E

di/dt = 70 mA/ms

TJ = 25 °C

See Note E

di/dt = 90 mA/ms

TJ = 25 °C

See Note E

di/dt = 110 mA/ms

TJ = 25 °C

See Note E

0.80 0.95 1.20 V

TNY174P 233 250 267

TNY174D 233 250 273

TNY175P 256 275 294

TNY175D 256 275 300

TNY176P 326 350 374

TNY176D 326 350 382

TNY177P 419 450 481

TNY177D 419 450 491

TNY178P 512 550 588

TNY178D 512 550 599

mA

12

Rev. G 08/16

di/dt = 130 mA/ms

TJ = 25 °C

See Note E

di/dt = 150 mA/ms

TJ = 25 °C

See Note E

TNY179P 605 650 695

TNY180P 698 750 802

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Parameter Symbol

Circuit Protection (cont.)

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 14

(Unless Otherwise Specied)

di/dt = 50 mA/ms

TJ = 25 °C

See Note E

TNY174P

TNY174D 196 210 237

TNY174-180

Min Typ Max Units

196 210 233

Reduced Current Limit
(BP/M Capacitor =
1 mF) See Note D

I

LI MI Tred

di/dt = 55 mA/ms

TJ = 25 °C

See Note E

di/dt = 70 mA/ms

TJ = 25 °C

See Notes E

di/dt = 90 mA/ms

TJ = 25 °C

See Notes E

di/dt = 110 mA/ms

TJ = 25 °C

See Notes E

di/dt = 130 mA/ms

TJ = 25 °C

See Notes E

di/dt = 150 mA/ms

TJ = 25 °C

See Notes E

di/dt = 50 mA/ms

TJ = 25 °C

See Notes E, F

TNY175P 233 250 277

TNY175D 233 250 283

TNY176P 256 275 305

TNY176D 256 275 311

TNY177P 326 350 388

TNY177D 326 350 396

TNY178P 419 450 499

TNY178D 419 450 508

TNY179P 512 550 610

TNY180P 605 650 721

TNY174P 196 210 233

TNY174D 196 210 237

mA

Increased Current Limit
(BP/M Capacitor =
10 mF) See Note D

www.power.com

I

LIMITinc

di/dt = 55 mA/ms

TJ = 25 °C

See Notes E

di/dt = 70 mA/ms

TJ = 25 °C

See Notes E

di/dt = 90 mA/ms

TJ = 25 °C

See Notes E

di/dt = 110 mA/ms

TJ = 25 °C

See Notes E

di/dt = 130 mA/ms

TJ = 25 °C

See Notes E

di/dt = 150 mA/ms

TJ = 25 °C

See Notes E

TNY175P 326 350 388

TNY175D 326 350 396

TNY176P 419 450 499

TNY176D 419 450 509

TNY177P 512 550 610

TNY177D 512 550 622

TNY178P 605 650 721

TNY178D 605 650 734

TNY179P 698 750 833

TNY180P

791 850 943

mA

13

Rev. G 08/16

TNY174-180

Parameter Symbol

Circuit Protection (cont.)

Power Coefcient I2f

Initial Current Limit I

Leading Edge
Blanking Time

Current Limit Delay t

Thermal Shutdown
Temperature

Thermal Shutdown
Hysteresis

BP/M Pin Shutdown
Threshold Current

BP/M Pin Power-Up
Reset Threshold Voltage

Output

t

T

T

I

V

BP/M(RESET)

INIT

LEB

ILD

SDH

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 14

Min Typ Max Units

(Unless Otherwise Specied)

Standard Current

Limit, I2f = I

× f

OSC( TYP)

Reduced Current Limit,

I2f = I

LI MI Tred( TYP)

× f

OSC( TYP)

Increased Current Limit,

I2f = I

LIMITinc(TYP)

× f

OSC( TYP)

LIMI T(TYP)

2

2

2

See Figure 19

TJ = 25 °C, See Note G

TJ = 25 °C

See Note G

TNY174-180P

TNY174-178D

TNY174-180P

TNY174-178D

TNY174-180P

TNY174-178D

0.9 ×
I2f

0.9 ×
I2f

0.9 ×
I2f

0.9 ×
I2f

0.9 ×
I2f

0.9 ×
I2f

0.75 ×

I

LIMIT(MIN)

170 215 ns

TJ = 25 °C

See Note G, H

SD

135 142 150 °C

I2f

I2f

I2f

I2f

I2f

I2f

150 ns

75 °C

SD

4 6.5 9 mA

1.6 2.6 3.6 V

TNY174P/D
ID = 25 mA

TJ = 25 °C 28 32

TJ = 100 °C 42 48

1.12 ×
I2f

1.16 ×
I2f

1.16 ×
I2f

1.20 ×
I2f

1.16 ×
I2f

1.20 ×
I2f

A2Hz

mA

ON-State
Resistance

14

Rev. G 08/16

R

DS(O N)

TNY175P/D
ID = 28 mA

TNY176 P/D
ID = 35 mA

TJ = 25 °C 19 22

W

TJ = 100 °C 29 33

TJ = 25 °C 14 16

TJ = 100 °C 21 24

www.power.com

Parameter Symbol

Output (cont.)

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 14

(Unless Otherwise Specied)

TNY177P/D
ID = 45 mA

TJ = 25 °C 7. 8 9.0

TJ = 100 °C 11.7 13.5

TNY174-180

Min Typ Max Units

TJ = 25 °C 5.2 6.0

TJ = 100 °C 7. 8 9.0

TJ = 25 °C 3.9 4.5

TJ = 100 °C 5.8 6.7

TJ = 25 °C 2.6 3.0

TJ = 100 °C 3.9 4.5

TNY174-176 50

ON-State Resistance R

DS(O N)

TNY178P/D
ID = 55 mA

TNY179P

ID = 65 mA

TNY180P

ID = 75 mA

V

= 6.2 V

BP/M

VEN = 0 V

OFF-State Drain
Leakage Current

Breakdown Voltage BV

I

I

DSS1

DSS2

DSS

VDS = 520 V
TJ = 125 °C

See Note I

V

= 6.2 V

BP/M

VEN = 0 V

VBP = 6.2 V, VEN = 0 V,
See Note J, TJ = 25 °C

TNY179-18 0 200

VDS = 375 V,

TJ = 50 °C

15

See Note G, I

650 V

DRAIN Supply Voltage 50 V

Auto-Restart ON-Time
at f

OSC

Auto-Restart
Duty Cycle

DC

t

AR

AR

TJ = 25 °C

See Note K

64 ms

TJ = 25 °C 3 %

W

mATNY177-178 100

www.power.com

15

Rev. G 08/16

TNY174-180

NOTES:

A. I

is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions.

S1

Total device consumption at no-load is the sum of IS1 and I

B. Since the output MOSFET is switching, it is difcult to isolate the switching current from the supply current at the DR AIN. An alternative is

to measure the BP/M pin current at 6.1 V.

C. BP/M pin is not intended for sourcing supply current to external circuitry.

D. To ensure correct current limit it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M capacitor

value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The
minimum and maximum capacitor values are guaranteed by characterization.

Nominal BP/M Pin

Cap Value

0.1 mF -60% +10 0%

1 mF -50% +10 0 %

10 mF -50% NA

E. For current limit at other di/dt values, refer to Figure 21.

F. TNY174 does not set an increased current limit value, but with a 10 mF BP/M pin capacitor the current limit is the same as with a 1 mF BP/M

pin capacitor (reduced current limit value).

G. This parameter is derived from characterization.

H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I

I. I

is the worst-case OFF-state leakage specication at 80% of BV

DSS1

specication under worst-case application conditions (rectied 265 VAC) for no-load consumption calculations.

J. Breakdown voltage may be checked against minimum BV

minimum BV

DSS

.

K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).

.

DSS2

Tolerance Relative to Nominal

Capacitor Value

Min MAX

specication.

LIMIT

and maximum operating junction temperature. I

DSS

specication by ramping the DRAIN pin voltage up to but not exceeding

DSS

is a typical

DSS2

16

Rev. G 08/16

www.power.com

Figure 14. General Test Circuit.

0.8

PI-4279-013006

PI-4774-073107

0.1 µF

10 V

50 V

470 Ω

5 W

S2

470 Ω

NOTE: This test circuit is not applicable for current limit or output characteristic measurements.

S D

EN

S

S

BP/M

S

S1

DC

MAX

(internal signal)

TNY174-180

t

P

Figure 15. Duty Cycle Measurement.

EN

V

DRAIN

1

tP =

f

OSC

Figure 16. Output Enable Timing.

t

EN

PI-4780-073107

Figure 17. Current Limit Envelope.

www.power.com

17

Rev. G 08/16

TNY174-180

1.1

1.0

0.9

-50 -25 0255075 100 125 150

Junction Temperature (°C)

Breakdown Voltage

(Normalized to 25 °C)

PI-2213-012301

DRAIN Voltage (V)

Drain Current (mA)

300

250

200

100

50

150

0

0 2 4 6 8 10

T

CASE

=25 °C

T

CASE

=100 °C

PI-4776-060915

TNY174 1.0
TNY175 1.5
TNY176 2.0
TNY177 3.5
TNY178 5.5
TNY179 7.3
TNY180 11

Scaling Factors:

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1 2 3 4

Normalized di/dt

PI-4775-073107

Normalized Current Limit

TNY174 50 mA/µs
TNY175 55 mA/µs
TNY176 70 mA/µs
TNY177 90 mA/µs
TNY178 110 mA/µs
TNY179 130 mA/µs
TNY180 150 mA/µs

Normalized

di/dt = 1

Note: For the
normalized current
limit value, use the
typical current limit
specified for the
appropriate BP/M
capacitor.

Drain Voltage (V)

Drain Capacitance (pF)

PI-4083-082305

0 100 200 300 400 500 600

1

10

100

1000

TNY174 1.0
TNY175 1.5
TNY176 2.0
TNY177 3.5
TNY178 5.5
TNY179 7.3
TNY180 11

Scaling Factors:

Temperature (°C)

PI-4102-010906

1.2

Standard Current Limit

(Normalized to 25

1.2

Junction Temperature (°C)

PI-4280-012306

Output Frequency

(Normalized to 25

Typical Performance Characteristics

1.0

°C)

0.8

0.6

0.4

0.2

0

-50 -25025 50 75 100 125

Figure 18. Breakdown vs. Temperature.

1

°C)

0.8

0.6

0.4

0.2

0

-50 050 100 150

Figure 20. Standard Current Limit vs. Temperature.

Figure 19. Frequency vs. Temperature.

Figure 21. Current Limit vs. di/dt.

18

Rev. G 08/16

Figure 22. Output Characteristic.

Figure 23. C

vs. Drain Voltage.

OSS

www.power.com

Typical Performance Characteristics (cont.)

50

30

40

10

20

0

0 200 400 600

DRAIN Voltage (V)

Power (mW)

PI-4778-073107

TNY174 1.0
TNY175 1.5
TNY176 2.0
TNY177 3.5
TNY178 5.5
TNY179 7.3
TNY180 11

Scaling Factors:

Figure 24. Drain Capacitance Power.

TNY174-180

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19

Rev. G 08/16

TNY174-180

Notes:

1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.

2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.

3. Dimensions shown do not include mold flash or other
protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.

4. Pin locations start with Pin 1, and continue counter-clock­ wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.

5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).

6. Lead width measured at package body.

7. Lead spacing measured with the leads constrained to be
perpendicular to plane T.

.008 (.20)
.015 (.38)

.300 (7.62) BSC

(NOTE 7)

.300 (7.62)
.390 (9.91)

.356 (9.05)
.387 (9.83)

.240 (6.10)
.260 (6.60)

.125 (3.18)
.145 (3.68)

.057 (1.45)
.068 (1.73)

.118 (3.00)
.140 (3.56)

.015 (.38)
MINIMUM

.048 (1.22)
.053 (1.35)

.100 (2.54) BSC

.014 (.36)
.022 (.56)

-E-

Pin 1

SEATING
PLANE

-D-

-T-

P08C

PDIP-8C (P Package)

PI-3933-081716

D S

.004 (.10)

⊕

T E D S

.010 (.25) M

⊕

(NOTE 6)

.137 (3.48)

MINIMUM

20

Rev. G 08/16

www.power.com

SO-8C (D Package)

TNY174-180

0.10 (0.004)

2X

1.35 (0.053)

1.75 (0.069)

0.10 (0.004)

0.25 (0.010)

3.90 (0.154) BSC

2

D

C

Pin 1 ID

1.27 (0.050) BSC

B

4

1.25 - 1.65

(0.049 - 0.065)

2

4.90 (0.193) BSC

A

8

1

4

5

4

0.10 (0.004)

D

6.00 (0.236) BSC

2X

7X 0.31 - 0.51 (0.012 - 0.020)

0.25 (0.010)

7X

SEATING PLANE

C

A-B

C

0.20 (0.008)

M

0.10 (0.004)

2X

C A-B D

C

C

SEATING
PLANE

1.04 (0.041) REF

C

0.40 (0.016)

1.27 (0.050)

H

0.17 (0.007)

0.25 (0.010)

DETAIL A

o

0 - 8

0.25 (0.010)
BSC

DETAIL A

GAUGE
PLANE

Reference
Solder Pad
Dimensions

2.00 (0.079)

D07C

1.27 (0.050)

Part Ordering Information

TNY 178 P N - TL

+

Notes:

1. JEDEC reference: MS-012.

4.90 (0.193)

+

+

+

0.60 (0.024)

• TinySwitch Product Family

• Series Number

• Package Identier

P Plastic DIP-8C

D Plastic Surface Mount SO-8C

• Lead Finish

N Pure Matte Tin (Pb-Free) (Not available in D Package)

G RoHS Compliant and Halogen Free (D Package only)

• Tape & Reel and Other Options

Blank Standard Conguration

TL Tape & Reel, 2.5 k pcs for D Package. Not available for P Package.

2. Package outline exclusive of mold flash and metal burr.

3. Package outline inclusive of plating thickness.

4. Datums A and B to be determined at datum plane H.

5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.

PI-4526-040110

www.power.com

21

Rev. G 08/16

Revision Notes Date

A Initial Release 08/07

B Minor text change 08/10/07

Updated Part Ordering Information section with Halogen Free and added D package part.

C

Corrected electrical symbol mF in three locations under Circuit Protection in Parameter Table.

D Added TNY177D. 08/12

E Added TNY178D. 09/13

F Updated with new Brand Style. 12/15

G Updated PDIP-8C (P Package) per PCN-16232. 08/16

07/09
03/10

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARR ANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILIT Y,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose

failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signicant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS,
HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of
Power Integrations, Inc. Other trademarks are propert y of their respective companies. ©2016, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters

5245 Hellyer Avenue
San Jose, CA 95138, USA.
Main: [phone]
Customer Service:
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

China (Shanghai)

Rm 2410, Charity Plaza, No. 88
North Caoxi Road
Shanghai, PRC 200030
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

China (Shenzhen)

17/F, Hivac Building, No. 2, Keji Nan

8th Road, Nanshan District,
Shenzhen, China, 518057
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Germany

Lindwurmstrasse 114
80337 Munich
Germany
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Germany

HellwegForum 1
59469 Ense
Germany
Tel: [phone]
e-mail: igbt-driver.sales@
power.com

India

#1, 14th Main Road
Vasanthanagar
Bangalore-560052 India
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Italy

Via Milanese 20, 3rd. Fl.
20099 Sesto San Giovanni (MI) Italy
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Japan

Kosei Dai-3 Bldg.
2-12-11, Shin-Yokohama,
Kohoku-ku
Yokohama-shi, Kanagawa
222-0033 Japan
Ph o ne: [phone]
Fa x: [phone]

e-mail: [e-mail]

Korea

RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Singapore

51 Newton Road
#19-01/05 Goldhill Plaza
Singapore, 308900
Phone: [phone]
Fax: [phone]
e-mail: [e-mail]

Taiwan

5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei 11493, Taiwan R.O.C.
Phone: [phone]
Fax: [phone] - 4550
e-mail: [e-mail]

UK

Cambridge Semiconductor,
a Power Integrations company
Westbrook Centre, Block 5, 2nd Floor
Milton Road
Cambridge CB4 1YG
Phone: [phone]
e-mail: [e-mail]

Mouser Electronics

Authorized Distributor

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Power Integrations:
TNY174DG TNY175DG TNY178DG TNY180PG TNY177DG TNY179PN TNY176DG TNY177PG TNY175PN

TNY174DG-TL TNY178PG TNY175PG TNY179PG TNY174PN TNY175DG-TL TNY176DG-TL TNY177DG-TL
TNY177PN TNY178DG-TL TNY180PN TNY176PN TNY176PG TNY178PN TNY174PG