Datasheet TMXF281553BAL-2-DB Datasheet (Lucent Technologies)

Download

Page 1

Preliminary Data Sheet

May 2001

TMXF28155 Super Mappe r

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Features

■

Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications.

■

Implementation sup ports both linear (1 + 1, unprotected) and ring (UPSR) network topol ogies.

■

Provides full termination of up to 21 E1, 28 T1, or 28 J1.

■

Low power 3.3 V supply.

■

–40 °C to +85 °C industrial temperature range.

■

456-pin ball grid array (PBGA) package.

■

Complies with

Bellcore*

, IT U,

ANSI

†

, ETSI and Japanese TTC standards: GR-253-CORE, GR-499, (A T T) TR-62411, ITU-T G.707, G.704, G.706, G.783, G.962, G.964, G.965, Q.542, T1.105, JT-G704, JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1, ETS 300 011, T1.107, T1.404.

1.1 SONE T/S D H Inte rf a ce

■

Termination of a single 155 Mbits/s STS-3/STM-1 or single 51 Mbits/s STS-1/STM-0.

■

Built-in clock and data recovery circuit at 155 Mbits/s STS-3/STM-1 interface (can be deselected if external clock recovery is provided).

■

Supports overhead processing for all transport and path overhead bytes.

■

Optional insertion and extraction of overhead bytes via a serial transport overhead access channel. Configurable as dedicated DCC channels.

■

Software controlled linear 1 + 1 protecti on via dedicated interface to protection card.

■

Full path termination and SPE extraction/insertion.

■

SONET/SDH compliant condition and alarm reporting.

■

Built-in diagnostic loopback modes.

■

8 kHz line frame sync output.

Bellcore

is now

Telcordia Technolog ie s. T elcordia Technologies

is a

trademark of Telcordia Technologies, Inc.

†

ANSI

is a registered trademark of American National Standards

Institute, Inc.

1.2 STS/STM Pointer Interpreter

■

Interprets STS/AU/TU-3 pointers.

■

Syn chron i zes 8 kHz f ra me and 2 kH z superframe to system/shelf timing reference by setting the transmit STS-3/STM-1 pointers to a fixed value of 522.

■

Monitors/terminates SPE path overhead.

1.3 Telecom Bus Inte rf a ce

■

Telecom bus interface to mate devices including clock, data[ 8 ], parity, SPE-, J0-, J1-, and V1 timing indicator.

■

Line and path RDI and REI signals passed to mate devices.

■

Three Super Mapper devices, two configured as mate devices, provide full termina tion of an STS-3/STM-1. A three-chip solution to terminate 84 DS1s/J1s or 63 E1s.

1.4 VT Termination/Gen e ra tio n (x 28 /x 21 )

■

Monitors/terminates VT pa th overhead for 28 VT1.5/TU-11 or 21 VT2/TU-12.

■

Synchronizes VT/TU SPE to system/shelf timing reference by setting the transmit VT/TU pointers to fixed values for asynchronous mapping or by dynamically changing the transmit VT/TU pointers for byte synchronous mapping.

■

Fixed pointer generation in transmit side for asynchronous mapping.

■

Dynamic pointer generation in transmit side for bytesynchronous mapping.

1.5 Mapping/Multiplexing Modes ( x 28 /x 21 )

■

Maps DS3 clear channel or framed signal into STS-1 or TUG-3.

■

Maps T1/E1/J1 into VT/TU (including DS1 into TU-12).

■

Support s asy nchronous, byte-synchronous, and bitsynchronous mapping.

Page 2

2 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

1 Features

(continued)

■

Support s UP S R applications via the dedicated ring interface and a n external tributary selector.

■

Support s all valid T1/E1/J1 multiplexing structures into STS-1 and STS-3/STM-1:

— STS-3/STS-1/SPE/VTG/VTx — STM-1/AU-3/TUG-2/TU-1x/VC-1x — STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x

■

Allows grooming of VTs/TUs in granularity of TUG-2s within the STS-3/STM-1 signal.

■

Supports J2 trace identifier monitoring/inse rtion.

■

Configurable VT/TU slot selection for DS1, E1, and J1 insertion and drop.

■

Automatic receive monitor functions include VT/TU RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.

■

Complies with GR-253-CORE, GR-499, ITU-T G.707, G.704, G.783, T1.105, JT-G707, ETS 300 417-1-1.

1.6 M13 F ea t ur es

■

Configurable multiplexer/demultiplexer for 28 DS 1 signals, 21 E1 signals, or 7 DS2 signals to/from a DS3 signal.

■

Operates in either M2 3 or C-bit parity mode.

■

Provisionable time slot selection for DS1, E1, and DS2 insertion or drop.

■

Full alarm monitoring and generation (LOS, BPV, EXZ, OOF, S E F, AIS, RAI, FEAC, P-bit and C-bit parity errors, FEBE).

■

HDLC transmitter with 128-byte data buffer and HDLC receiver with 128-byte data FIFO for the C-bit parity path maintenanc e data lin k.

■

DS3, DS2, DS1, and E1 loopback and loopback request generation.

■

Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR 499, G.747, and G.775.

1.7 DS3/DS2/DS1/E1 Cross Connect

■

Highly configurable interconnect for up to 28 DS1 or 21 E1 signals to/from the framer, external pins, M13, or VT mappers.

■

Support s up to seven DS2 signals to/from the external pins or M13.

■

Sources may be broadcast, looped back, or routed to/from a test-pattern generator or monitor.

■

Any DS1 or E1 channel may be routed through the jitte r a t tenua to r.

■

DS3 may be configured for the M13 to interconnect with the SPE, or external I/O to interconnect with the M13 or SPE.

1.8 Jitter Attenuation

■

PLL-free receive operation using built-in digital jitter attenuator (in VT/VC mode or M13 mode).

■

Configurable to meet jitter and MTIE requirements.

1.9 PDH Interfaces

■

One DS3, 7x DS2.

■

x28/x21 framed or unframed DS1 or E1 interfaces.

■

One additional dedicated protection channel for DS2/DS1/E1.

1.10 T1/E1/J1 Framing Features (x28/x21)

■

x28/x21 T1/E1/J1 channels.

■

Line coding: B8ZS, HDB3, ZCS, AMI, and CMI (JJ20-11 ).

■

T1 framing modes: ESF, D4,

SLC

-96, T1 DM DDS,

and SF (F

only).

■

E1 framing: G.704 basic and CRC-4 multiframe consistent with G.706.

■

J1 framing modes: J ESF (Japan).

■

Supports T1 and E1 unframed and transparent transmission format.

■

T1 signaling modes: transparent; register and system access for ESF 2-state, 4-state, and 16-state; D4 2-state, 4-state, and 16-state;

SLC

-96 2-state, 4-state, and 16-state; J-ESF handling groups maintenance and signaling; VT 1.5 SPE 2, 4, 16 state.

■

E1 signaling modes: transparent; register and system access for entire TS16 multiframe structure as per ITU G.732.

■

Signaling debounce and change of state interrupt.

■

V5.2 Sa7 processing.

Page 3

3Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Features

(continued)

■

Alarm reporting and performance monitoring per AT&T,

ANSI

, ITU-T, and ETSI standards.

■

Facility da ta link featur e s :

— HDLC or transparent access for either ESF or

DDS + FDL frame formats.

— Register/stack access for

SLC

-96 transmit and re-

ceive data.

— Extended superframe (ESF): automatic transmis-

sion of the ESF performance report messages (PRM). Automatic transmission of the

ANSI

T1.403 ESF performance report messages. Automatic detection and transmission of the

ANSI

T1.403 ESF FDL bit-oriented codes.

— Register/stack access for all CEPT Sa-bits trans-

mit and receive data.

■

HDLC features:

— HDLC or transparent mode. — Programmable logical channel assignment: any

time slot, any bit for ISDN D-channel, also inserts/ extracts C-channels for V5.1, V5.2 interfaces.

— 64 logical channels in both transmit and receive di-

rection (any framing format).

— Maximum channel data rate: 64 kbits/s. — Minimum channel data rate: 4 kbits/s (DS1-FDL or

E1 Sa bit).

— 128-byte FIFO per channel in both transmit and re-

ceive direction.

— Tx to Rx loopback supported.

■

System interfaces:

— Concentration highway interface: Single clock and

frame sync s i gnals; programmable clock rates at

2.048 MHz, 4.096 MHz, 8.192 MH z , and

16.384 MHz; programmable data rates at 2.048 Mbits/s,

4.096 Mbits/s, and 8.192 Mbits/s; programmable clock edges and bit/byte offsets.

— Parallel system bus interface at 19.44 MHz for

data and signaling: single clock and frame sync signals.

— Time-division multiplex data rate serial interface at

1.544 MHz or 2.048 MHz. Twenty-eight receive data, clock, and frame sync signals. Twenty-eight transmit data signals with a global clock and frame sync.

— Network serial multiplexed interface minimal pin

count serial interface at 51.84 MHz optimized for data and IMA applications.

1.11 System Test and Maintenance

■

A variety of loopback modes implemented on SONET/SDH side as well as on framer level.

■

Built-in test pattern generator and monitor configurable for simultaneously testing E1, DS1, DS2, and DS3 (one channel each).

Microprocessor Interface

■

20-bit address and 16-bit data interface with 16 MHz to 66 MHz read and write access.

■

Compatible with most industry-standard processors.

Chip Testing and Maintenance

■

IEEE

* 1149.1 JTAG boundary scan.

Interface to Other Agere ME Devices

Seamless interface to the following Agere Systems ’ devices:

■

TADM042G5.

IEEE

is a registered trademark of the Institute of Electrical and

Electr onics Engineers, Inc.

Page 4

4 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

Table of Contents

By Major Sections

Contents Page

Features ...................................................................................................................................................................1

Product De scription ............ ......... .......... ................ .......... ......... ......................................... .......................................5

Preface ...................................................................................................................................................................5

Interface Specific a ti o n s ...... ......... ................................. .......... ......... .................................. .......................................8

Pin Information .......................................................................................................................................................8

Electrical Characteristics ....................... ................. ................ ................................. .............................................33

Timing Characteristics .........................................................................................................................................37

Ordering Inform ation ............................................................................................................................................61

Register Description ...............................................................................................................................................62

Microprocessor Interface and Global Control and Status Registers .... .................. ................. ....................... ......62

TMUX Registers ............. ......... ......... ....................................................................................................................75

SPE Mapper Registers ...................................................................................................................................... 1 33

VT/TU Mapper Registers ...................................................................................................................................153

M13/M23 MUX/DeMUX Registers .....................................................................................................................196

28-Channel Framer Registers ............................................................................................................................239

Cross Connect (XC) Registers ...........................................................................................................................321

Digital Jitter Attenuation Controller Registers ....................................................................................................331

Test-Pattern Generation/Detection Registers .....................................................................................................336

Functional Descriptions ................................................... ................ ................. ....................................................354

Microprocessor Interface Functional Description ...............................................................................................354

TMUX Functional Description ........................................................................ .. ....... ..... ....... ...............................359

SPE Mapper Functional Description ..................................................................................................................396

VT/TU Mapper Functional Description ...............................................................................................................425

M13/M23 MUX/DeMUX Block Functional Description .......................................................................................455

28-Channel Framer Block Functional Description ..............................................................................................475

Cross Connect (XC) Block Functional Description ................................... ....... ..... .. .......... .. ..... ....... .. .................542

Digital Jitter Attenuation Controller Functional Description ................................................................................5 70

Test-Pattern Generation/Detec tion Functional Description ................................................................................574

Philosophies ....................................................................................................................................................... 5 82

Applications ..........................................................................................................................................................588

Change History ................................ ..... ..... ....... .. ..... .. .......... .. ..... ....... ..... .. ..... ....... .. ..... ......................................604

Page 5

5Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Product Description

2 Preface

Table of Contents

Contents Page

1 Features ............................................................................................................................................................... 1

1.1 SONET/SDH Interfa c e ......................... .......... ......... .................................................. ..................................... 1

1.2 STS/STM Pointer Interpreter .................... ......... ................................. .......... ......... ........................................ 1

1.3 Telecom Bus Inter face ................ ................................................. .......... ......... ............................................... 1

1.4 VT Termination/Generation (x28/x21) ................................. ....... .. ....... ..... ..... ....... .. ....... ..... ............................ 1

1.5 Mapping/Mu ltiplexing Mo des (x28/x21) ......... ......... ................................. .......... ......... ................................... 1

1.6 M13 Features ........... ......... .......... ................ .......... ......... ................. ......... .......... ............................................ 2

1.7 DS3/DS2/DS1/E1 Cross Connect ..................................................... .. ..... ..... .. ....... ..... .. ..... ..... ....................... 2

1.8 Jitter Attenuation .......................................................................... ................... ....... ........................................ 2

1.9 PDH Interfaces ..................................... .......... ......... .................................................. . .................................... 2

1.10 T1/E1/J1 Framing Features (x28/x21) ......................................................................................................... 2

1.11 System Test and Maintenance .................................................................................................................... 3

2 Preface .................................................................................................................................................................5

2.1 Major Categori e s .................................... .......... ......... ................. ......... .......... ................................................. 6

2.2 Naming Convention for Registers and Parameters ....................................................................................... 6

2.3 Overview ........... ................................. ......... .......... ................................. ......... ............................................... 7

Figures Page

Figure 1. Functional Diagram of Super Mapper ............................................................. ....... .. .......... ....................... 7

Page 6

6 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

2 Preface

(continued)

The objective of this data sheet is to defin e the functionality of the Super Mapper for hardware and software developers. The information contained in this data sheet is preliminary, and may change without notice; the reader must therefore ascertain that the latest version is used when a product is under development.

The latest version of this data sheet can b e accessed at: http://www.lucent.com/micro/netcom/products/ pdh.html#super_mapper.

2.1 Major Ca tegorie s

This data sheet is divided into six major categories with sub-sections as follows:

■

Features

■

Product Descript ion

— Features — Preface — Overview

■

Interface Specifications

— Pin Information — Electrical Characteristics — Timing Characteristics — Ordering Information

■

— Microprocessor Interface Registers — TMUX Registers — SPE Mapper Registers — VT/UT Mapper Registers — M13/M23 MUX/deMUX Registers — 28-Channel Framer Registers — Cross Connect (XC) Registers — Digital Jitter Attenuation Registers — Test Pattern Generation/Detec ti on Registers

■

Functional Descriptions

— Microprocessor Interface Description — TMUX Registers Description — SPE Mapper Registers Description — VT/UT Mapper Registers Description — M13/M23 MUX/deMUX Registers Description — 28-Channel Framer Registers Description — Cross Connect (XC) Registers Description — Digital Jitter Attenuation Registers Description — Test Pattern Generation/Detecti on Registers De-

scription

■

Applications

— Application Block Diagrams and Descriptions

2.2 Naming Convention for Registers and Parameters

There are many provisioning registers for controlling the Super Mapper. A naming conv ention for all registers and parameters (bit names) is followed throughout this data sheet. A prefix is attached to the base name of each register or parameter, depending on which functional section the register or parameter is associated with:

■

SMPR_, for the Microprocessor Interface

■

TMUX_, for the TMUX

■

SPE_, for the SPE Mapper

■

VT_, for the VT/VC Mapper

■

M13_, for the M13/M23 MUX/deMUX

■

FRM_, for the 28-Channel Framer

■

XC_, for the Cross Connect

■

DJA_, for the Digital Jitter Attenuator

■

TPG_ and TPM_, for the Test-Pattern Generator/ Detection

A suffix is appended to the base name of three common parameters:

■

_IS, for interrupt signal.

■

_IM, for interrupt mask.

■

_SWRS, for software reset.

Page 7

7Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

2 Preface

(continued)

2.3 Over view

The SONET/SDH Super Mappe r device integrates the SONET/SDH line, path, and tributary termination functions with M13 multiplex functions and t he primary rate framing function. It is designed to drive an OC-3/STM-1 optical signal directly or to allow for modular growth in terminal or add/drop applications.

It provides a versatile interface for all STS -3/STM-1 and STS-1 termi nation applications in point-to-point scenarios and for ring applications. This chip can be used in tributary shelf applications for up to 28 T1 or J1 or 21 E1 line cards providing all possible mappings into SONET/SDH. Bec ause of the flexibility of the mappings, software upgrades from M13 mapped connections to VT/TU mapped connections are possible. This device can also be used for DS3/DS2 applications.

A single Super Mapper is capable of processing the aggregate bandwidth of one STS-1 or DS3. By communicating to two other mate devices via the telecom bus interface, the Super Mapper is capable of terminating a full STS-3/STM-1 signal.

5-8923(F)

Figure 1. Functional Diagram of Super Mapper

TMUX

SPE/ AU-3

MAPPER

M13

MUX

VT/VC

MAPPER

TEST PATTERN GEN/MON

FRAMER

BANK

DIGITAL

JITTER

ATTENUATOR

T1/E1

DS2 DS3

CROSS

CONNECT

OVERHEAD

STS-1/

STS-3

MSP

MPU INTERFACE

AND CONTROL

MPU INTERFACE

TELECOM BUS

MAPPING &

DS3

T1/E1/J1

SYSTEM INTE RFACE

DS0/E0

DS1 (X29)

DS2 (X7)

DS1XCLK

DS1/E1

DS3/STS1

TPOAC

RPOAC

TTOAC

RTOAC

LOPOHOUT

LOPOHIN

TCB AND TDL

LINERX

LINETX

MISC

DS2AISCLK

SYS

TERMINATION

MULTIPLEXING

FRAMING

STM-1

AU-3

1 + 1

CLK

SYNC

RCB AND RDL

E1XCLK

(NSMI MODE)

/E1 (X22 )

(XN)

BUS

Page 8

8 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

Interface Specifica tions

3 Pin Information

Table of Contents

Contents Page

3 Pin Information ..................................................................................................................................................... 8

3.1 456-Pin PBGA Pin Diagram ............................................ ............ ....... ....... ............ ....... ....... ........................... 9

3.2 Pin Assig nme nt s ........................................ ......... .......... ......... ................. ......... .......... .................................... 9

3.3 Pin Descriptions ...... ......... ......... .................................. ......... .......... .............................................................. 15

3.3.1 High-speed I/O Pin Descriptions ........................................................................................................ 15

3.3.2 Protection Switch I/O Pin Description ................................................................................................ 16

3.3.3 Telecom Bus (Low-speed I/O) Pin Description .................................................................................. 16

3.3.4 TOAC and POAC ............................................................................................................................... 1 9

3.3.5 Miscellaneous Signals ........................................................................................................................ 20

3.3.6 DS3 Port .............................................................................................................................................2 0

3.3.7 M13 Multiplexer/Demultiplexer Receive Section ................................................................................ 2 2

3.3.8 Low-Order Path Overhead Access Channel ...................................................................................... 2 3

3.3.9 Framer PLL ........................................................................................................................................ 27

3.3.10 Test Pins ..................... .......... ................................. ......... .......... ....................................................... 30

3.4 Outline Diagra m ............... ......... .................................. ......... .......... ......... ................. .................................... 32

3.4.1 456-Pin PBGA .................................................................................................................................... 32

List of Figures

Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)........................................................................................... 9

Figure 3. Protection Switch..................................................................................................................................... 16

Figure 4. DS1/E1 to DXC Block Diagram............................................................................................................... 23

List of Tables

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order ....................................................................... 9

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name ..............................................................................12

Table 3. High- sp e ed I/O Pi n Descri p tions ................ ......... .......... ..........................................................................15

Table 4. Prot e ction Switch I/O Pin Description ...... .......... ......... .......... ................................................................... 16

Table 5. Telecom Bus (Low-speed I/O) Pin Description ........................................................................................ 17

Table 6. TOAC and POAC ............. ......... .......... ................................................. .......... ......... ................................19

Table 7. Miscellaneous Signals .............................................................................................................................20

Table 8. DS3 Port ..................................................................................................................................................21

Table 9. DS3 Port, C-Bit, and Datalink Access ..................................................................................................... 22

Table 10. M13 Multiplexer/Demultiplexer Receive Section ................................................................................... 22

Table 11. Low-Order Path Overhead A ccess Channel ........................................................... .............................. 23

Table 12. Multifunction System Interface Transmit Path Direction ........................................................................24

Table 13. Framer PLL ............................................................................................................................................ 27

Table 14. Microprocessor Interfaces .....................................................................................................................28

Table 15. General Purpose Interface ....................................................................................................................29

Table 16. Test Pins ................................................................................................................................................30

Table 17. CDR Power ............................................................................................................................................ 30

Table 18. LVDS Contr o l Pi n s .............. .......... ......... .................................. ......... ......... .......... .................................. 30

Page 9

9Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

3.1 456-Pin PBGA Pin Diagram

5-8931(F)

Figure 2. Pin Diagra m of 456-Pin PBGA (Bottom View)

3.2 Pin Assignments

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 V

A21 V

B15 LINETXDATA2 C9 LINERXSYNC24

A2 V

A22 VDD B16 LINETXSYNC4 C10 LINERXCLK25 A3 LINERXDATA17 A23 LINETXSYNC12 B17 LINETXSYNC5 C11 LINERXCLK26 A4 LINERXDATA18 A24 LINETXSYNC13 B18 LINETXSYNC6 C12 LINERXCLK27 A5 V

A25 V

B19 LINETXCLK7 C13 LINERXDATA28

A6 V

A26 V

B20 LINETXDATA8 C14 LINETXSYNC2

A7 LINERXDATA21 B1 V

B21 LINETXSYNC10 C15 LINETXCLK3 A8 LINERXSYNC23 B2 LINERXCLK15 B22 LINETXDATA10 C16 LINETXCLK4 A9 LINERXCLK24 B3 LINERXSYNC18 B23 LINETXDATA11 C17 LINETXCLK5

A10 V

B4 LINERXSYNC19 B24 LINETXDATA12 C18 LINETXDATA6

A11 V

B5 LINERXSYNC20 B25 LINETXCLK13 C19 LINETXSYNC8

A12 LINERXDATA27 B6 LINERXDATA20 B26 V

C20 LINETXCLK9 A13 LINERXSYNC29 B7 LINERXSYNC22 C1 LINERXSYNC15 C21 LINETXCLK10 A14 LINETXDATA1 B8 LINERXCLK23 C2 LINERXDATA14 C22 LINETXCLK11 A15 LINETXSYNC3 B9 LINERXDATA24 C3 LINERXCLK17 C23 LINETXCLK12 A16 V

B10 LINERXDATA25 C4 LINERXCLK18 C24 LINETXCLK14

A17 V

B11 LINERXDATA26 C5 LINERXCLK19 C25 LINETXSYNC15 A18 LINETXCLK6 B12 LINERXSYNC28 C6 LINERXCLK20 C26 LINETXDATA14 A19 LINETXDATA7 B13 LINERXCLK29 C7 LINERXCLK21 D1 LINERXSYNC14 A20 LINETXSYNC9 B14 LINETXCLK1 C8 LINERXDATA22 D2 LINERXDA TA13

AE AD AC AB AA

V U T R P N

L K

F E D C B A

123456789

10121314151617181920232425

BALL

CORNER

Page 10

10 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

D3 LINERXCLK14 E21 LINETXDATA13 J25 LINETXDATA21 N1 LINERXDATA3 D4 V

E22 V

J26 LINETXCLK21 N2 LINERXCLK3

D5 LINERXDATA19 E23 LINETXDATA16 K1 V

N3 LINERXSYNC4 D6 LINERXSYNC21 E24 LINETXCLK16 K2 LINERXSYNC7 N4 LINERXSYNC3 D7 LINERXCLK22 E25 LINETXSYNC17 K3 LINERXCLK7 N5 SCAN_EN D8 LINERXDATA23 E26 V

K4 LINE RXDATA6 N11 V

D9 LINERXSYNC25 F1 V

K5 LINERXSYNC16 N12 V

D10 L INERXSYNC26 F2 LINERXSYNC12 K22 DS3NEGDATAIN N13 V

D11 LINERXSYNC27 F3 LINERXCLK12 K23 LINETXSYNC23 N14 V

D12 LINERXCLK28 F4 LINERXDATA11 K24 LINETXCLK22 N15 V

D13 LINERXDATA29 F5 LINERXDATA15 K25 LINETXDATA22 N16 V

D14 LINETXSYNC1 F22 LINETXSYNC14 K26 V

N22 DS3DATAOUTCLK

D15 LINETXCLK2 F23 LINETXSYNC18 L1 V

N23 LINETXDATA26 D16 LINETXDATA3 F24 LINETXCLK17 L2 LINERXSYNC6 N24 LINETXDATA25 D17 LINETXDATA4 F25 LINETXDATA17 L3 LINERXCLK6 N25 LINETXCLK26 D18 LINETXDATA5 F26 V

L4 LINERXDATA5 N26 LINETXSYNC26

D19 LINETXSYNC7 G1 LINERXSYNC11 L5 V

P1 LINERXSYNC2

D20 LINETXCLK8 G2 LINERXDATA10 L11 V

P2 LINERXCLK2

D21 LINETXDATA9 G3 LINERXCLK11 L12 V

P3 LINERXDATA1

D22 LINETXSYNC11 G4 LINERXCLK10 L13 V

P4 LINERXDATA2

D23 V

G5 V

L14 V

P5 IDDQ

D24 LINETXCLK15 G22 V

L15 V

P11 V

D25 LINETXSYNC16 G23 LINETXCLK19 L16 V

P12 V

D26 LINETXDATA15 G24 LINETXCLK18 L22 V

P13 V

E1 V

G25 LINETXSYNC19 L23 LINETXSYNC24 P14 V

E2 LINERXDATA12 G26 LINETXDATA18 L24 LINETXCLK23 P15 V

E3 LINERXCLK13 H1 LINERXDATA9 L25 LINETXDATA23 P16 V

E4 LINERXSYNC13 H2 LINERXCLK9 L26 V

P22 DS3NEGDATAOUT

E5 V

H3 LINERXSYNC10 M1 LINERXSYNC5 P23 LINETXSYNC27 E6 LINERXSYNC17 H4 LINERXSYNC9 M2 LINERXDATA4 P24 LINETXSYNC28 E7 V

H5 LINERXDATA16 M3 LINERXCLK5 P25 LINETXCLK27 E8 TDLDATA H22 RDLDATA M4 LINERXCLK4 P26 LINETXDATA27 E9 TDLCLK H23 LINETXDATA20 M5 SCAN_MODE R1 RLSDATA7

E10 DS2AISCLK H24 LINETXDATA19 M11 V

R2 LINERXSYNC1

E11 V

H25 LINETXCLK20 M12 V

R3 RLSDATA6

E12 TCBDATA H26 LINETXSYNC20 M13 V

R4 LINERXCLK1

E13 TCBCLK J1 LINERXCLK8 M14 V

R5 TCK

E14 TCBSYNC J2 LINERXSYNC8 M15 V

R11 V

E15 R CBDATA J3 LINERXDATA8 M16 V

R12 V

E16 V

J4 LINERXDATA7 M22 DS3POSDATAIN R13 V

E17 RCBCLK J5 LINERXCLK16 M23 LINETXCLK25 R14 V

E18 RCBSYNC J22 DS3DATAINCLK M24 LINETXCLK24 R15 V

E19 RDLCLK J23 LINETXSYNC22 M25 LINETXSYNC25 R16 V

E20 V

J24 LINETXSYNC21 M26 LINETXDATA24 R22 DS3POSDATAOUT

T ab le 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

(continued)

Page 11

11Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

R23 LINETXCLK28 W5 TMSN AB19 RXDATAEN AD11 RPSC155N R24 LINETXCLK29 W22 TXDATAEN AB20 V

AD12 REF14 R25 LINETXDATA28 W23 DATA4 AB21 MODE2_PLL AD13 TPSC155N R26 LINETXSYNC29 W24 DATA7 AB22 V

AD14 ECSEL

T1 V

W25 DATA5 AB23 ADDR19 AD15 TSTSFTLD T2 RLSDATA4 W26 DATA6 AB24 INTN AD16 DS1XCLK T3 RLSDATA3 Y1 TLSDATA2 AB25 DATA15 AD17 MPMODE T4 RLSDATA5 Y2 TLSDATA3 AB26 V

AD18 DSN

T5 VDD Y3 TLSDATA1 AC1 RLSSYNC52 AD19 ADDR3

T11 V

Y4 TLSDATA4 AC2 RLSC52 AD20 ADDR7

T12 V

Y5 V

AC3 TLSC52 AD21 ADDR10

T13 V

Y22 V

AC4 V

AD22 VDDD_PLL

T14 V

Y23 DATA8 AC5 TPOACSYNC AD23 VSSS_PLL

T15 V

Y24 DATA11 AC6 A UT O_AIS1 AD24 CLKIN_PLL

T16 V

Y25 DATA9 AC7 RHSCP AD25 ADDR16

T22 V

Y26 DATA10 AC8 THSSYNCP AD26 ADDR15

T23 LINETXDATA29 AA1 V

AC9 VDDA_CDR AE1 V

T24 RSTN AA2 TLSCLK AC10 RPSC155P AE2 TTOACDATA T25 PMRST AA3 TLSPAR AC11 REF10 AE3 RPOACCLK T26 V

AA4 TLSDATA0 AC12 TPSC155P AE4 TPOACCLK U1 V

AA5 RTOACSYNC AC13 LOPOHCLKIN AE5 LOSEXT U2 RL SDATA1 A A22 ADDR13 AC14 LOPOHDATAIN AE6 AUTO_AIS2 U3 RL SDATA0 AA23 DATA12 AC15 ETOGGLE AE7 RHSDN U4 RLSDATA2 AA24 DATA14 AC16 TSTMUX0 AE8 THSCN U5 TDI AA25 DATA13 AC17 E1XCLK AE9 THSDN

U22 PHASEDETDOWN AA26 V

AC18 CSN AE10 RPSD155N

U23 DTN AB1 V

AC19 ADDR0 AE11 CTAPTH U24 PAR1 AB2 TLSSPE AC20 ADDR4 AE12 RESLO U25 PAR0 AB3 TLSV1 AC21 ADDR8 AE13 TPSD155N U26 VDD AB4 TLSJ0J1V1 AC22 ADDR12 AE14 BYPASS

V1 RLSSPE AB5 V

AC23 V

AE15 EXDNUP V2 RLSPAR AB6 TTOACCLK AC24 ADDR17 AE16 TSTMUX1 V3 RLSJ0J1V1 AB7 V

AC25 APS_INTN AE17 MPCLK V4 RLSCLK AB8 TRSTN AC26 ADDR18 AE18 ADSN V5 TDO AB9 IC3STATEN AD1 RTOACCLK AE19 ADDR1

V22 PHASEDETUP AB10 CTAPRH AD2 TLSSYNC52 AE20 ADDR5 V23 DATA0 AB11 V

AD3 RTOACDATA AE21 ADDR9 V24 DATA3 AB12 VSSA_CDR AD4 RPOACDATA AE22 ADDR11 V25 DATA1 AB13 CTAPRP AD5 TPOACDATA AE23 VDDS_PLL V26 DATA2 AB14 LOPOHVALIDIN AD6 AUTO_AIS3 AE24 MODE1_PLL

W1 TLSDATA6 AB15 LOPOHCLKOUT AD7 RHSFSYNCN AE25 ADDR14 W2 TLSDATA7 AB16 V

AD8 RHSCN AE26 V

W3 TLSDATA5 AB17 LOPOHDATAOUT AD9 THSSYNCN AF1 V

W4 RLSV1 AB18

LOPOHVALIDOUT

AD10 RPSD155P AF2 V

T ab le 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

(continued)

Page 12

12 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

AF3 TTOACSYNC AF9 THSDP A15 TSTMODE AF21 VSS AF4 RPOACSYNC AF10 V

A16 V

AF22 VDD

AF5 V

AF11 V

A17 V

AF23 VSSA_PLL

AF6 V

A12 REWSHI A18 RWMN AF24 MODE0_PLL AF7 RHSDP AF13 TPSD155P A19 ADDR2 AF8 THSCP AF14 TSTPHASE AF20 ADDR6

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

ADDR0 AC19 CTAPRP AB13 ECSEL AD14 LINERXCLK24 A9 ADDR1 AE19 CTAPTH AE11 ETOGGLE AC15 LINERXCLK25 C10 ADDR2 AF19 DATA0 V23 EXDNUP AE15 LINERXCLK26 C11 ADDR3 AD19 DATA1 V25 IC3STATEN AB9 LINERXCLK27 C12 ADDR4 AC20 DATA2 V26 IDDQ P5 LINERXCLK28 D12 ADDR5 AE20 DATA3 V24 INTN AB24 LINERXCLK29 B13 ADDR6 AF20 DATA4 W23 LINERXCLK1 R4 LINERXDATA1 P3 ADDR7 AD20 DATA5 W25 LINERXCLK2 P2 LINERXDATA2 P4 ADDR8 AC21 DATA6 W26 LINERXCLK3 N2 LINERXDATA3 N1

ADDR9 AE21 DATA7 W24 LINERXCLK4 M4 LINERXDATA4 M2 ADDR10 AD21 DATA8 Y23 LINERXCLK5 M3 LINERXDATA5 L4 ADDR11 AE22 DATA9 Y25 LINERXCLK6 L3 LINERXDATA6 K4 ADDR12 AC22 DATA10 Y26 LINERXCLK7 K3 LINERXDATA7 J4 ADDR13 AA22 DATA11 Y24 LINERXCLK8 J1 LINERXDATA8 J3 ADDR14 AE25 DATA12 AA23 LINERXCLK9 H2 LINERXDATA9 H1 ADDR15 AD26 DATA13 AA25 LINERXCLK10 G4 LINERXDATA10 G2 ADDR16 AD25 DATA14 AA24 LINERXCLK11 G3 LINERXDATA11 F4 ADDR17 AC24 DATA15 AB25 LINERXCLK12 F3 LINERXDATA12 E2 ADDR18 AC26 DS1XCLK AD16 LINERXCLK13 E3 LINERXDATA13 D2 ADDR19 AB23 DS2AISCLK E10 LINERXCLK14 D3 LINERXDATA14 C2

ADSN AE18 DS3DATAINCLK J22 LINERXCLK15 B2 LINERXDATA15 F5

APS_INTN AC25 DS3DATAOUTCLK N22 LINERXCLK16 J5 LINERXDATA16 H5 AUTO_AIS1 AC6 DS3NEGDATAIN K22 LINERXCLK17 C3 LINERXDATA17 A3 AUTO_AIS2 AE6 DS3NEGDATAOUT P22 LINERXCLK18 C4 LINERXDATA18 A4 AUTO_AIS3 AD6 DS3POSDATAIN M22 LINERXCLK19 C5 LINERXDATA19 D5

BYPASS AE14 DS3POSDATAOUT R22 LINERXCLK20 C6 LINERXDATA20 B6

CLKIN_PLL AD24 DSN AD18 LINERXCLK21 C7 LINERXDATA21 A7

CSN AC18 DTN U23 LINERXCLK22 D7 LINERX DATA22 C8

CTAPRH AB10 E1XCLK AC17 LINERXCLK23 B8 LINERXDATA23 D8

T ab le 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

(continued)

Page 13

13Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

LINERXDATA24 B9 LINETXCLK7 B19 LINETXDATA19 H24 LOPOHCLKOUT AB15 LINERXDATA25 B10 LINETXCLK8 D20 LINETXDATA20 H23 LOPOHDATAIN AC14 LINERXDATA26 B11 LINETXCLK9 C20 LINETXDA TA21 J25 LOPOHDA TAOUT AB17 LINERXDATA27 A12 LINETXCLK10 C21 LINETXDATA22 K25 LOPOHVALIDIN AB14 LINERXDATA28 C13 LINETXCLK11 C22 LINETXDATA23 L25 LOPOHVALIDOUT AB18 LINERXDATA29 D13 LINETXCLK12 C23 LINETXDATA24 M26 LOSEXT AE5

LINERXSYNC1 R2 LINETXCLK13 B25 LINETXDATA25 N24 MODE0_PLL AF24 LINERXSYNC2 P1 LINETXCLK14 C24 LINETXDATA26 N23 MODE1_PLL AE24 LINERXSYNC3 N4 LINETXCLK15 D24 LINETXDATA27 P26 MODE2_PLL AB21 LINERXSYNC4 N3 LINETXCLK16 E24 LINETXDATA28 R25 MPCLK AE17 LINERXSYNC5 M1 LINETXCLK17 F24 LINETXDATA29 T23 MPMODE AD17 LINERXSYNC6 L2 LINETXCLK18 G24 LINETXSYNC1 D14 PAR0 U25 LINERXSYNC7 K2 LINETXCLK19 G23 LINETXSYNC2 C14 PAR1 U24 LINERXSYNC8 J2 LINETXCLK20 H25 LINETXSYNC3 A15 PHASEDETDOWN U22

LINERXSYNC9 H4 LINETXCLK21 J26 LINETXSYNC4 B16 PHASEDETUP V22 LINERXSYNC10 H3 LINETXCLK22 K24 LINETXSYNC5 B17 PMRST T25 LINERXSYNC11 G1 LINETXCLK23 L24 LINETXSYNC6 B18 RCBCLK E17 LINERXSYNC12 F2 LINETXCLK24 M24 LINETXSYNC7 D19 RCBDATA E15 LINERXSYNC13 E4 LINETXCLK25 M23 LINETXSYNC8 C19 RCBSYNC E18 LINERXSYNC14 D1 LINETXCLK26 N25 LINETXSYNC9 A20 RDLCLK E19 LINERXSYNC15 C1 LINETXCLK27 P25 LINETXSY NC10 B 21 RDLDATA H22

LINERXSYNC16 K5 LINETXCLK28 R23 LINETXSYNC11 D22 REF10 AC11 LINERXSYNC17 E6 LINETXCLK29 R24 LINETXSYNC12 A 23 REF14 AD12 LINERXSYNC18 B3 LINETXDATA1 A14 LINETXSYNC13 A24 RESHI AF12 LINERXSYNC19 B4 LINETXDATA2 B15 LINETXSYNC14 F22 RESLO AE12 LINERXSYNC20 B5 LINETXDATA3 D 16 LINETXSYNC15 C25 RHSCN AD8 LINERXSYNC21 D6 LINETXDATA4 D17 LINETXSYNC16 D25 RHSCP AC7 LINERXSYNC22 B7 LINETXDATA5 D18 LINETXSYNC17 E25 RHSDN AE7 LINERXSYNC23 A8 LINETXDATA6 C18 LINETXSYNC18 F23 RHSDP AF7 LINERXSYNC24 C9 LINETXDATA7 A19 LINETXSYNC19 G25 RHSFSYNCN AD7 LINERXSYNC25 D9 LINETXDATA8 B20 LINETXSYNC20 H26 RLSC52 AC2 LINERXSYNC26 D10 LINETXDATA9 D21 LINETXSYNC21 J24 RLSCLK V4 LINERXSYNC27 D11 LINETXDATA10 B22 LINETXSYNC22 J 23 RLSDATA0 U3 LINERXSYNC28 B12 LINETXDATA11 B23 LINETXSYNC23 K 23 RLSDATA1 U2 LINERXSYNC29 A13 LINETXDATA12 B24 LINETXSYNC24 L23 RLSDATA2 U4

LINETXCLK1 B14 LINETXDATA13 E21 LINETXSYNC25 M25 RLSDATA3 T3 LINETXCLK2 D15 LINETXDATA14 C26 LINETXSYNC26 N26 RL SDATA4 T2 LINETXCLK3 C15 LINETXDATA15 D26 LINETXSYNC27 P23 RLSDATA5 T4 LINETXCLK4 C16 LINETXDATA16 E 23 LINETXSYNC28 P24 RLSDATA6 R3 LINETXCLK5 C17 LINETXDATA17 F25 LINETXSYNC29 R26 RLSDATA 7 R1 LINETXCLK6 A18 LINETXDATA18 G26 LOPOHCLKIN AC13 RLSJ0J1V1 V3

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name

(continued)

Page 14

14 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

RLSPAR V2 TLSPAR AA3

AB11 V

N12

RLSSPE V1 TLSSPE AB2 V

AB16 V

N13

RLSSYNC52 AC1 TLSSYNC52 AD2 V

AB22 V

N14

RLSV1 W4 TLSV1 AB3 V

AB26 V

N15

RPOACCLK AE3 TMSN W5 V

AF1 V

N16

RPOACDATA AD4 TPOACCLK AE4 V

AF5 V

P11

RPOACSYNC AF4 TPOACDATA AD5 V

AF10 V

P12

RPSC155N AD11 TPOACSYNC AC5 V

AF17 V

P13

RPSC155P AC10 TPSC155N AD13 V

AF22 V

P14

RPSD155N AE10 TPSC155P AC12 V

AF26 V

P15

RPSD155P AD10 TPSD155N AE13 VDDA_CDR AC9 V

P16

RSTN T24 TPSD155P AF13 VDDD_PLL AD22 V

R11

RTOACCLK AD1 TRSTN AB8 VDDS_PLL AE23 V

R12

RTOACDATA AD3 TSTMODE AF15 V

A2 V

R13

RTOACSYNC AA5 TSTMUX0 AC16 V

A6 V

R14

RWN AF18 TSTMUX1 AE16 V

A11 V

R15

RXDATAEN AB19 TSTPHASE AF14 V

A16 V

R16

SCAN_EN N5 TSTSFTLD AD15 V

A21 V

SCAN_MODE M5 TTOACCLK AB6 V

A25 V

T11

TCBCLK E13 TTOACDATA AE2 V

B1 V

T12

TCBDATA E12 TTOACSYNC AF3 V

B26 V

T13

TCBSYNC E14 TXDATAEN W22 V

D4 V

T14

TCK R5 V

A1 V

D23 V

T15

TDI U5 V

A5 V

E7 V

T16

TDLCLK E9 V

A10 V

E20 V

T26

TDLDATA E8 V

A17 V

F1 V

TDO V5 V

A22 V

F26 V

Y22

THSCN AE8 V

A26 V

G5 V

AA1

THSCP AF8 V

E1 V

G22 V

AA26

THSDN AE9 V

E5 V

L1 V

AB7

THSDP AF9 V

E11 V

L11 V

AB20

THSSYNCN AD9 V

E16 V

L12 V

AC4

THSSYNCP AC8 V

E22 V

L13 V

AC23

TLSC52 AC3 V

E26 V

L14 V

AE1

TLSCLK AA2 V

K1 V

L15 V

AE26

TLSDATA0 AA4 V

K26 V

L16 V

AF2

TLSDATA1 Y3 V

L5 V

L26 V

AF6

TLSDATA2 Y1 V

L22 V

M11 V

AF11

TLSDATA3 Y2 V

T5 V

M12 V

AF16

TLSDATA4 Y4 V

T22 V

M13 V

AF21

TLSDATA5 W3 V

U1 V

M14 V

AF25

TLSDATA6 W1 V

U26 V

M15 VSSA_CDR AB12

TLSDATA7 W2 V

AB1 V

M16 VSSA_PLL AF23

TLSJ0J1V1 AB4 V

AB5 V

N11 VSSS_PLL AD23

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name

(continued)

Page 15

15Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

3.3 Pin Descriptions

3.3.1 High-speed I/O Pin Descriptions

The high speed I/O consists of five LVDS signals (10 pins) that connect the Super Mapper to an external OC-3 optics device. It exchanges an STS-3 or STM-1 signal between the TMUX and an OC-3 transceiver. The Super Mapper is capable of recovering a clock from the receive data, or can accept a clock recovered externally by the optics device. If internal clock recovery is used, the Super Mapper uses T HSCP/N as a reference.

The high-speed I/O m ay also run at 52.84 M b its/s in applications that terminate an STS-1 or EC-1 signal. In this case, the (electrical) line signals a r e typically t erminated by a line interface unit (LIU) chip. The operating speed of the high-speed I/O is determined by TMUX_RCV_TX_MODE.

Table 3. High-speed I/O Pin Descriptions

Pin Symbol Type I/O Description

AF7,

AE7

RHSDP RHSDN

LVDS I

Receive High-speed Data.

155.52 Mbits/s serial data input in STS-1 or STM-1 format, or 51.84 Mbits/s data in STS-1 format. If RHSD is not used (in a slave Super Mapper, for example) the P input should be pulled high through a 1 kΩ resistor and the N input pulled low through a 1 kΩ resistor. RHSD is typically provided by and OC-3 receiver, an STS-1 line interface unit or an higher order (e.g. STS-12) demultiplexing chip.

AC7,

AD8

RHSCP RHSCN

LVDS I

Receive High-speed Clock.

155.52 or 51.84 MHz clock for STS-3 or STS-1 input data. Typically supplied by an external OC-3 opto-electonic device, or an STS-1/EC1 l ine interface unit, synchronous with RHSD. If the internal clock recovery (CDR) feature is enabled, RHC is not required and should be connected to through 1 kΩ resistors to V

(RHCP input)

and V

(RHCN input).

AF8,

AE8

THSCP

THSCN

LVDS I

Transmit High-speed Clock.

Transmit 155.52 MHz or 51. 84 MHz clock. Master clock for the transmit sections of the TMUX, telecom bus, SPE, and VT mappers. THSC is also used as a reference clock for the receive CDR, if it is being used.

AC8,

AD9

THSSYNCP THSSYNCN

LVDS I

Transmit High-speed Frame Synchronization.

An optional input that may be used to specify the position of the transmit STS-3, STM-1, or STS-1 frame. THSSYNC mark s the position of bit 1 of the A1 byte, i.e., the first bit of the overhead in the THSD output. If THSSYNC is not used, the P input should be pulled high through a 1 kΩ resistor, and the N input pulled low through a 1 kΩ resistor. A typical application for this pin may be to synchronize a group of Su per Mappers, so that their STS-3 outputs may be multiplexed into an STS- 12 signal.

AF9,

AE9

THSDP

THSDN

LVDS O

T ransmit High-speed Data.

Transmit output for STS-3, STM-1, or STS-1 serial data. Typically connected to an OC-3 module or an LIU, if operating in STS-1 mode. May also b e c onnected to a higher order mu ltiplexing device, STS-12 for e xample.

Page 16

16 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

3.3.2 Protection Switch I/O Pin Description

The protection switch I/O provides additional copies of the high-speed interface signals so that various protection schemes may be implemented. The protection interface may be used when the high-speed interface is operating in both STS-3 and STS-1 modes. If the protection port is not used, the input clock and data may be left unconnected, tied to power (P inputs), or ground (N inputs) through 1 kΩ resistors. Unused protection outputs should be left unconnected.

Table 4. Protection Switch I/O Pin Description

Figure 3. Protection Switch

3.3.3 Telecom Bus (Low-speed I/O) Pin Description

The telecom bus on the Super Mapper is used for interconnecting STS-1 signals. It has two eight-bit data buses, one for upstream data and one for downstream data, plus clock and frame indication signals for each bus. The telecom bus can operate at 19.44 MHz (space for three STS-1 signals) or 6.48 MH z (space for 1 STS-1 signal).

Super Mappers in OC-3 applications are typically connected together using the telecom bus, and the bus is configured to operate at 19.44 MHz.

Pin Sym bol Type I/O Description

AD10,

AE10

RPSD155P RPSD155N

LVDS I

Receive Protection Data.

Receive side high-speed serial data input

from protection board.

AC10,

AD11

RPSC155P RPSC155N

LVDS I

Receive Protection Clock.

Receive side high-speed clock input from

protection board.

AF13,

AE13

TPSD155P TPSD155N

LVDS O

Transmit Protection Data.

Transmit side high-speed se rial data output

to protection board.

AC12,

AD13

TPSC155P TPSC155N

LVDS O

Transmit Protection Clock.

Transmit side high-speed clock outp ut to

protection board.

STS-3 TRANSMIT

FRAMER

STS-3 RECEIVE

FRAMER

RPSMUXSEL1

HIGH-SPEED PROTECTION INPUTS

TPSMUXSEL2

HIGH-SPEED PROTECTION OUTPUTS

TPSMUXSEL3

HIGH-SPEED I/O

Page 17

17Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Table 5. Telecom Bus (Low-speed I/O) Pin Description

Pin Symbo l Type I/O Description

R1, R3, T4, T2,

T3, U4, U2, U3

RLSDATA[7:0] — I/O

Receive Low-speed Data (7:0), Parallel Data Bus.

Used to connect the downstream STS - 1 signals from the master to the slave devices. In master mode, RLSDATA is an output bus, eight bits wide. It contains all the received data for distribution to the two slave devices. Connect to RLSDATA(7:0) on the slave devices. In slave mode, these pins are inputs and should b e conne cted to the RLSDATA(7:0) outputs on the master. RLSDATA contains three byte-interleaved STS-1 time slots. The slot used by each SPE mapper in the slaves and the master device, is determined by programing the SPE_RSTS3_TMSLOT register bits.

V4 RLSCLK — I/O

Receive Low-speed Clock.

This is a 19.44 MHz or

6.48 MHz clock for the receive low speed data b its. In

19.44 MHz master m ode, this is a 19.44 MHz clock output for distribution to the two slave devices. Connect to RLSCLK on the slaves. RLSCLK is an input signal on slave devices.

Note:

As outputs, these pins have 6 mA drive capability.

V2 RLSPAR — I/O

Receive Low-speed Parity.

Receive data parity bit, may be configured for odd or even parity generated on RLSDATA(7:0). The default is odd parity; it may be set to even by setting bit 2 of the register at 0x4001B an output in master mode and an input in slave mode. Connect the RSLPAR (output) on the master to T he RLS PAR (input) pins on the slaves.

V1 RLSSPE — I/O

Receive Low-speed SPE Marker.

Receive synchronous payload envelope timing indicator. It is high, while there is SPE data on the RLSDATA(7:0) output bus. Connect to RLSSPE on the slaves. RLSSPE is an input on slave devices.

V3 RLSJ0J1V1 — I/O

Receive Low-speed J0/J1/V1 Marker.

On the master device, this is an output that is high while J0-1, J1 (1, 2 and 3) and V1 (1, 2 and 3) bytes are present on the RLSDAT A b us. Connect to RLSJ0J1V1 on the slav es, which is an inp ut.

W4 RLSV1 — I/O

Receive Low-speed V1 Marker.

Receive V1 timing indicator. On the master this is an output that is high while the V1 bytes (1, 2 and 3) are present on RLSDATA(7:0) output bus. Connect to RLSV1 on the slaves.

Page 18

18 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Table 5. Telecom Bus (Low-speed I/O) Pin Description

(continued)

Pin Symbol Type I/O Description

W2, W1, W3, Y4,

Y2, Y1, Y3, AA4

TLSDATAI[7:0] — I/O

Transmit Low-speed Data (7:0).

This is a parallel data bus. It is used to connect the upstream STS-1 signals from the slave devices to the master device. In master mode, TLSDATA is an input bus, eight bits wide. It contains all the transmit STS-1 data from the slave devices. In slave mode, these pins are outputs and should be connecte d to the TLSDATA(7:0) inputs on the master. TLSDATA contains three byte-interleaved STS-1 time slots. The slot use d b y each SPE mapper in the slaves and the master device, is determined by programing the SPE_TSTS3_TMSLOT register bits.

AA2 TLSCLK — I/O

Transmit Low-speed Clock.

This is a 19.44 MHz or

6.48 MHz clock for the TLSDATA(7:0) bits. TLSCLK is an output on a master Super Mapper and an input on a slave.

Note:

As outputs, these pins have 6 mA drive capability.

AA3 TLSPAR — I/O

T ransmit Low-speed Parity .

This parity bit is generated on the TLSDATA(7:0) bits output from slave devices and input to the master Super Mapper. May be configured for odd or even parity generation or for checking.

AB2 TLSSPE — I/O

Transmit Low-speed SPE Marker.

High while the STS-1 payloads are present on the TLSDATA(7:0) bus. Low while the STS-1 overhead is present on the TLSDATA(7:0) bus. An output from the master and input on the slaves.

AB4 TLSJ0J1V1 — I/O

Transmit Low-speed J0/J1/V1 Marker.

T ransmit J0, J1, or V1, timing indicator. High while the J0, J1 or V1 bits are present on the TLSDATA(7:0) bus. An output on the master and input on slaves.

AB3 TLSV1 — I/O

T ransmit Low-speed V1 Marker 3.

Transmit V1 timing indicator. High while the V1 bits are present on the TLSDATA(7:0) bus. An output on the master and input on slaves.

AC2 RLSC52 — I/O

Receive Low-speed Clock.

When in output (master) mode, it is the receive side of the 51.84 MHz clock output, synchronous to the receive high-speed input clock (data). When in input (slave) mode, it receives a 51.84 MHz clock input, synchronous to the receive high-speed input clock (data).

Note:

As outputs, these pins have 6 mA drive capability.

AC1 RLSSYNC52 — I/O

Receive Low-speed Sync

. When in output (master) mode,

it is the receive side frame sync output synchronous to a

51.84 MHz output. When in input mode, it is the receive side frame sync input synchronous to a 51.84 MHz input.

Page 19

19Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Table 5. Telecom Bus (Low-speed I/O) Pin Description

(continued)

3.3.4 TOAC and POAC

The transport and path overhead access channels (TOAC and POAC) allow parts of the SONET/SDH overhead to be examined externally (receive direction) or overwritten (transmit direction) through serial data ports. Each port has clock and data lines and synchronization signal that marks the last bit of the frame so that the rest of the overhead bytes can be identified.

The receive TOAC and POAC channels contain all of the respective overheads bytes. The transmit channels contain space for all the overhead bytes, but whether they are actually transmitted depend on how the device is programmed. Some overhead bytes can not be modified; others may be modified only thro ugh t he CPU port; some may be modified only through the overhead access channels; and some may be modified either through the CPU port, or through the overhead access channels.

Pin Sym bo l Type I/O Description

AC3 TLSC52 — I/O Transmit Low-speed Clock. When in output (master) mode,

it is the transmit side 51.84 MHz clock output synchronous to transmit high-speed input clock. When in input mode, it receives a 51.84 MHz clock input synchronous to transmit high-speed input clock

Note:

TLSCLK is used as the master clock for the T1/E1 framer and should therefore be provided even if the TMUX SPE and VT mappers are not used.

AD2 TLSSYNC52 — I/O

Transmit Low-speed Sync.

Whe n in output (master) mode,

it is the transmit side frame sync output synchron ous t o

51.84 MHz output. When in input (slave) mode, it receives the transmit side frame sync input synchronous to 51.84 MHz input.

Table 6. TOAC and POAC

Pin Symbol Type I/O Description

AD1 RTOACCLK — O

Receive TOAC Clock.

Receive side serial access channel

clock output for the transport overhead bytes.

AD3 RTOACDATA — O

Receive TOAC Data.

Receive side serial access channel

data output for the transport overhead b yte s.

AA5 RTOACSYNC — O

Recei ve T OAC Sync hr on iz at ion .

Receive side sync output for TOAC channel. Active-high during the LSB of the last byte.

AB6 TTOACCLK — O

Transmit TOAC Clock.

Transmit side serial access channel

clock output for the transport overhead bytes.

AE2 TTOACDATA — I

Pull down

Transmit TOAC Data.

Transmit side serial access channel

data input for the transport overhead bytes.

AF3 TTOACSYNC — O

Transmit TOAC Synchronization.

Transmit side sync output for TOA C channel. Active-high during the LSB of the last byte.

Path Overhead Access Channel (POAC)

AE3 RPOACCLK — O

Receive POAC Clock.

Receive side serial access channel

clock output for the path overhead bytes.

AD4 RPOACDATA — O

Receive POAC Data.

Receive side serial access channel

data output for the path overhead bytes.

Page 20

20 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

3.3.5 Miscellaneous Signals

Table 7. Miscellaneous Signals

3.3.6 DS3 Port

If a DS3 output is required in a Super Mapper application and the DS3 signal has been recovered (demapped) from an STS-1, then it is necessary to smooth the DS3 recovered clock. The DS3 clock extracted from the STS-1 clock will have considerable jitter introduced when the SONET overhead is removed and pointer adjustments are made. A phase locked loop is recommended for this purpose. The Super Mapper contains a phase comparator, that can be used in conjunction with an external low-pass filter and voltage controlled crystal oscillator to implement the PLL.

Pin Symbol Type I/O Description

AF4 RPOACSYNC — O

Receive POAC Synchr onization.

Receive side sync output for POAC channel. Active-high during the last bit of the last byte of the POAC frame.

AE4 TPOACCLK — O

T ransmit POA C Clock.

T ransmit side serial access channel

clock output for the path overhead bytes.

AD5 TPOACDATA — I

Pull down

Transmit POAC Data.

Transmit side serial access channel

data input for the path overhead b yte s.

AC5 TPOACSYNC — O

Transmit POAC Synchronization.

Transmit side sync output for POAC channel. Active-high during the last bit of the last byte.

Pin Symbol Type I/O Description

AE5 LOSEXT — I

Pull up

Loss of Signal External.

External loss of signal input. If external clock and data recovery is used on the high-speed I/O port, it may be connected to this input which can be configured to assert the LOS register bit normally associated with the internal LOS detection in the internal CDR bloc k. The polarity of LOS may be programmed active-high or low.

AD6, AE6,

AC6

AUTO_AIS — I/O

AIS Enable (3:1).

Control signal for automatic AIS insertion on each STS1. The STS-1 AIS is applied down stream on the telecom bus, i.e., it is an output from masters and an input to slaves. Active-high. Input when slave mode. Output when master mode If not used, leave open.

AD7 RH SFSYNCN — O

Receive High-speed Frame Synchronization.

Receive side frame sync output indicating the frame l ocation of the highspeed data input. May be used as a 8 kHz timing reference for network synchronization to the receive high-speed data input (STS-3 or STS-1).

Table 6. TOAC and POAC

(continued)

Page 21

21Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Table 8. DS3 Port

Pin Symbol Type I/O De scription

V22 PHASEDETUP — O P hase Detector Up. Phase error signal out to external filter

and VCXO. This output will generate an error signal when the VCXO output is slower than the reference signal.

U22 PHASEDETDOWN — O

Phase Detector Down.

Phase error signal out to external filter and VCXO. This output will generate an error signal when the VCXO output is faster that the reference signal.

R22 DS3POSDATAOUT — O

Positive Data Output.

Serial DS3 positive data out to LIU when the DS3 output port is operating in dual rail-mode. Nonreturn t o zero DS3 data output when the DS3 output is operating in single ended mode.

P22 DS3NEGDATAOUT — O

Negative Data Output.

Serial DS3 negative data output to LIU when the DS3 port is operating in dual rail mode. In single rail mode, this outpu t is not used and may be left unconnected.

N22 DS3DATAOUTCLK — I

Pull

down

DS3 Data Out Clock.

44.736 MHz DS3 clock input. If the Super Mapper is being used to map DS3 dat a to and from STS-1, then this clock will be supplied by the external VCXO that is associated with the DS 3 c lock recovery PLL. In other DS3 modes (e.g., M13) this input will be supplied by an external crystal oscillator, usually associated with a DS3 LIU. If the DS3 port is not used , this input may be tied to ground or left open, since it is equipped with an i nternal pull-down resistor.

M22 DS3POSDATAIN — I

Pull

down

Positive Data Input.

If the DS3 port is configured in dual-rail mode, then this input is serial positive data from an external DS3 LIU. If the DS3 port is configured in single-rail mode, then this input is serial nonreturn-to zero data from th e external LIU.

K22 DS3NEGDATAIN — I

Pull

down

Negative Data In.

In dual rail mode, this is negative data from an external DS3 LIU. In single rail mode, it may be connected to the bipolar violation output of the external DS3 LIU, left unconnected, or tied to ground.

J22 D S3DATAINCLK — I

Pull

down

DS3 Data In Clock.

This is a 44.736 MHz clock input from

the clock recovery in the external DS3 LIU.

Page 22

22 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Table 9. DS3 Port, C-Bit, and Datalink Access

3.3.7 M13 Multiplexer/Demultiplexer Receive Section

Two groups of s ignals are defined in this section. The first group are reference clocks, used internally in the jitter attenuation and AIS generation processes. Note that these are typically supplied by free-running crystal oscillators.

The outputs below provide access to the received C-bits and data link bits extracted from the received DS3 frame. These operate in the same way if the source of the DS3 signal is from an SPE or from the external DS3 port.

Pin Symbol Type I/O Description

E14 TCBSYNC — O

Transmit C-Bit Sync.

In the C-bit parity mode, 10 C-bits may optionally be input for multiplexing into the transmit DS3 frame through the TCBDATA input. The TCBSY NC output is low, except dur ing t he rising edge o f TCBCLK th a t is used to input C2.

E13 TCBCLK — O

Transmit C-Bit Clock.

A gapped clock (nominally 93.983 kHz) for

accepting selected C-bits on input M13_CBDATA.

E12 TCBDATA — I

Pull down

Transmit C-Bit Data.

In the C-bit parity mode, the network requirements b i t (C2), a nd the unused C-b its (C4, C5, C6, C16, C 17, C18, C19, C20, and C21) may optionally be inpu t for multiplexing into the transmit DS3 frame through this input.

E9 TDLCLK — O

Transmit Data Link Clock.

A gapped clock (nominally 28.195 kHz)

for accepting path maintenance data link C -b its on input TDLDATA .

E8 TDLDATA — I

Pull down

Transmit Data Link Data.

The path maintenance data link C-bits (C13, C14, and C15) may optionally be input for multiplexing into the transmit DS3 frame through this input.

Table 10. M13 Multiplexer/Demultiplexer Receive Section

Pin Symbol Type I/O Description

AC17 E1XCLK — I

Pulldown

E1 Reference Clock.

This clock is used as a reference for the jitter attenuator when it is operating in the E1 mode. It must have a frequency of 2.048 MHz, 32.768 MHz, or 65.536 MHz and a stability of 50 ppm. It is also used to generate an E1 AIS (all ones). May be left unconnected, or tied to ground, if no E1 options are being used.

AD16 DS1XCLK — I

Pulldown

DS1 Reference Clock.

This clock is used as a reference f or the jitte r attenuator when it is operating in the DS1 or the J1 mode. It must have a frequency of 1.544 MHz, 24.704 M H z, or 49.408 MHz and a stability of ±32 ppm. This clock sig n a l is also used to generate DS1 AIS signals. May be left unconnected or tied to ground, if not, no DS1 options are being used.

E10 DS2AISCLK — I

Pulldown

DS2 Reference Clock.

A 6.312 MHz ±30 ppm input. In the M23 mode, this clock is used to generate DS2 AIS. May be left unconnected or tied to ground if no DS2 options are being used . Note that C-bit parity mode does no require a DS2 reference clo ck .

E18 RCBSYNC — O

Receive C-Bit Sync.

Ten C-bits are output on RCD after they are demultiplexed from the received DS3 signal. The RCS output is low, except during the rising edge of RCD that is used to output C2.

Page 23

23Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

3.3.8 Low-Order Path Overhead Access Channel

Each VT has a low-order path overhead, and this interface allows access to all LOPOH bits for all V Ts. Note that the purpose of doing this is slightly different form the transport and path overhead access. These are used to cross couple the bits between links in a protection scheme, rather than provide access for examination or modification of the overhead, although that is possible too.

Table 11. Low-Order Path Overhead Access Channel

Figure 4. DS1/E1 to DXC Block Diagram

Pin Symbol Type I/O Description

E17 RCBCLK — O

Receive C-Bit Clock.

A gapped clock (nominally 93.983 kHz) for out-

putting selected C-bits on RCD.

E15 RCBDATA — O

Receive C-Bit Data.

The received network requirements bit (C2) and the received unused C-bits (C4, C5, C6, C16, C17, C18, C19, C20, and C21) are output after they are demultiplexed from the received DS3 signal.

E19 RDLCLK — O

Receive Data Link Clock.

A gapped clock (nominally 28.195 kHz)

for outputting path maintenance data link C-bits on RDLD.

H22 RDLDATA — O

Receive Data Link Data.

The received path maintenance data link C-bits (C13, C14, and C15) that are demultiplexed from the received DS3 signal.

Pin Symbol Type I/O Description

Transmit Direction

AC13 LOPOHCLKIN — I Pull down

6.48 MHz Low Order Path Overhead Clock.

AC14 LOPOHDATAIN — I Pull down

Low-Order Path Overhead Data.

(O-bits, V5, J2 ,

Z6/N2, Z7, and K4 byte.)

AB14 LOPOHVALIDIN — I Pull down

Valid LOPOH_DATA.

Receive Direction

AB15 LOPOHCLKOUT — O

6.48 MHz Low Order Path Overhead Clock.

AB17 LOPOHDATAOUT — O

Low-Order Path Overhead Data.

(O-bits,V5, J2,

Z6/N2, Z7/K4 byte.)

AB18 LOPO HVALIDOUT — O

Valid VTMPR_LOPOH_DATA Output.

Table 10. M13 Multiplexer/Demultiplexer Receive Section

(continued)

VT MAPPER VT MAPPER

LOPOH

OUTPUTS

LOPOH

INPUTS

LOPOH OUTPUTS

LOPOH INPUTS

TELECOM BU S

DS1/E1 TO DXC

Page 24

24 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Table 12. Multifunction System Interface Transmit Path Direction

Pin Symbol Type I/O Description

C13, A12,

B11, B10, B9,

D8, C8, A7, B6, D5, A4, A3, H5, F5, C2, D2, E2, F4, G2, H1,

J3, J4, K4, L4,

M2, N1 , P4 ,

LINERXDATA[28:1] — I

Pull down

Line Receive Data (28:1).

Configurable inputs to the internal cross connect. The use depends on the application. Generally, these inputs are used for the received positive-rail or single-rail DS1/E1 line data input. If operating in dual rail mode, the negative rail will be expected on LINERXSYNC(28:1). Using dual rail mode implies that the internal B8ZS or HDB3 decoders are enabled, and line code violation s c an be detected and counted inside the Super Mapper.

These data inputs may be assigned, using the cross connect block, to the DS1 or E1 inputs on the VT mapper, M13 or DS1/E1 framers. It is also possible to use the inputs for DS2 data, in which case they may be assigned to the M23 multiplexer inputs.

D13 LINERXDATA29 — I

Pull down

Receive Data 29.

Configurable input to the internal cross connect. May be used as an additional line receive data input, for a protection channel. Other possible uses are as follows:

Global transmit line clock input. Externally supplied

1.544 MHz or 2.048 MHz low jitter clock phase-locked to the TDM system clock. Used for transmit line clock on the DS1/E1 framers. This is not normally used, because the DS1/E1 framer has a PLL which ca n generate a

1.544 MHz clock from the TDM system clock (CHI clock). This applies in PSB and CHI modes.

Receive data input. If NSMI mode is used, this will be a

51.84 Mbits/s serial data input.

D12, C12,

C11, C10, A9,

B8, D7, C7,

C6, C5, C4,

C3, J5, B2,

D3, E3, F3,

G3, G4, H2,

J1, K3, L3,

M3, M4, N2,

P2, R4

LINERXCLK[28:1] — I/O

Pull down

Receive Clock (28:1).

Configurable inputs/outputs to the internal cross connect. Typically a line clock associated with the corresponding LINERXDATA input. It can therefore be running at DS1, E1 or DS2 rate. The cross connect is used to assign these inputs to the VT mapper, M13 or DS1/E1 framers.

B13 LINERXCLK29 — I/O

Pull down

Receive Clo ck 29.

May be used as additional receive clock input for a DS1/E1 protection channel. Also has special use as a mast er clock. In CHI mode, it is the receive clock input (2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz). In PSB mode, it is the receive clock input (19.44 MHz). In NSMI mode, it is the receive clock output. (51.84 MHz).

Page 25

25Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Pin Symbol Type I/O Description

B12, D11,

D10, D9, C9,

A8, B7, D6, B5, B4, B3, E6, K5, C1, D1, E4, F2,

G1, H3, H4,

J2, K2, L2,

M1, N3, N4,

P1, R2

LINERXSYNC[28:1] — I

Line Receive Synchronous 28:1.

Multifunction input. Channel assignment may be configured through t he internal cross connect. Can be used as the negative rail of a DS1/E1 signal in conjunction with LINERXDATA(28:1), when operating in dual-rail mode. In CHI mode these inputs are used for receive TDM highways that may run at 2.048, 4.096, or 8.192 Mbits/s. In p arallel system bus mode the receive system data b us inputs are assigned to LINERXSYNC 16:1. The PSB is a 16bit wide bus that operates at 19.44 MHz.

A13 LINERXSYNC29 — I/O

Line Receive Synchronous 29.

In CHI and PSB modes this input is used as the receive system frame synchronization input. In NSMI mode, it is the receive frame sync output

R25, P26, N23, N24, M26, L25,

K25, J25, H23, H24, G26, F25, E23, D26, C26, E21,

B24, B23, B22, D21,

B20, A19, C18, D18, D17, D16,

B15, A14

LINETXDATA[28:1] — I/O

Line Transmit Data (28:1)

Con figurable outputs from the internal cross connect. Used for transmit positiverail or singl e- r a i l DS1/E1 line data outputs. May be connected to the DS1/E1 outputs from the VT mapper, M13 MUX or DS1/E1 frame line outputs. May also be used as a DS2 output.

T23 LINETXDATA29 — O

Line Transmit D ata 29.

Configurable output from the internal cross connect. An extra DS1 or E1 transmit port that may be used f or protection o r as a timing reference output.

Table 12. Multifunction System Interface Transmit Path Direction

(continued)

Page 26

26 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Pin Symbol Type I/O Description

R23, P25,

N25, M23,

M24, L24,

K24, J26,

H25, G23,

G24, F24, E24, D24,

C24, B25, C23, C22, C21, C20,

D20, B19,

A18, C17, C16, C15,

D15, B14

LINETXCLK[28:1] — I/O

Line Transmit Clock (28:1).

Configurable outputs from the internal cross connect. Can be used as the clock signals for LINETXDATA(28: 1) in DS1, E 1, and DS2 modes.

R24 LINETXCLK29 — I/O

Line Transmit Clock 29.

Configurable output to the internal cross connect for the protection or timing reference channel. Also used as the transmit global sys tem clock input for CHI (2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz), PSB (19.44 MHz), and NSMI (51.84 MHz) modes.

P24, P23,

N26, M25,

L23, K23, J23,

J24, H26, G25, F23, E25, D25, C25, F22, A24, A23, D22, B21, A20, C19, D19, B18, B17, B16, A15, C14,

D14

LINETXSYNC[28:1] — I/O

Line Transmit Synchronous (28:1).

Configurable inputs/outputs to the internal cross connect. An output when used as the negative rail of a DS1 or E1 output port operating in dual-rail mode. In CHI mode, these pins may be used as output TDM highways. In PSB mode, bits 16:1 are used for the transmit data bus, and bits 28:17 are not used. These pins may also be used as DS2 I/O to the M12 block as follows: 7:1—Tx data out. 14:8—Tx clock in. 21:16—Rx data in. 28:22—Rx clock in.

R26 LINETXSYNC29 — I/O

Line Transmit Synchronous 29.

Configurable input/ output to the internal cross connect. An output when used as the negative rail of a DS1 or E1 output port operating in dual-rail mode. In CHI and PSB modes, it is used as the transmit system frame synchronization input. In NSMI mode, it is the transmit system frame sync output.

AB19 RXDATAEN — O

NSMI Receive Enable.

Receive data enable for NSMI

mode.

W22 TXDATAEN — O

NMSI Transmit Enable.

T ransmit data enable for NSMI

mode.

Table 12. Multifunction System Interface Transmit Path Direction

(continued)

Page 27

27Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

3.3.9 Framer PLL

The DS1/E1 framer has a phase-locked loop that may be used to generate a transmit line clock at 1.544 MHz or

2.048 MHz. The reference signal for this PLL may be chosen from a number of possible sources, all typ ically synchronized to the system clock (CHI transmit/receive clock for example.) In order to ensure reliable performance ,this PLL has its own isolated power pins. The PLL also has a number of tes t control pins that are used for factory testing only.

The PLL is active when framer bit PLL_BYPAS = 0. When PLL_BYPAS = 1, the PLL is bypassed and an external clock at the system interface is used as the line clock. An e xample would be when the framers are programmed for a CHI interface at 2.048 MHz and the frames are programmed for E1, the PLL may be bypassed and the CHI system clock may be used as the line clock.

Table 13 . Framer PLL

Pin Symbol Type I/O Description

AD22 VDDD_PLL VDD —

Digital VDD for PLL.

AE23 VDDS_PLL VDD —

Analog VDD for PLL.

AF23 VSSA_PLL VSS —

Analog VSS for PLL.

AD23 VSSS_PLL VSS —

Digital VSS for PLL.

AD24 CLKIN_PLL — I

Pull down

Clock In PLL.

Phase locked-loop reference clock input. Frequency should be consistent with the MODE_PLL pins in the PLL Mode1 table below. A 1.544 MHz clock for DS1 transmit outputs is generated synchronous t o this clock.

AB21 MODE2_PLL — I/O

PLL Mode 2.

Control bit that should be tied to the appropriate state depending on the frequency of CLKIN_PLL consistent with the PLL Mode1 table below. This pin is also used during factory testing as an output.

AF24 MODE0_PLL — I

Pull down

PLL Mode 0.

PLL control input 0.

AE24 MODE1_PLL — I

Pull down

PLL Mode 1.

PLL control input 1. The PLL mode inputs should be hardwired to the logic levels shown in the table below, depending on the frequency of the reference supplied to CLKIN_PLL.

Mode2

0 0 0 0 1 1 1 1

Mode1

0 0 1 1 0 0 1 1

Mode0

0 1 0 1 0 1 0 1

CLKIN_PLL

Reserved

51.84 MHz

26.624 MHz

19.44 MHz

16.348 MHz

8.194 MHz

4.096 MHz

2.048 MHz

Page 28

28 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

Table 14. Microprocessor Interfaces

Pin Sym bo l Type I/O Description

AE17 MPCLK — I

Processor Clock.

This is the synchronous microprocessor clock (when MPMODE=1). The maximum clock frequency is 66 MHz . This cl ock i s required to pr operly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. This clock must be within the range of 16 MH z—66 MHz.

AD17 MPMODE — I

Control Port Mode.

If the microprocessor interface is sy nchronous, CPM should be set to 1. If the microprocessor interface is asynchronous, CPM should be set to 0.

AC18 CSN — I

Pull up

Chip Select.

Active-low chip select. For synchronous mode, it should be stable beyond a certai n setup time before the rising clock edge when AS is active. For asynchronous mode, it should be stable before DS is asserted.

AE18 ADSN — I

Address Strobe.

Active-low address strobe that is a 1 PCK cycle wide pulse for synchronous mode and active for the entire read/write cycle for asynchronous m ode. Address bus signals, A(19:0), are transparently latched into Super Mapper when AS is low. The address bus should remain valid for the duration of AS.

AF18 RWN — I

Read/Write Cycle Selection.

RW is set high for a read oper-

ation, or set low for write operation.

AD18 DSN — I

Data Strobe.

DS is not used for synchronous mode. For asynchronous mode, write operation, DS becomes a ctive after dat a is stable . F or read operation, it is similar t o AS.

AB23, AC26,

AC24, AD25, AD26, AE25,

AA22, AC22,

AE22, AD21,

AE21, AC21, AD20, AF20, AE20, AC20, AD19, AF19,

AE19, AC19

ADDR[19:0] — I

Address (19:0).

A19 is the most significant and A0 the least sig nificant bit f or addr essi ng all the intern al SM registers during CPU access cycles.

Note:

The Super Mappe r is little endian, the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big- endian byte or dering.

AB25, AA24, AA25, AA23,

Y24, Y26,

Y25, Y23, W24, W26, W25, W23,

V24, V26,

V25, V23

DATA[15:0] — I/O

Data (15:0).

Data bus for all transfers between the CPU and the internal SM registers. The pins are inputs during write cycles and outputs during read cycles. DATA15 is the MSB and DATA0 is the LSB.

U24, U 2 5 PAR[1:0] — I/O

CPU Port Parity (1:0).

Byte-wide parity b its for data. CPP[1]

is the parity for D[15:8] and CPP[0] is the parity for D[7:0].

Page 29

29Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Table 15. General Purpose Interface

Pin Sym bo l Type I/O Description

U23 DTN — O

Open Drain

Data Transfer Acknowledge.

In synchronous CPU mode, DTA goes low at 4th cycle f o r write or 5th cycle for read, resulting in a fixed 2 wait-states for writes and 3 wait-states for reads. In asynchronous µP mode, after qualification of AS and DS by TLSC52 clock, DTA goes low for two TLSC52 clock cycles for writes and three TLSC52 clock cycles for reads. DTA goes high, along with the rising edge of AS.

AB24 INTN — O

Open Drain

Interrupt.

Super Mapper interrupt request, active-low . An open drain output should be connect ed to an external pull-up resistor.

AC25 APS_INTN — O

Open Drain

APS Interr upt.

Automatic protection switch interrupt request, active-low. An open drain output should be connected to an external pull-up resistor.

Pin Symbol Type I/O Description

T24 RSTN — I

Pull up

Reset.

Global reset, active-low. Initial i zes all internal registers

to their default state.

T25 PMRST — I/O

Pull down

Performance Monitor Reset.

May be configured as an input and then used to directly reset all the counters associated with DS1/E1 performance monitoring. If an internal PM reset is used, PMRST is configured as an output that indicates when a PM reset occurred.

R5 TCK — I

Test Clock.

This signal p rovides timing for the bound ary scan and TAP controller. This signal should be static, except during boundary scan testing.

U5 TDI — I

Pull up

Test Data In.

Data input for the boundary s c an; sampled on

the rising edge of TCK.

W5 TMSN — I

Pull up

Test Mode Select (Active-Low).

Controls boundary scan test

operations. TMS is sampled on the rising edge of TCK.

AB8 TRSTN — I

Pull down

Test Reset (Active-Low).

This signal is an asynchronous

reset for the TAP controller.

V5 TDO — O

Test Data Out.

Updated on the falling edge of TCK. The TDO

output is high impedance, except when scanning out test data.

AB9 IC3STATEN — I

Pull up

Global Output Enable.

All output and bidirectional buffers will be high impedance when this input is low. Normally pulled high internally.

Table 14. Microprocessor Interfaces

(continued)

Page 30

30 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

3.3.10 Test Pins

These pins are for factory test purposes only and must be connected as stated below for n orm al operation. They are used to establish special configurations for testing, inserting test data, etc. For normal operation they should be left unconnected; each is equipped with a pull-up or pull-down to the inactive (normal operation) state.

Table 16. Test Pins

Table 17. CDR Power

Pin Symbol Type I/O Description

N5 SCAN_EN — I

Pull down

Test Only.

Scan enable (active-high).

M5 SCAN_MODE — I

Pull down

Test Only.

Serial scan input for testing (act ive-high).

P5 IDDQ —

Pull up

Test Only.

Q input (active-high).

AE14 BYPASS — I

Pull down

Test Only.

Enables functional bypassing of the clock synthesis

with a test clock (active-high).

AF14 TSTPHASE —

Pull down

Test Only.

Controls bypass of 32 PLL-generated phases with

32 low-speed phases, generated by test logic (active-high).

AD14 ECSEL —

Pull down

Test Only.

Enables external test control of 155 MHz clock phase selection through ETOGGLE and EXDNUP inputs (active-high).

AC15 ETOGGLE —

Pulldown

Test Only.

Moves 155 MHz clock selection one phase per positive pulse > 20ns. Active + pulse.

AE15 EXDNUP —

Pulldown

Test Only.

Direction of phase changes. 0 = down 1 = up.

AF15 TSTMODE —

Pulldown

Test Only.

Enables CDR test mode.

AD15 TSTSFTLD —

Pulldown

Test Only.

Enables CDR test mode shift register.

AE16,

AC16

TSTMUX[1:0] — O

Test Only.

CDR test mode output

Pin Symbol Type I/O Description

AC9 VDDA_CDR — I

Analog Power.

Isolated analog power supply VDD for CDR.

AB12 VSSA_CDR — I

Analog Ground.

Isolated analog power supply VSS for CDR.

Table 18. LVDS Control Pins

Pin Symbol Type I/O D escription

AF12 AE12

RESHI

RESLO

— I

Resistor 1, 2.

A 100 Ω 1% resistor is sh ould be connected between

these two pins as a reference for the LVDS input buffer termination.

AC11 REF10 — I

Voltage Reference 1.

1.0 V reference voltage input.

AD12 REF14 — I

Voltage Reference 2.

1.4 V reference voltage input.

Page 31

31Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information

(continued)

Pin Symbol Type I/O Description

AB10 CTAPRH ——

Center Tap 1.

For RHSD P/N and RHSC P/N. Optional, 0.1 µF capacitor connected between CTAP pin and ground, to improve the common mode rejection of the LVDS input buffers.

AE11 CTAPTH ——

Center Tap 2.

For THSD P/N and THSC P/N. Optional, 0.1 µF capacitor connected between CTAP pin and ground, to improve the common mode rejection of the LVDS input buffers.

AB13 CTAPRP ——

Center Tap 3.

For RPSD155 P/N and RPSC155 P/N. Optional,

0.1 µF capacitor connected between CTAP pin and ground, to improve the common mode rejection of the LVDS input buffers.

Table 18. LVDS Control Pins

(continued)

Page 32

32 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

3 Pin Information

(continued)

3.4 Outlin e D iagr a m

3.4.1 456-Pin PBGA

Dimensions are in millimeters.

5-6216(F)r.1

0.56 ± 0.06

1.17 ± 0.05

2.33 ± 0.21 SEATING PLANE

SOLDER BALL

0.60 ± 0.10

0.20

PWB

MOLD

COMPOUND

35.00 ± 0.20

35.00

± 0.20

+0.70 –0.00

30.00

+0.70 –0.00

30.00

A1 BALL

IDENTIFIER ZONE

AE AD AC

V U T R

25 SPACES @ 1.27 = 31.75

P N M

1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 2620

11 13 15 17 2119 23 25

E D C

CENTER ARRAY

FOR THERMAL

ENHANCEMENT

(OPTIONAL)

25 SPACES

@ 1.27 = 31.75

A1 BALL

CORNER

0.75 ± 0.15

Page 33

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

33Agere Systems Inc.

4 Electrical Characteristics

Table of Contents

Contents Page

4 Electrical Characteristics ....................................................................................................................................3 3

4.1 Absolute Maxi mum Rat ings ..... .......... ................ .......... ......... .......... ................ .......... ......... ..........................3 4

4.2 Handling Precautions ...................................................................................................................................34

4.3 Operati ng Conditions ........... ......... ......... .................................................. .......... ......... .................................3 4

4.4 Logic Interface Characteristics .................................................................................... .................................35

4.5 LVDS Interfa ce Cha ra c te ristics ........................................................... .......... ......... .......... ............................ 36

List of Figures

Figure 5. Single-Ended Input S pecification ............................................................................................................35

List of Tables

Table 19. Absolute Maximum Ratings ................................................................................................................... 34

Table 20. Handling Precaution ..............................................................................................................................34

Table 21. Recommended Operating Conditions ...................................................................................................34

Table 22. Logic Interface Characteristics .............................................................................................................. 35

Table 23. LVDS Inter face Characteristics ...................................................................................... .......................36

Page 34

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

34 Agere Systems Inc.

4 Electrical Characteristics

(continued)

4.1 Absolute Maximum Ratings

Stresses in excess of the absolut e maximum ratings can caus e permanent damage to the device. These are absolute stress ratings only. Func t ional operation of the device is not impli e d at thes e or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely af fect devic e re liability.

4.2 Handlin g Pr ec au t ion s

Although protection circuitry has been designed into thi s device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere e mploys a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and prote ction design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the d efi ned model. No in dustry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitanc e = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters:

4.3 Operat i ng Co ndition s

The following tables list the voltages required for proper operation of the TMXF28155 device, along with their tolerances.

Table 21. Recommended Operating Conditions

* Internal reference voltage is used if SMPR_LVDS_REF_SEL = 1 (Table 70); or else exte rnal volt ag e is us ed .

Table 19. Absolute Maximum Ratings

Parameter Symbol Min Max Unit

dc Supply Voltage Range V

–0.5 4.6 V

Power Dissipation P

——mW Storage Temperature Range Tstg –65 125 °C Ambient Operating Tem perature Range T

–40 85 °C Maximum Voltage (digital input pins) ——5.25 V Minimum Voltage (digital input pins) —–0.3 — V

Table 20. Handling Precaution

Device Voltage

TMXF28155 2000 V

Parameter Symbol Min Typ Max Unit

Power V

3.14 3.3 3.47 V

Ground V

— 0.0 — V

Input Voltage, High V

VDD – 1.0 — 5.25 V

Input Voltage, Low V

— 1.0 V

1.0 V, LVDS Reference* LVDS_REF10 — 1.0 — V

1.4 V:,LVDS Reference* LVDS_REF14 — 1.4 — V

Page 35

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

35Agere Systems Inc.

4 Electrical Characteristics

(continued)

4.4 Logic Int e r fac e Charact e ri st ic s

Table 22. Logic Interface Characteristics

The input specification for the remaining (nonbalanced) inputs are specified in Figure 5

5-6032(F)r.2

Figure 5. Single-Ended Input Specification

Parameter Symbol Test Conditions Min Max Unit

Input Leakage I

——1.0 µA

Output Current:

Low High

— —

2 2

mA mA

Output V oltage:

Low High

— —

VDD – 0.5

0.5

5.25

V V

Input Capacitance C

— — 1.5 pF

Page 36

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

36 Agere Systems Inc.

4 Electrical Characteristics

(continued)

4.5 LVDS Interface Characteristics

3.3 V ± 5% VDD, 0—125 °C, slow—fast process.

Table 23. LVDS Interface Characteristics

* Buffer will not produc e o utput transition when input is open-circuited.

Parameter Symbol Test Conditions Min Typ Max Unit

Input Buffer Parameters

Input Voltage Range, V

or V

GPD

| < 925 mV, dc—1 MHz 0.0 1.2 2.4 V

Input Differential Threshold V

IDTH

GPD

| < 925 mV, 311 MHz –100 — 100 mV

Input Differential Hysteresis V

HYST

(+V

IDTH

) – (–V

IDTH

) —— —*mV

Receiver Differential Input

Impedance

With built-in termination,

center-tapped

80 100 120 Ω

Output Buffer Parameters

Output V oltage:

Low (V

or VOB)

High (V

or VOB)

LOAD

= 100 Ω ±1%

LOAD

= 100 Ω ±1%

—

0.925——

1.475

—

V V

Output Differential V ol tage |V

LOAD

= 100 Ω ±1% 0.25 — 0.40 V

Output Offset Voltage V

LOAD

= 100 Ω ±1% 1.125 — 1.275 V

Output Impedance, Single Ended R

VCM = 1.0 V and 1.4 V 40 50 6 0 Ω

Mismatch Between A and B ∆R

VCM = 1.0 V and 1.4 V —— 10 %

Change in Differential Voltage

Between Complementary States

|∆V

LOAD

= 100 Ω ±1% —— 25 mV

Change in Output Offset Voltage

Between Complementary States

∆V

LOAD

= 100 Ω ±1% —— 25 mV

Output Current I

, I

Driver shorted to V

—— 24 mA

Output Current I

SAB

Drivers shorted together —— 12 mA

Page 37

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

37Agere Systems Inc.

5 Timing Characteristics

Table of Contents

Contents Page

5 Timing Characteristics ........................................................................................................................................ 37

5.1 TMUX Block Timi ng ................. ................................. .......... ......... .......... ................ ...................................... 39

5.2 DS3 Timing ......... ......... .......... ................ .......... ......... .................................. ......... ........................................ 43

5.3 M13 Timing ......... ......... ................. ......... .......... ................................. .......... ......... ........................................ 44

5.4 VT Mapper Timing ......................................... ......... .......... ................................. ......... ................................. 4 5

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing ................................................................. 45

5.5 Concentration Highway (CHI) Tim ing .................................................................. ........................................ 46

5.6 Parall e l Syst e m Bus Timin g ................. .......... ......... ................. ......... .......... ................................................. 4 7

5.7 NSMI Timing Mode 1 ................................................................................................................................... 49

5.8 SMI Timing Mode 2 (8 pin) . .......................................................................................................................... 49

5.9 Framer Onl y Mode Timi n g .................................... ......... .......... ................ .......... ......... .................................51

5.10 Framer—LIU Mode Timing ........................................................................................................................ 5 3

5.11 Microprocessor Interface Timing ................................................................................................................ 54

5.11.1 Synchronous Mode ................................................................. ............ ....... ............ .......................... 54

5.12 Asynchronous Mode .................................................................................................................................. 56

5.13 General Purpose Interface Timing .............................................................................................................60

6 Ordering Information............................................................................................................................................ 61

Figures Page

Figure 6. Generic Clock Timing..............................................................................................................................39

Figure 7. Generic Interface Data Timing ................................................................................................................41

Figure 8. VT Mapper Transmit Path Overhead Detailed Timing ............................................................................ 45

Figure 9. VT Mapper Receive Path O verhead Detailed Timing .............................................................................45

Figure 10. CHI Transmit I/O Timing........................................................................................................................46

Figure 11. CHI Receive I/O Timi n g.......... ......... ............................................................ ..........................................47

Figure 12. Para l lel System Bus Interface Tr a n smi t I/O Ti ming........... ......... .......... ......... ........................................48

Figure 13. Parallel System Bus Interface Receive I/O Timing................................................................................48

Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1).................................54

Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1).................................55

Figure 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0) ............ 57

Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0) ...............................59

Tables Page

Table 24. High-speed Input Clock Specifications ..................................................................................................39

Table 25. Output Clock Specifications ...................................................................................................................40

Table 26. Input Timing Spec ificatio ns ....................................................................................................................41

Table 27. Output Timing Specifications .................................................................................................................42

Table 28. DS3 Input Clock Specifications .............................................................................................................43

Table 29. Input Timing Spec ificatio ns ....................................................................................................................43

Table 30. Output Timing Specifications .................................................................................................................43

Table 31. M13 Clock Specifications ......................................................................................................................44

Table 32. Input Timing Spec ificatio ns ....................................................................................................................44

Table 33. Output Timing Specifications .................................................................................................................44

Table 34. VT Mapper Receive Path Overhead Detailed Timing ............................................................................45

Table 35. CHI Transmit Timing Characteri stics ......... ............................................................................................46

Table 36. CHI Receive Timing Characteristics ......................................................................................................47

Table 37. PSB Interface Transmit Timing Characteristics .....................................................................................47

Page 38

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

38 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table of Contents

(continued)

Tables Page

Table 38. PSB Interface Receive Timing Characteristics ......................................................................................48

Table 39. NSMI (Mode 1) Input Clock Specifications ............................................................................................49

Table 40. Input Timing Specifications ... .................................................................................................................49

Table 41. Output Timing Specifications .................................................................................................................49

Table 42. SMI (Mod e 2) I nput Clock Specif ications ........... .................................................................................... 49

Table 43. Input Timing Specifications ... .................................................................................................................50

Table 44. Output Timing Specifications .................................................................................................................50

Table 45. Framer Only Mode Clock Specificat ions ............................................................................................... 51

Table 46. Framer Mode Only Input Timing Specifications ..................................................................................... 52

Table 47. Framer Mode Only Output Timing Specifications .................................................................................. 52

Table 48. Framer—LIU Mode Clock Specifications ............................................................................................... 53

Table 49. Framer—LIU Mode Input Timing Specifications ....................................................................................54

Table 50. Framer—LIU Mode Output Timing Specificat ions .................................................................................54

Table 51. Microprocessor Interface Synchro nous Write Cycle Specifications ......................................................55

Table 52. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................... 56

Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications .....................................................58

Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................... 60

Table 55. Input Timing Specifications ... .................................................................................................................60

Table 56. Output Timing Specifications .................................................................................................................61

Page 39

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

39Agere Systems Inc.

5 Timing Characteristics

(continued)

5.1 TMUX Bl ock Timing

The TMUX (STS-N/STM-1) timing parameters can be grouped separately for clocks, inputs, and outputs. Table 24 shows the input clock specifications for this device. The rise and fall times refer to the transition times from 10% to 90% of full swing.

For definitions of the signal names, see the pin descriptions section at the begi nning of this data sheet.

Table 24. High-speed Input Clock Specifications

Note: When th e t ru e and complement inputs are floati n g, the input buffer wi l l not oscillate.

5-9077(F)

Figure 6. Gene ric Clock Tim ing

Symbol Parameter Signal Name 155 Clock 51 Clock Unit

Min Nom Max Min Nom Max

fCK Operating

Frequency

THSCP/N — 155.52 ±30 ppm —— 51.84 ±50 pp m — MHz

RHSCP/N — 155.52 ±30 ppm —— 51.84 ±50 ppm — MHz

RPSC155P/N — 155.52 ±30 ppm — MHz

tCK Clock

Period

THSCP/N — 6.43 ±0.4% —— 19.29 ±0.4% — ns RHSCP/N — 6.43 ±0.5% —— 19.29 ±0.5% — ns

RPSC155P/N — 6.43 ±0.5% —— ns

tCLKHI Clock

Pulse High

Time

THSCP/N 2.5 — 3.9 7.8 — 11.6 n s RHSCP/N 2 .5 — 3.9 7.8 — 11.6 ns

RPSC155P/N 2.5 — 3.9 — ns

tR Rise Time THSCP/N ——1.5 ——5.0 ns

RHSCP/N ——1.5 ——5.0 ns

RPSC155P/N ——1.5 — ns

tF Fall Time THSCP/N ——1.5 ——5.0 ns

RHSCP/N ——1.5 ——5.0 ns

RPSC155P/N ——1.5 — ns

CLKHI

Page 40

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

40 Agere Systems Inc.

5 Timing Characteristics

(continued)

The output clock specifications are shown in Table 25, where the symbols match the waveform diagram above.

Table 25. Output Clock Specifications

* The specifica tions for the table are with all loopbacks disab led.

Note:

Any of the telecom signals bei ng used as inputs (slave Super Mapper) need to meet these same output clock specifications.

Signal Name Reference CLK

Frequency Clock Pulse High

Time (t

CLKHI)

Test

Condition

Max Rise

Time (t

Max Fall Time (t

TLSCLK THSCP/N 19.44 MHz 24.43—27.00 ns CL = 50 pF 3.5 ns 3.5 ns

TTOACCLK THSCP/N 5.184 MHz 91.62—101.3 ns C

= 15 pF 3.5 ns 3.5 ns

RLSCLK RHSCP/N or

Internal CDR Clock

19.44 MHz 24.43—27.00 ns C

= 50 pF 3.5 ns 3.5 ns

RTOACCLK RHSCP/N or

Internal CDR Clock

5.184 MHz 91.62—101.3 ns C

= 15 pF 3.5 ns 3.5 ns

TPSC155P/N THSCP/N 155.5 MHz 3.119—3.311 ns C

= 15 pF 1.5 ns 1.5 ns

TPOACCLK THSCP/N 5.184 MHz 91.62—101.3 ns C

= 15 pF 3.5 ns 3.5 ns

RPOACCLK RHSCP/N 5.184 MHz 91.62—101.3 ns C

= 15 pF 3.5 ns 3.5 ns

TLSC52 THSCP/N 51.84 MH z 9.162—10.13 ns C

= 30 pF 3.0 ns 3.0 ns

RLSC52 RHSCP/N 51.84 MHz 9.162—10.1 3 n s C

= 30 pF 3.0 ns 3.0 ns

Page 41

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

41Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 2 6 . Input Timing Specifications

Figure 7. Generic Interface Data Timing

Input Name Reference CLK Min Setup Time (t

Min Hold Time (t

Transmit Signa ls

THSSYNC THSC ↑ 2.0 ns 0.0 ns

TLSDATA[7:0] TLSCLK ↑ 5.0 ns 0.0 ns

TLSPAR TLSCLK ↑ 5.0 ns 0.0 ns TLSSPE TLSCLK ↑ 5.0 n s 0.0 ns

TLSJ0J1V1 TLSCLK ↑ 5.0 ns 0.0 ns

TLSV1 TLSCLK ↑ 5.0 ns 0.0 ns

TLSSYNC52 TLSC52 ↑ 4.0 ns 0.0 ns

TTOACDATA TTOACCLK ↑ 10.0 ns 0.0 ns

TPOACDATA TPOACCLK ↑ 10.0 ns 0.0 ns

Receive Signals

RHSDP/N RHSCP/N ↑↓ 2.0 ns 0.0 ns

RPSD155P/N RPSC155P/N 2.0 ns 0.0 ns

RLSDATA[7:0] RLSCLK ↑ 5.0 ns 0.0 ns

RLSPAR RLSCLK ↑ 5.0 ns 0.0 ns

RLSSPE RLSCLK ↑ 5.0 ns 0.0 ns

RLSJ0J1V1 RLSCLK ↑ 5.0 ns 0.0 ns

RLSV1 RLSCLK ↑ 5.0 ns 0.0 ns

RLSSYNC52 RLSC52 ↑ 4.0 ns 0.0 ns

Miscellaneous Si gnals

LOSEXT NA ASYNC ASYNC

AUTO_AIS[3:1] NA ASYNC ASYNC

CLOCK

DATA

CLOCK

DATA

Page 42

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

42 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 27 . Output Timing Specifications

* Propagation delay skew, t

PLH

– t

PHL

, is ±200 ps.

Output Name Reference CLK Test

Conditions

Propagation Delay* Unit

Min Max

Transmit Signals

THSDP/N THSCP/N ↑ C

= 15 pF 0.6 2.9 ns

TPSD155P/N TPS C 155P/N C

= 15 pF 0.6 2.9 ns

TLSDATA[7:0] TLSCLK ↑ C

= 50 pF 4.0 12.0 ns

TLSPAR TLSCLK ↑ C

= 50 pF 4.0 12.0 ns

TLSSPE TLSCLK ↑ C

= 50 pF 4.0 12.0 ns

TLSJ0J1V1 TLSCLK ↑ C

= 50 pF 4.0 12.0 ns

TLSV1 TLSCLK ↑ C

= 50 pF 4.0 12.0 ns

TLSSYNC52 TLSC52 ↑ C

= 30 pF 0.0 6.0 ns

TTOACSYNC TTOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

TPOACSYNC TPOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

Receive Signals

RLSDATA[7:0] RLSCLK ↑ C

= 50 pF 4.0 12.0 ns

RLSPAR RLSCLK ↑ C

= 50 pF 4.0 12.0 ns

RLSSPE RLSCLK ↑ C

= 50 pF 4.0 12.0 ns

RLSJOJ1V1 RLSCLK ↑ C

= 50 pF 4.0 12.0 ns

RLSVI RLSCLK ↑ C

= 50 pF 4.0 12.0 ns

RLSSYNC52 RLSC52 ↑ C

= 30 pF 0.0 6.0 ns

RTOACSYNC RTOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

RTOACDATA RTOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

RPOACSYNC RPOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

RPOACDATA RPOACCLK ↑↓ C

= 15 pF 10.0 30.0 ns

RHSFSYNCN RLSCLK ↓ C

= 30 pF 0.0 8.0 ns

Miscellaneous Signals

AUTO_AIS[3:1] NA — ASYNC ASYNC —

Page 43

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

43Agere Systems Inc.

5 Timing Characteristics

(continued)

5.2 DS3 T imi n g

Table 28. DS3 Input Clock Specifications

Table 2 9 . Input Timing Specifications

Table 30 . Output Timing Specifications

Symbol Parameter Signal Name Min Max Unit

Clock Frequency DS3DATAINCLK

DS3DATAOUTCLK

— —

44.736 MHz ±50 ppm —

Clock Period DS3DATAINCLK

DS3DATAOUTCLK

— —

22.353

CLKHI

Clock Pulse High Time DS3DATAINCLK

DS3DATAOUTCLK

6 6

16 16

Rise Time DS3DATAINCLK

DS3DATAOUTCLK

02ns

Fall Time DS3DATAINCLK

DS3DATAOUTCLK

02ns

Input Name Reference CLK Min Setup Time (t

Min Hold Time (t

DS3POSDATAIN DS3DATAINCLK ↑↓ 40

DS3NEGDATAIN DS3DATAINCLK ↑↓ 40

Output Name Reference CLK Test Conditions Propagation Delay t

Unit

Min Max

DS3POSDAT AOUT DS3DAT AOUTCLK ↑↓ C

= 15 pF 2 6 ns

DS3NEGDATAOUT DS3DATAOUTCLK ↑↓ C

= 15 pF 2 6 ns

Page 44

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

44 Agere Systems Inc.

5 Timing Characteristics

(continued)

5.3 M13 T im i ng

Table 31. M13 Clock Specifications

Table 3 2 . Input Timing Specifications

Table 33 . Output Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

Clock

Frequency

TCBCLK

TDLCLK E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

— —

2.048

1.544

— — —

93.983 gapped

28.195 gapped

32.768

24.704

6.312

93.983

28.195

— —

65.536

49.408

— — —

kHz

kHz MHz MHz MHz

kHz

CLKHI

Clock Pulse

High Time

TCBCLK

TDLCLK

RCBCLK

RDLCLK

212.19

223.53

250.77

Rise Ti me TCBCLK

TDLCLK E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

0 0 0 0 0 0 0

— — — — — — —

3 3 3 3 3 3 3

Fall Time TCBCLK

TDLCLK E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

0 0 0 0 0 0 0

— — — — — — —

3 3 3 3 3 3 3

Input Name Reference CLK Setup Time (t

) Hold Time (tH)Unit

Min Max Min Max

TCBDATA TCBCLK ↑ 50 — 0 — ns TDLDATA TDLCLK ↑ 50 — 0 — ns

Output N a me Reference CLK Test Conditions Propag a t ion Delay t

Unit

Min Max

TCBSYNC TCBCLK ↑ C

= 15 pF 2 10 ns

RCBSYNC RCBCLK ↑ C

= 15 pF 2 10 ns

RCBDATA RCBCLK ↑ C

= 15 pF 2 10 ns

RDLDATA RDLCLK ↑ C

= 15 pF 2 10 ns

Page 45

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

45Agere Systems Inc.

5 Timing Characteristics

(continued)

5.4 VT Mapper Timing

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing

Table 34. VT Mapper Receive Path Overhead Detailed Timing

5-9078(F)

Figure 8. VT Mapper Transmit Path Overhead Detailed Timing

5-9079(F)

Figure 9. VT Mapper Receive Path Overhead Detailed Timing

Symbol Parameter Min Max Unit

Clock Frequency 6.48 6.48 MHz

Clock Period 154 154 ns

CLKHI

Clock Pulse High Time 50 7 5 ns

Clock Rise Time 0 3 ns

Clock Fall Time 0 3 ns

LOPOH Data Setup Time 5 — ns

LOPOH Data Hold Time 0 — ns

LOPOH Valid Signal Setup Time 5 — ns

LOPOH Valid Signal Hold Time 0 — ns

PDV

Clock to LOPOH Valid Signal Out 0 5 ns

PDD

Clock to LOPOH Data O ut 0 5 ns

LOPOHC LKIN

LOPOHVALIDIN

LOPOHDATAIN

PDV

PDD

LOPOHCLKOUT

LOPOHVALIDOUT

LOPOHDATAOUT

Page 46

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

46 Agere Systems Inc.

5 Timing Characteristics

(continued)

5.5 Concentration Highway (CHI) Timing

Table 35 and Table 3 6 with Figure 10 and Figure 11, respec tively, illustrate the detailed CHI timing for clock, data,

and frame synchronization.

Table 35. CHI Transmit Timing Characteristics

*fCK can be eit her 2.048 MH z, 4.096 MHz, 8.192 MHz, or 16.384 MHz.

5-9080(F)

Figure 10. CHI Transmit I/O Timing

Symbol Parameter Min Max Unit

Clock Frequency* 2.048 16.384 MHz

Clock Period 488.2 61. 04 ns

Clock Rise Time 0 3 ns

Clock Fall Time 0 3 ns

Frame Sync Setup Time 35 — ns

Frame Sync Hold Time 0 — ns

Clock to CHI Data Delay — 25 ns

LINETXCLK29

LINETXSYNC29

LINETXSYNC[28:1]

CLOCK

FRAME SYNC

DATA

Page 47

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

47Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 36. CHI Receive Timing Characteristics

*fCK can be eit h er 2.048 M H z , 4.096 MHz, 8.192 MHz, or 16.384 MHz.

5-9081(F)

Figure 11. CHI Receive I/O Timing

5.6 Parallel Sy ste m Bus T im in g

Table 37 and Table 3 8 with Figure 12 and Figure 13, respectively, show the transmit and receive timing. In the

transmit direction (to the system interface) the frame sync is sampled and the data is clocked out on the rising edge of the clock. In the receive direction (from the switch) the data and frame sync are sampled on the rising edge of the clock.

Table 37. PSB Interface T ransmit Timing Characteristics

Symbol Parameter Min Max Unit

Clock Frequency* 2.048 16.384 MHz

Clock Period 488.2 61.04 ns

Clock Rise Time 0 3 ns

Clock Fall Time 0 3 ns

SSYNC

Frame Sync Setup Time 30 — ns

HSYNC

Frame Sync Hold Time 0 — ns

SDATA

CHI Data Setup Time 25 — ns

HDATA

CHI Data Hold Time 0

—

Symbol Parameter Min Max Unit

Clock Frequency 19.44 19. 44 MHz

Clock Period 51.44 51.44 ns

Clock Rise Time 0 3 ns

Clock Fall Time 0 3 ns

Frame Sync Setup Time 8 — ns

Frame Sync Hold Time 0 — ns

Clock to PSB Out Delay 3 10 ns

HDATA

LINERXCLK29

LINERXSYNC29

LINERXSYNC[28:1]

CLOCK

FRAME SYNC

DATA

SSYNC

HSYNC

SDATA

tCK

Page 48

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

48 Agere Systems Inc.

5 Timing Characteristics

(continued)

5-9082(F)

Figure 12. Parallel System Bus Interface Transmit I/O Timing

Table 38. PSB Interface Receive Timing Characteristics

5-9083(F)

Figure 13. Parallel System Bus Interface Receive I/O Timing

Symbol Parameter Min Max Unit

Clock Frequency 19.44 19.4 4 MHz

Clock Period 51.44 51.4 4 ns

Clock Rise Time 0 3 ns

Clock Fall Time 0 3 ns

SSYNC

Frame Sync Setup Time 8 — ns

HSYNC

Frame Sync Hold Time 0 — ns

SDATA

PSB to Clock Setup Time 8 — ns

HDATA

PSB Hold Time from Clock 0

—

DEV #0, TS #1, DEV #0, TS #1,

tPD

STUFFED TS STUFFED TS

6 (3) STUFFED TS IN DS1 (E1)

tHtS

LINETXCLK29

LINETXSYNC29

LINETXSYNC[16:1]

CLOCK

FRAME SY NC

DATA

LINK #0 LINK #1

tCK

DATA SAMPLED

tSDATA tHDATA

DEV #0, TS #1, DEV #0, TS #1,

STUFFED TS STUFFED TS

tHSYNCtSSYNC

LINERXCLK29

LINERXSYNC29

LINERXSYNC[16:1]

CLOCK

FRAME SYNC

DATA

LINK #0 LINK #1

tCK

Page 49

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

49Agere Systems Inc.

5 Timing Characteristics

(continued)

5.7 NSMI T im ing Mod e 1 (6 Pi n)

Table 3 9 . N SMI (Mode 1) Input Clock Specifi c ations

Table 4 0 . Input Timing Specifications

Table 41 . Output Timing Specifications

5.8 SMI Timi n g Mo d e 2 (8 Pi n)

Table 4 2 . SMI (Mode 2) Input Clock Specifications

Symbol Parameter Signal Name Min Nom M ax Unit

Clock Frequency

LINE_TXCLK29

LINE_RXCLK29

— —

51.84/44.736 ±50 p pm

— —

MHz MHz

CKHI

Clock Pulse High Time

LINE_TXCLK29

LINE_RXCLK29

6 6

— —

12 12

ns ns

Rise Time LINE_TXCLK29

LINE_RXCLK29

— —

3 3

ns ns

Fall Time LINE_TXCLK29

LINE_RXCLK29

— —

3 3

ns ns

Input Name Reference CLK Setup Time (t

) Hold Time (tH)Unit

Min Max Min Max

LINE_RXDATA29 LINE_RXCLK29 ↓ 5 — 0 — ns

LINE_RXSYNC29 LINE_RXCLK29 ↓ 5 — 0 — ns

Output Name Reference CLK Test Conditions Propagation Delay t

Unit

Min Max

LINE_TXDATA29 LINE_TXCLK2 9 ↑ C

= 15 pF 0 3.5 ns

LINE_TXSYNC29 LINE_TXCLK29 ↑ C

= 15 pF 0 3.5 ns

RXDATAEN LINE_TXCLK29 ↑ C

= 15 pF 0 3.5 ns

TXDATAEN LINE_TXCLK29 ↑ C

= 15 pF 0 3.5 ns

Symbol Parameter Signal Name Min Nom Max Unit

Clock

Period

LINE_TXCLK29 LINE_RXCLK29

RXDATAEN

44.736 MHz ±50 ppm TBD TBD

19.29

19.29 TBD

TBD TBD TBD

ns ns ns

CKHI

Clo ck Pulse

High Time

LINE_TXCLK29 LINE_RXCLK29

RXDATAEN

6 6

TBD

1/3 tck

1/3 or 1/2 tck

TBD

TBD TBD TBD

ns ns ns

Rise Time LINE_TXCLK 29

LINE_RXCLK29

RXDATAEN

0 0 0

— — —

3 3 3

ns ns ns

Fall Time LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

0 0 0

— — —

3 3 3

ns ns ns

Page 50

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

50 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 4 3 . Input Timing Specifications

Table 44 . Output Timing Specifications

Input Name Reference CLK Setup Time (t

) Hold Time (tH)Unit

Min Max Min Max

LINE_RXDATA29 LINE_RXCLK29 ↓ 5 — 0 — ns

LINE_RXSYNC29 LINE_RXCLK29 ↓ 5 — 0 — ns

Output Name Reference CLK Test Conditions P ropagation Delay t

Unit

Min Max

LINE_TXDATA29 LINE_TXCLK29 ↑ C

= TBD pF 0 3.5 ns

LINE_TXSYNC29 LINE_TXCLK29 ↑ C

= TBD pF 0 3.5 ns

TXDA TAEN RXDATAEN ↑ C

= TBD pF 0 3.5 ns

Page 51

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

51Agere Systems Inc.

5 Timing Characteristics

(continued)

5.9 Frame r O nly Mode Timing

Table 45. Framer Only Mode Clock Specifications

Symbol Parameter Sig nal Name Min Nom Max Unit

Clock Frequency

TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

–50 ppm

–130 ppm

–50 ppm

–130 ppm

–50 ppm –50 ppm –50 ppm –50 ppm

–130 ppm

–50 ppm –50 ppm –50 ppm –50 ppm

51.84

1.544

or 2.048

1.544

2.048 or 4.096 or 8.192

or 16.384

1.544 or 2.048 or 4.096 or 8.192

or 16.384

50 ppm

130 ppm

50 ppm

130 ppm

50 ppm 50 ppm 50 ppm 50 ppm

130 ppm

50 ppm 50 ppm 50 ppm 50 ppm

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

CKHI

Clock Pulse High Time

TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

12 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ns ns ns ns ns ns ns ns ns ns ns ns ns

Rise Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

0 0 0 0 0 0 0 0 0 0 0 0 0

— — — — — — — — — — — — —

3 3 3 3 3 3 3 3 3 3 3 3 3

ns ns ns ns ns ns ns ns ns ns ns ns ns

Page 52

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

52 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 45. Framer Only Mode Clock Specifications

(continued)

Table 46 . Framer Mode Only Input Ti ming Specifications

Table 47. Framer Mode Only Outp ut Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

Fall Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

0 0 0 0 0 0 0 0 0 0 0 0 0

— — — — — — — — — — — — —

3 3 3 3 3 3 3 3 3 3 3 3 3

ns ns ns ns ns ns ns ns ns ns ns ns ns

Input Name Reference CLK Setup Time (t

) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[28:1] LINERXCLK[28:1] ↑ 25 — 0 — ns

LINERXSYNC[28:1] LI NERXCLK [ 28: 1] ↑ 30 — 0 — ns

LINERXSYNC29 LINERXC LK 29 ↑ 30 — 0 — ns LINETXSYNC29 LINETXCLK29 ↑ 35 — 0 — ns

Output Name Reference CLK Test Conditions Propagation Delay t

Unit

Min Max

LINETXDATA[28:1] LINETXCLK[28:1] ↑ C

= TBD pF 25 TBD ns

LINETXDATA29 LINETXCLK29 ↑ C

= TBD pF 25 TBD ns

LINETXSYNC[28:1] LINETXCLK[28:1] ↑ C

= TBD pF TBD TBD ns

Page 53

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

53Agere Systems Inc.

5 Timing Characteristics

(continued)

5.10 Fram er —LIU Mode Timin g

Table 48. Framer—LIU Mod e Clock Specifications

Symbol Parameter Signal Name Min Nom Max Unit

Clock Frequency

TLSC52

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

51.84 TBD

2.048

or 4.096 or 8.192

or 16.384

TBD

or 2.048 or 4.096 or 8.192

or 16.384

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

MHz TBD MHz MHz MHz MHz TBD MHz MHz MHz MHz

CKHI

Clock Pulse High Time

TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ns ns ns ns ns ns ns ns ns ns ns ns ns

Rise Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

0 0 0 0 0 0 0 0 0 0 0 0 0

— — — — — — — — — — — — —

3 3 3 3 3 3 3 3 3 3 3 3 3

ns ns ns ns ns ns ns ns ns ns ns ns ns

Fall Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

0 0 0 0 0 0 0 0 0 0 0 0 0

— — — — — — — — — — — — —

3 3 3 3 3 3 3 3 3 3 3 3 3

ns ns ns ns ns ns ns ns ns ns ns ns ns

Page 54

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

54 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 49. Framer—LIU Mode Input Timi ng Specific a tions

Table 50. Framer—LIU Mode Output Timing Specifications

5.11 Microprocessor Interface Timing

5.11.1 Synchronous Mode

The synchronous microprocessor interface mode is selected whe n MPMODE (pin AD17) = 1. Interface timing for the synchronous mode write cycle is given in Figure 14 and in Table 51 and for the read cycle in Figure 15 and in

Table 52.

Note:

In addition to the MP U_CLK, the VT mapper block also requires TLSC52,TLSSYNC52, RLSC52, RLSSYNC52 signals to access specific por tions of the register map. The user needs to make sure that the VT_RD Y bit is set before VT_MAPPER reads/writes can occur.

5-7659(F)a

Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA [28:1] LINERXCLK [28:1] ↑↓ TBD 35 35 — ns

LINERXDATA29 LINERXCLK29 ↑↓ TBD 35 35 — ns

LINERXSYNC[28:1] LINERXCLK[28:1] ↑↓ TBD 35 35 — ns

LINERXSYNC29 LINERXCLK29 ↑↓ TBD 35 35 — ns

Output Name Reference CLK Test Conditions Propagation Delay t

Unit

Min Max

LINETXDATA[28:1] LINETXCLK[28:1] ↑↓ C

= TBD pF –35 35 ns

LINETXDATA29 LINE TX CLK 29 ↑↓ C

= TBD pF –35 35 ns

LINETXSYNC[28:1] LINETXCLK[28:1] ↑↓ C

= TBD pF –35 35 ns

LINETXSYNC29 LINETXCLK29 ↑↓ C

= TBD pF –35 35 ns

MPCLK

ADDR[9:0]

CSN

ADSN

RWN

DATA[1 5:0]

DTN

(66 MHz MAX)

(INPUT)

tADSNVS

tWS

tDTNVPD

tWS

tCSNVS

tWS

tCLK T1 T2 T3 Tn – 2 Tn – 1Tn

tAIPD

tAPD

tDTNIPD

HIGH ZHIGH Z

tADSNVDTF

Page 55

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

55Agere Systems Inc.

5 Timing Characteristics

(continued)

MPCLK 16 MHz minimum to 66 MHz maximum frequency. ADDR [19:0] The address will be available throughout the entire cycle. DATA[15:0 ] Data will be available during cycle T1. RWN (Input) The read (H ) w r ite (L) signal is always high except during a write cycle. CSN (Input) Chip select is an active-low signal. DTN (Output) Dat a transfer acknowledge is active-low for one clock and then driven high before entering a high-

impedance state. (This is done with an I/O pad using the input as f eedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low.

ADSN (In pu t) Address strobe is ac tive -low. ADSN must be 1 MPCLK clock period wide.

Table 51. Microprocessor Interface Syn chronous Write Cycle Specifications

(See Figure 14 on page 54 for the timing diagram. )

5-7660(F).a

Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)

Symbol Para m et er Setup (ns)

(Min)

Hold (ns)

(Min)

Delay (ns)

(Max)

Delay (ns)

(Min)

CLK

MPCLK 16 MHz Min—66 MHz Max Frequency ————

ADDR, RWN, DATA (write) Valid to MPCLK 3.5 0 — —

APD

MPCLK to ADDR, RWN, D ATA, CSN (wr ite) Invalid — 5 — —

CSNVS

CSN Valid to MPCLK 3.5 0 — —

ADSNVS

ADSN Valid to MPCLK 5.5 0 — —

AIPD

MPCLK to ADSN Invalid — 5 — —

DTNVPD

MPCLK to DTN Valid ——16 4

DTNIPD

MPCLK to DTN Invalid ——16 4

ADSNVDTF

ADSN Valid to DT Falling ——1000 —

MPCLK

ADDR[9:0]

CSN

ADSN

RWN

(66 MHz MAX)

tADSNSU tSNIPD

tCSNSU

tAVS

T0 T1 T2 Tn – 4Tn – 3Tn – 2Tn – 1 Tn

DTN

DATA[15:0]

(OUTPUT)

tDAIPD

tDVPD

tDIPD

tADSNVDTF

HIGH Z

tAPD

Page 56

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

56 Agere Systems Inc.

5 Timing Characteristics

(continued)

MPCLK 16 MHz minimum to 66 MHz maximum frequency. ADDR [19:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns

high. DATA [15:0] Read data is stable in Tn –1. RWN (Input) The read (H) write (L) signal is always high during the read cycle. CSN (Input) Chip select is an active-low signal. DTN (Output) D at a transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one

clock and then driven high before entering a high- impedance state. (This is done with an I/O pad

using the input as feedback to qualify the 3-state term.) DT will become 3-stated when CS is high.

Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low. ADSN (In pu t) Addr e s s strobe is active-low. ADSN must be one MPCLK clock period wide.

Table 52. Microprocessor Interface Syn chronous Read Cycle Specifications

(See Figure 15 on page 55 for the timing diagram. )

5.12 Asynchronous Mode

The asynchronous microprocessor interface mode is selected when MPMODE (pin AC18) = 0. Interface timing for the asynchronous mode write cycle is given in Figure 16 and in Table 53, and for the read cycle in Figure 17 and in

Table 54 (see pages 59—60).

Symbol Parameter Setup (ns)

(Min)

Hold (ns)

(Min)

Delay (ns)

(Max)

CLK

MPCLK 1 6 MHz Min—66 M Hz Max Frequency ———

AVS

ADDR Valid to MPCLK 3.5 0 —

APD

MPCLK to ADDR Invalid — 5 —

CSNSU

CSN Active to MPCLK 3.5 0 —

ADSNSU

ADSN Valid to MPCLK 5 .5 0 —

SNIPD

MPCLK to ADSN Inactive — 5 —

DVPD

MPCLK to DTN Valid —— 8

DIPD

MPCLK to DTN Invalid —— 8

DAIPD

MPCLK to DATA 3-state ——8

ADSNVDTF

ADSN Valid to DT Falling ——1000

Page 57

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

57Agere Systems Inc.

5 Timing Characteristics

(continued)

5-7661(F).ar.1

Figu re 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0)

ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-

able throughout the entire cycle.

DATA [15:0] Write data is asynchronously pas s ed f r om the host bus to the internal bus. Data will be available

throughout the entire cycle. RWN (Input) The read (H ) w r ite (L) signal is always high except during a write cycle. CSN (Input) Chip select is an active-low signal. DTN (Output)Dat a transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN.

DTN is driven high until the internal transaction is done. DTN is driven high again when eith e r ADSN

or DSN is deasserted. DTN will become 3-stated when CSN is high. ADSN (In pu t) Addr e s s strobe is active-low. ADSN must be a minimum of one MPCLK clock period wide. DSN (Input) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

(INPUT)

tAVADSF

tDVDSF

tCSFDTR

tDSFDTF

tADSRDTR

tCSRDT3

tDSRDI

tDSRRWR

tDSNRAI

tADSRAI

tAICSR

tRWFDSF

tAVDSF

HIGH Z HIGH Z

tCSFDSF

Page 58

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

58 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications

(See Figure 16 on page 57 for the timing diagram.)

* Simulation results.

† Falling edges o f ADSN and DSN determine falling edge of DTN. ‡ DTN fall is variable, depending on the block selected for access, and may be longer than the typical maximu m spec ifi e d.

§ Rising edge of ADSN determines rising edge of DTN.

Note:

Specifications are valid for 50 MHz M P CLK with MPMODE = 0. Address strobe (ADSN) and chip select (CSN) may be connected and driven from the same source. In this configuration, the setup and hold times for ADSN must be satisfied.

Symbol Parameter Min Interval (ns) Max Interval (ns)

CSFDSF

CSN Fall to DSN Fall 0 —

AICSR

ADDR Invalid to CSN Rise 0 —

AVADSF

ADDR Valid to ADSN Fall 0 —

ADSRAI

ADSN Rise to ADDR Invalid 0 —

AVDSF

ADDR Valid to DSN Fall 0 —

DSNRAI

DSN Rise to ADDR Invalid 0 —

RWFDSF

RWN Fall to DSN Fall 0* —

DSRRWR

DSN Rise to RWN Rise 0* —

DVDSF

DATA Va l id to DSN Fall 0* —

DSRDI

DSN Rise to DATA Invalid 0* —

CSFDTR

CSN Fall to DTN Rise 20 —

DSFDTF

DSN Fall to DTN Fall 120 280

†‡

ADSRDTR

ADSN Rise to DTN Rise 20

—

CSRDT3

CSN Rise to DTN 3-state 10 —

Page 59

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

59Agere Systems Inc.

5 Timing Characteristics

(continued)

5-7662(F).ar.1

Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)

ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-

able throughout the entire cycle. DATA [15:0] Read data on the internal bus is only valid for one clock cycle; therefore, a latch is necessary to meet

the correct timing on the host bus. RWN (Input) The read (H) write (L) signal is always high during a read cycle. CSN (Input) Chip select is an active-low signal. DTN (Output)Dat a transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN,

DSN, and ADSN. DTN is driven high while the internal bus transaction is in progress. There is no

need to provide synchronization to outgoing signals in this mode. DTN is driven high and then placed

in a high-impedance state when either ADSN or DSN is deasserted. DTN will become 3-stated when

CSN is high. ADSN (In pu t) Addr e s s strobe is active-low. DSN (Input) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

DTN

DATA[15:0]

tADSRD3

tCSRDT3

tADSRDTR

tCSFDSF

RWN

tAVADSF

tAVDSF

tAICSR

tADSRAI

tDSNRAI

tDTVDV

tDSFDTF

tCSFDTR

HIGH Z

Page 60

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

60 Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications

(See Figure 17 on page 59 for the timing diagram. )

Notes: 1 DSN can be asserted up to 20 ns (1 clk at 50 MHz) previous to CSN.

2 ADDR can be asserted up t o 60 n s (3 c lk at 5 0 MHz) into cycle from AS DN. 3 DTN fall is variable depending on the block selected for access and may be longer than typical maximum specified. 4 Leadin g edges of A D SN a nd D S N de termine the falling ed ge of DTN. 5 Rising edge of ADSN determines the rising edge of DTN. 6 Data toggle 20 ns (1 clk at 50 MHz) previous to CSN.

Note:

5.13 General Purpose Interface Timing

Table 5 5 . Input Timing Specifications

Symbol Parameter Min Interval (ns) Max Interval (ns)

CSFDSF

CSN Fall to DSN Fall 0

—

AICSR

ADDR Invalid to CSN Rise 0 —

AVADSF

ADDR Valid to ADSN Fall 0 60

ADSRAI

ADSN Rise to ADDR Invalid 0 —

AVDSF

ADDR Valid to DSN Fall 0 —

DSNRAI

DSN Rise to ADDR Invalid 0 —

CSFDTR

CSN Fall to DTN Rise 20 —

DSFDTF

DSN Fall to DTN Fall 100 280

3, 4

ADSRDTR

ADSN Rise to DTN Rise 20 —

CSRDT3

CSN Rise to DTN 3-state 10 —

DTVDV

DTN Valid to DATA Valid 0

—

ADSRD3

ADSN Rise to DATA 3-state 20 —

Input Name Reference CLK Min Setup Time (t

Min Hold Time (t

JTAG Signals

TDI TCLK ↑ 15.0 ns 2.0 ns

TMSN TCLK ↑ 15.0 ns 2.0 ns

TRSTN NA ASYNC ASYNC

SCAN_EN NA ASYNC ASYNC

SCAN_MODE NA ASYNC ASYNC

Miscellaneous Si gnals

RSTN NA ASYNC ASYNC

PMRST NA ASYNC ASYNC

IC3STATEN NA ASYNC ASYNC

IDDQ NA ASYNC ASYNC

Page 61

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

61Agere Systems Inc.

5 Timing Characteristics

(continued)

Table 56 . Output Timing Specifications

* Propagation delay skew, t

PLH

– t

PHL,

is ±200 ps.

6 Ord ering Information

Output Name Reference CLK Test Conditions Propagation Delay* (t

PD)

Unit

Min Max

Transmit Signals

TDO TLCK ↓ C

= 25 pF 3.0 20.0 ns

Miscellaneous Si gnals

PMRST NA — ASYNC ASYNC —

Device Code Package Temperature Comcode

TMXF281553BAL-2-DB 456-pin PBGA –40 °C to 85 °C 108700055

Page 62

62 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

Table of Contents

Contents Page

7 Microprocessor Interface and Global Control and Statu s Registers ........... ....................... ................. ................ 62

7.1 Super Mapper Global Control and Status Registers .................................................................................... 63

7.2 Microproce ssor Interface Register Map..................................................... .......... ......... .......... ...................... 73

Tables Page

Table 57. SMPR_VCR, Super M apper V ersion Control R egist er (RO) .................................................................63

Table 58. SMPR_SYMR[4], Super M apper Symbol Regis ter4 SMPR (RO) ......................................................... 63

Table 59. SMPR_SYMR[3], Super M apper Sym bol Register3 (RO) .....................................................................63

Table 60. SMPR_SYMR[2], Super M apper Sym bol Register2 (RO) .....................................................................63

Table 61. SMPR_SYMR[1], Super M apper Sym bol Register1 (RO) .....................................................................64

Table 62. SMPR_SYMR[0], Super M apper Sym bol Register0 (RO) .....................................................................64

Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO) ................................................................... 64

Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW) ............................................... .. ..... ..... .. ......65

Table 65. SMPR_GTR, Global Trigger Register (RW) .......................................................................................... 66

Table 66. SMPR_MSRR, Block Software Reset Register (RW) ........................................................................... 66

Table 67. SMPR_GCR, Global Control Register (RW) ...................... ................................................................... 68

Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW) ............. .......... ......... .......... ...................... 69

Table 69. SMPR_FCR, Framer Control Register (RW) ......................................................................................... 69

Table 70. SMPR_CLCR, CDR and LVDS Control Register (RW) ......................... .. .. ..... ... .. .. ... .. .. ..... .. ... .. ..... ........ 70

Table 71. SMPR_CPCR, Clock and Power Control Register (RW) ...................................................................... 71

Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) ...................................... ..... .. ... .. .. ..... .............71

Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW) ................................ ..... .. ..... .. ..... .. ..... ..... .. ..... .72

Table 74. SMPR_SR, Scratch Register (RW) .......... ......... .......... ......... .......... .......................................................72

Table 75. SMPR_TX_LINE_EN1 ........................................................................................................................... 72

Table 76. Microprocessor Interface Register Map ................................................................................................. 73

Page 63

63Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers

(continued)

7.1 Super Mapper Global Control and Status Registers

This section gives a brief description of each register bit and its functionality. The abbreviations after each register indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W) .

Table 57. SMPR_VCR, Super Mapper Version Control Register (RO)

Table 58. SMPR_SYMR[4], Super Mapper Symbol Regist e r4 SMPR (R O)

Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO)

Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO)

Address Bit Name Function Res et Default

0x00000 15:11 —

Reserved.

0x0000

10:8 SMPR_VERSION[2:0]

Super Mapper Version Number.

SMPR version

7:0 SMPR_ID[7:0]

SMPR ID Num b er.

Address Bit Name Function Reset Default

0x00001 15:8 T

Super Mapper Symbol Bit.

0x544D

7:0 M

Super Mapper Symbol Bit.

Address Bit Name Function Reset Default

0x00002 15:8 X

Super Mapper Symbol Bit.

0x5846

7:0 F

Super Mapper Symbol Bit.

Address Bit Name Function Reset Default

0x00003 15:8 2

Super Mapper Symbol Bit.

0x3238

7:0 8

Super Mapper Symbol Bit.

Page 64

64 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO)

Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO)

T ab le 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO)

Address Bit Name Function Reset Default

0x00004 15:8 1

Super Ma pper Symbol Bit.

0x3135

7:0 5

Super Ma pper Symbol Bit.

Address Bit Name Function Reset Default

0x00005 15:8 5

Super Ma pper Symbol Bit.

0x350D

7:0 CR

Super Ma pper Symbol Bit.

Address Bit Name Function Reset

Default

0x00008 15 SMPR_APS_IS

APS Interrupt.

Active-high signal indicating an interrupt event has occurred in the automatic protection switch (APS) block, which is within the TMUX block.

0x0000

14:10 —

Reserved.

9SMPR_PARITY_IS

Microprocessor Interface Data Bus Parity Error Interrupt.

Active-high signal indicating a µP data bus parity error has occurred. Summary of errors detected in PAR[ 1] and PAR[0] parity detectors.

8 SMPR_PMRESET_IS

Performance Monitor Reset Interrupt.

Active-high signal

indicating a 1 second event has occurred.

7SMPR_TPG_IS

TPG Interrupt.

Active-high signal indicating an interrupt event has occurred in the test pattern generation block.

6 SMPR_DJA_IS

DJA Interrupt.

Active-high signal indicating an interrupt event

has occurred in the digital jitter attenuation block.

5SMPR_FRM_IS

FRM Inte rrupt.

Active-high signal indicating an interrupt event has occurred in the framer block. However, on device powerup, this bit is erroneously set. A device initialization routine containing the following sequence should clear the interrupt:

■

Power up the framer block by selecting one of the clock options in address 0x00012.

■

Set and clear the framer software reset bit, bit of address 0x0000E.

■

Power down the framer block in address 0x00012.

4SMPR_XC_IS

XC Interrupt.

Active-high signal indicating an interrupt event

has occurred in the cross conne ct block.

3 SMPR_M13_IS

M13 Interrupt.

Active-high signal indicating an interrupt event

has occurred in the M13 multiplexer/demultiplexer block.

2 SM PR_VTMPR_IS

VTMPR Interrupt.

Active-high signal indicating an interrupt

event has occurred in the VT mapper block.

1 SMPR_SPEMPR_IS

SPEMPR Interru pt.

Active-high signal indicating an interrupt

event has occurred in the SPE mapper block.

0 SMPR_T MUX_IS

TMUX Interrupt.

Active-high signal indicating an interrupt

event has occurred in the TMUX block.

Page 65

65Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW)

Address Bit Name Function Reset

Default

0x00009 15 SMPR_APS_IM

APS Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin APS_INTN.

0x83FF

14:10 —

Reserved

9 SMPR_PARITY _IM

Microprocessor Interface Data Bus Parity Error Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will

be inhibited from contributing to the interrupt pin INTN.

8 SMPR_PMRESET_IM

Performance Monitor Reset Interrupt Mask.

When this bit is set to 1, the com posite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

7SMPR_TPG_IM

TPG Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

6 SMPR_DJA_IM

DJA Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

5 SMPR_FRM_IM

FRM Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

4SMPR_XC_IM

XC Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

3 SMPR_M13_IM

M13 Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

2 SMPR_VTMPR_IM

VTMPR Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

1 SMPR_SPEMPR_IM

SPEMPR Interru pt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

0 SMPR_TMUX_IM

TMUX Interrupt Mask.

When this bit is set to 1, the composite interrupt bit will be inhibited from contributing to the interrupt pin INTN.

Page 66

66 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 65. SMPR_GTR, Global Trigger Register (RW)

Table 66. SMPR_MSRR, Block Software Reset Register (RW)

Address Bit Name Function Reset Default

0x0000D 15:10 —

Reserved.

0x0000

9 SMPR_BER_INS RT

Bit Error Rate Insertion.

When this bit is set to 1, this bit indicates to the Super Mapper that a bit error has to b e inserted in the appropri ate frame.

8 SMPR_PMRESET

Performance Monitor Reset.

When this bit is set to 1, the PMRESET signal will transition from a logic 0 to a logi c 1 s tate. It will stay at a logic 1 state for a minimum of 100 ns. (Self-clearing.)

7:1 —

Reserved.

0 SMPR_SWRS

Super Mapper Software Reset.

When this bit is set to 1, it will create a software reset of the device. This reset has the same effect as the hardware reset. All microprocessor registers are reset to their default states and all internal data path state machine are reset. (Self-clearing.)

Address Bit Name Function Reset

Default

0x0000E 15:8 —

Reserved.

0x0000

7 SM P R_TPG_ SW RS

TPG Block Software Reset.

When this bit is set to 1, it will create a software reset for the test-pattern generation macro. This reset has the same effects as the hardware reset and chip-level software reset. All microprocessor registers within the macro are reset to their default states. All internal data path state machine within the block are also reset.

6 SMPR _DJA_SWRS

DJA Block Software Reset.

When this bit is set to 1, it will create a software reset for the digital jitter attenuation block. This reset has the same effects as the hardware reset and chip-level software reset. All microprocessor registers within the macro are reset to their default states. All internal data path state machine within the block are also reset.

5 SMPR_FRM_SWRS

FRM Block Software Reset.

When this b it is se t to 1 , it w ill create a software reset for the framer bloc k. This reset has the same effects as the hardware reset and chip-level software reset. All microprocessor registers within the block are reset to their default states. All internal data path state machine within the block are also reset.

Page 67

67Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 66. SMPR_MSRR, Block Software Reset Register (RW)

(continued)

Address Bit Nam e Function Reset

Default

0x0000E 4 SMP R_XC_SWRS

XC Block Software Reset.

When this bit is set to 1, it will create a software reset for the cross connect block. This reset has the same effects as the hardware reset and chiplev el software reset. All microprocessor registers within t he block are reset to their def ault states. A ll internal data path state machine within the block are also reset.

0x0000

3 SMPR_M13_SWRS

M13 Block Software Reset.

When this bit is set to 1, it will create a software reset for the M13 multiplexer/demultiplexer block. This reset has the same effects as the hardware reset and chip-level software reset.

All microprocessor registers within the block are reset to their default states. All internal data path state machine within the block are also reset.

2 SMPR_VTMPR_SWRS

VTMPR Block Software Reset.

When this bit is set to 1, it will create a software reset for the VTMPR block. This reset has the same effects as the hardware reset and chip-level software reset. All microprocessor registers within the block are reset to their default states. All internal data path state machine within the block are also reset.

1 SMPR_SPEMPR_SWRS

SPEMPR Block Software Reset.

When this bit is set to 1, it will create a software reset for the SPEMPR block. This reset has the same effects as t he hardware reset and chip-level software reset. All microprocessor registers within the block are reset to their default states. All internal data path state machine within the block are also reset.

0SMPR_TMUX_SWRS

TMUX Block Software Reset.

When this bit is set to 1, it will create a software reset for the TMUX block. This reset has the same effects as the hardware reset and chip-level software reset. All microprocessor registers within the block are reset to their def ault states. A ll internal data path state machine within the block are also reset.

Page 68

68 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 67. SMPR_GCR, Global Control Register (RW)

Address Bit Name Function Reset

Default

0x0000F 15:10 —

Reserved.

0x0000

9:8 SMPR_PMMODE[1:0]

Performance Monitor Mode:

00 = PMRST comes from external pin. 10 = PMRST comes from external pin. 01 = PMRST comes from internal 1 second counter.

Note:

Please see Table 72 and Table 73.

11 = PMRST is software controlled using the

SMPR_PMREST register bit 8 (Table 65 on

page 66).

7:5 —

Reserved.

4 SMPR_PARITY_EVEN_ODD

Even or Odd Parity Indication on the Microprocessor Data Bus.

This bit controls the parity setting and

checking on the microprocessor data bus: 0 = Even parity on microprocessor byte data/parity bus.

1 = Odd parity on microprocessor byte data/parity bus.

3SMPR_OH_DEFLT

Overhead Default.

This bit c on t r ols the filling of the

unused overhead bytes: 0 = Filling the unused overhead bits with 0.

1 = Filling the unused overhead bits with 1.

2 SMPR_FXD_STFF_DEFLT

Fixed Stuff Default.

This bit control the filling of the

fixed stuff bytes: 0 = Filling t he fi xed stuff bytes with 0.

1 = Filling t he fi xed stuff bytes with 1.

1 SMPR_COR_COW

Clear On Read or Clear On Write.

This bit controls the way clearing is performed on all delta and event bits in all registers:

0 = The delta and event bit is cleared by writing a 1 to it.

Note:

The clear-on-write (COW) feature does not apply to all registers in the 28-channel framer block. The only framer block register that has COW is transmit FDL link register 8 (address 0x8LTD7). All other registers in the framer block are only clear-on-read.

1 = The de lta and event bit is cleared when a micr opro-

cessor read is performed on this delta and event bit.

0 SMPR_SAT_ROLLOVER

Saturate or Rollover.

This bit controls if error counters hold their values or rollover when they reach their ma ximum values.

0 = Error counters rollover when reaching maximum val-

ues.

1 = Error counters hold their values when reaching max-

imum values.

Page 69

69Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW)

Table 69. SMPR_FCR, Framer Control Register (RW)

Address Bit Name Function Reset

Default

0x00010 15:4 —

Reserved.

0x0000

3 MPU_RHDZTHD_LB

Forces Received High-speed to Transmit Highspeed Data Loopback Prior to the CDR.

2 SMPR_RE TIME_CLK_EDGE

Retime Clock Edge for the Received High-speed Data.

This bit controls on which clock edge, positive or negative, the received high-speed data is to retimed.

1 = The received data will be clocked into the device

on the negative clock edge.

0 = The received data will be clocked into the device

on the positive clock edge.

1 SMPR_TELECOMBUS_EDGE

Telecom Bus Edge.

When the SPE mapper is enabled to use a time slot on the telecom bus. This bit selects the clock edge for the data signals transmitted to the telecom bus d uring the selected time slot.

0 = Clock telecom bus signals out on the falling edge. 1 = Clock telecom bus signals out on the rising edge.

0 SMPR_TMUX_MASTE R_S LAVE

SMPR/TMUX M aster Slave.

This bit controls if the TMUX block in this Super Mapper is the master device in the system module that this Super Mapper is on, or if it is a slave device.

0 = This Super Mapper/TMUX is a slave device in

the module.

1 = This Super Mapper/TMUX is a master device in

the module.

Address Bit Name Function Reset

Default

0x00012 15:3 —

Reserved.

0x0000

2:0 SMPR_FRM_CLK_ SEL[2:0]

Framer Clock Selection.

Selects the source of the framer high-speed clock the selected clock needs to be faster than the aggregate throughput of the framer block for proper operation.

000 = Framer is powered down. No clock required. 001 = Framer receives TLSC52 (pin AC3) clock input 010 = Framer receives DS1XCLK (pin AD16) clock input. 011 = Framer receives E1XCLK (pin AC17) clock input.

Page 70

70 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 70. SMPR_CLCR, CDR, and LVDS Control Register (RW)

Address Bit Name Function R eset

Default

0x00013 15:11 —

Reserved

. 0x000C

10 SMPR_MPU_CDR_MODE

CDR Mode Selection.

This bit controls the operating mode of the internal CDR; whether it operates at 155 MHz or 51 MHz.

0 = 155 MHz mode. 1 = 51 MHz mode.

9 SMPR_MPU_CG_PWRDN

PLL Powerdown Selection.

This bit controls whether

the internal framer PLL is powered on or off. 0 = Internal PLL powered on.

1 = In ter nal PLL powered off.

8 SMPR_LVDS_REF_SEL

LVDS Reference Voltage Selection.

This bit controls which reference voltage, internal or external, is used to power the LVDS buffers.

0 = External reference voltage is used. 1 = Internal reference voltage is used.

7:4 —

Reserved.

3 SMPR_RXPWRDN

CDR Channel Powerdown.

This bit controls the power

to the CDR data channel. 0 = Channel is active, power is on.

1 = Channel is inactive, power to the channel is turned off.

2 SM P R_P LLP WRDN

CDR Phase-Lock Loop Powerdown.

This bit controls

the power to the CDR PLL circuit. 0 = PLL is active, power to the PLL is turned on.

1 = PLL is inactive, power to the PLL is turned off.

1 SMPR_MRESET

CDR Master Reset.

This bit is used for the CDR initialization. It can also be used in test mode to reset test circuitry.

0 = No reset. 1 = Reset mode.

0 SMPR_CDR_SEL

CDR Selection.

This bit controls if the TMUX receives its high-speed receive clock and data from the on-chip CDR block or from the pins (bypass the CDR).

0 = Bypass CDR. Receives clock and data directly from

pins.

1 = Use CDR. Receives clock and data through CDR.

Page 71

71Agere Systems Inc.

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 71. SMPR_CPCR, C lock and Power Control Register (RW)

Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW)

Address Bit Name Fu nction Reset

Default

0x00014 15:9 —

Reserved.

0x0000

8 SMPR_M13_TCLK

M13 MUX/Tx Clock Enable.

0 = M13 MUX/Tx clock is powered down and inactive. 1 = M13 MUX/Tx clock is powered up and active.

7 SMPR_M13_RCLK

M13 DeMUX Rx Clo ck Enable.

0 = M13 deMUX/Rx clock is powered down and inactive. 1 = M13 deM UX/Rx clock is po wered up and active.

6 SMPR_DJA_CLK

Digital Jitter Attenuation Clock Enable.

0 = DJA DPLL is powered d own and inactive. 1 = DJA DPLL is powered u p and active.

5 SMPR_VTMPR_TCLK

VT Mapper Tx Clock Enable.

0 = VT mapper Tx clock is powered down and inactive. 1 = VT mapper Tx clock is powered up and active.

4 SMPR_VTMPR_RCLK

VT Mapper Rx Clock Enable.

0 = VT mapper Rx clock is powered and inactive. 1 = VT mapper Rx clock is powered up and active.

3 S M PR_SPEMPR_TCLK

SPE Mapper Tx Clock Enable.

0 = SPE mapper Tx clock is powered down and inactive. 1 = SPE mapper Tx clock is powered up and active.

2 SMPR_SPEMPR_RCLK

SPE Mapper Rx Clock Enable.

0 = SPE mapper Rx clock is powered down and inactive. 1 = SPE mapper Rx clock is powered up and active.

1 SMPR_TMUX_TCLK

TMUX Tx Clock Enable.

0 = TMUX Tx clock is powered down and inactive. 1 = TMUX Tx clock is power ed up and active.

0 SMPR_TMUX_RCL K

TMUX Rx Clock Enable.

0 = TMUX Rx clock is powered down and inactive. 1 = TMUX Rx clock is powered up and active.

Address Bit Name Function Res et

Default

0x00016 15:11 —

Reserved.

0x01F8

10:0 SMPR_P MRESET_HIGH_COUNT[10:0]

Performance Monitor Counter Preset.

The preset value of this register dete rmines the frequency of the internal PM counter. User should preload an appropriate value based on the microprocessor interface clock rate in ord er to reach the desire d PMRST rate.

Page 72

72 Agere Systems Inc.

TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW)

Table 74. SM PR_ SR , Scratch Register (RW)

Table 75. SMPR_TX_LINE_EN1

Address Bit Name Function Reset

Default

0x00017 15:0 SMPR_PMRESET_LOW_COUNT[15:0]

Performance Moni tor Counter Preset .

The preset value of this register determines the frequency of the internal PM counter. User should preload an appropriate value based on the microprocessor interface clock rate in order to reach the desired PMRST rate .

0x0000

Address Bit Name Function Reset

Default

0x0001F 1 5:0 SMPR_S CRATCH_REGISTER[15:0]

Scratch Register.

This register is for test

and diagnostics purpose. Read/write operations can be performed on

all bits. No SMPR control and status will be affected by an y read/write operations to this register.

0x0000

Address Bit Name Function Reset

Default

0x00018 15:0 SMPR_TX_LINE_EN[16:1]

3-State Control for LINETXDATA, LINETXCLK, and LINETXSYNC Output Pins.

0x0000

0x00019 12:0 SMPR_TX_LINE_EN[29:17]

3-State Control for LINETXDATA, LINETXCLK, and LINETXSYNC Output Pins.

0x0000

Page 73

Prelimi

nary Data Shee

t TMXF28155 S

uper Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

73Agere Systems Inc.

7 Microprocessor Interface and Global Control and Status Registers

(continued)

7.2 Microprocessor Interf ace Register Map

Table 76. Microprocessor Interface Register Map

Address Symbol Bit15Bit14Bit13Bit12Bit11Bit10Bit

Bit

Super Mapper V ersion Control Register—RO

0x00000 SMPR_VCR 0 0 0 0 0 S MPR_VERSION[2:0] SMPR_ID[7:0]

Super Mapper Symbol Register—RO

0x00001 SMPR_SYMR4 0x54 = T 0x4D = M 0x00002 SMPR_SYMR3 0x58 = X 0x46 = F 0x00003 SMPR_SYMR2 0x32 = 2 0x38 = 8 0x00004 SMPR_SYMR1 0x31 = 1 0x35 = 5 0x00005 SMPR_SYMR0 0x35 = 5 0x0D = CR 0x00006

—

0x00007

—

Super Mapper I nte rrupt Status Registe r—RO

0x00008 SMPR_ISR SMPR_APS_IS SMPR_

PARI TY_IS

SMPR_

PMRESET_IS

SMPR_TPG_IS SMPR_DJA_IS SMPR_FRM_ISSMPR_XC_IS SMPR_M13_ISSMPR_VTMPR_ISSMPR_

SPEMPR_IS

SMPR_TMUX_

Super Mapper Interrupt Mask Register—R/W

0x00009 SMPR_IMR SMPR_APS_IM SMPR_

PARI TY_IM

SMPR_

PMRESET_IM

SMPR_TPG_IM SMPR_DJA_IMSMPR_FRM_IMSMPR_XC_IM SMPR_M13_IMSMPR_VTMPR_IMSMPR_

SPEMPR_IM

SMPR_TMUX_

0x0000A

—

0x0000C

—

Global Trigger Register—R/W

0x0000D SMPR_GTR SMPR_BER_

INSRT

SMPR_

PMRESET

SMPR_SWRS

Block Software Reset Register—R/W

0x0000E SMPR_MSRR SMPR_TPG_SWRS SMPR_DJA_

SWRS

SMPR_FRM_

SWRS

SMPR_XC_

SWRS

SMPR_M13_

SWRS

SMPR_VTMPR_

SWRS

SMPR_SPEMPR_

SWRS

SMPR_TMUX_

SWRS

Global Control Register (SMPR_GCR)—R/W

0x0000F SMPR_GCR SMPR_PMMODE[1:0] SMPR_PARITY_

EVEN_ODD

SMPR_OH_

DEFLT

SMPR_FXD_ STFF_DEFLT

SMPR_COR_

COW

SMPR_SAT_ ROLLOVER

Page 74

TMXF28155 Super Ma pp er Prelimi nary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

Agere Systems Inc.

7 Microprocessor Interface and Global Control and Status Registers

(continued)

Tabl e 76. Microprocessor Interface Register Map (continued)

Address Symbol Bit

15:11

Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMUX and SPEMOR CONTROL Register—R/W

0x00010 SMPR_TSCR

MP0RH02THD_LB

SMPR_RETIME_

CLK_EDGE

SMPR_TELECOMBUS_

EDGE

SMPR_SMPR_TMUX_

MASTER_SLAVE

0x00011 —

FRAMER Control Register—R/W

0x00012 SMPR_FCR SMPR_FRM_CLK_SEL[2:0]

CDR and LVDS Control Register—R/W

0x00013 SMPR_CLCR — SMPR_MPU_C

DR_MODE

SMPR_MPU_

CG_PWRDN

SMPR_LVDS_

REF_SEL

SMPR_RXPWRDN SMPR_

PLLPWRDN

SMPR_MRESET SMPR_CDR_SEL

Clock and Power Control Register—R/W

0x00014 SMPR_CPCR SMPR_M13_

TXCLK

SMPR_M13_

RXCLK

SMPR_DJA_

CLK

SMPR_VTMPR_

TXCLK

SMPR_VTMPR_

RXCLK

SMPR_SPEMPR_

TXCLK

SMPR_SPEMPR_

RXCLK

SMPR_TMUX_

TXCLK

SMPR_TMUX_RXCLK

0x00015 —

PM Reset Count Register High—R/W

0x00016 SMPR_PMRCHR SMPR_PMRESET_HIGH_COUNT[10:0]

PM Reset Count Register Low—R/W

0x00017 SMPR_PMRCLR SMPR_PMRESET_LOW_COUNT[15:0] 0x00018 TX_LINE_EN1 TX_LINE_EN[16-1] 0x00019 TX_LINE_EN2

TX_LINE_EN[29-17]

Scratch Register—R/W

0x0001F SMPR_SR SMPR_SCRATCH_REGISTER[15:0]

Page 75

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

75Agere Systems Inc.

8 TMUX Registers

Table of Contents

Contents Page

8 TMUX Registers .................................................................................................................................................7 5

8.1 TMUX Register Descri p tions ........... .......................... ................................................................................... 7 7

8.2 TMUX Register Map ..... .......... ......... .......... ................................................................................................. 124

Tables Page

Table 77. TMUX_ID_R, TMUX Identification Register (RO) ..................................................................................77

Table 78. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W) .................................................................77

Table 79. TMUX_RCV_TX _M ODE , TMUX Receive/Transmit M ode (R/W ) ...... .......... ......... .......... ......... .......... ....77

Table 80. TMUX_TX_DLT, Delta/Event (COR/COW) ...........................................................................................78

Table 81. TMUX_RPS_ DL T, De lta/Event (COR/COW ) ................. .......... ......... ........................................... .........78

Table 82. TMUX_RHS_D L T, De lta/Event (CO R /CO W) ........................................................................................79

Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) ............................................................................81

Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) ..........................87

Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) .......................88

Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) ....................... 88

Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) .................. 89

Table 88. TMUX_ APSINT_MSK, Mask Bits for APSINT Inte r r u p t Signal (R/W) (Mask = 1, No Mask = 0) ........... 91

Table 89. TMUX_TX _ STATE, State Parameters (RO) ........... .......... ................ .......... ......... ................. ................91

Table 90. TMUX_RPS_STATE, S t ate and Value Parameters (RO) ..................................................................... 91

Table 91. TMUX_RHS_STATE, State and Value Parameters (RO) .....................................................................92

Table 92. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) .........................................................92

Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W) .....................................................94

Table 94. TMUX_RLS_BITBLK_CTL, Receive Low-speed Control Parameters (R/W) ........................................94

Table 95. TMUX_RL S_MO D E_CTL , Receiv e Low- sp eed Cont ro l Par a mete r s (R/W) ..........................................95

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) ............................................... 96

Table 97. TMUX_LOSDETCNT, Receive Low-speed Control Parameters (R/W) ................................................ 97

Table 98. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W) ..........................98

Table 99. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W) ......................... 99

Table 100. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Control Parameters (R/W) ............................100

Table 101. TMUX_RF1MON, Receive Monitor Values (RO) .............................................................................. 100

Table 102. TMUX_RAPSMON, Receive Monitor Values (RO) ...........................................................................100

Table 103. TMUX_RS1MON, Receive Monitor Values (RO) .............................................................................. 100

Table 104. TMUX_RP OHMON[1—3][A—D], Receive Monitor Values (RO) .......................................................101

Table 105. TMUX_TLS_CTL, Transmit Low-speed Control Parameters (R/W) ..................................................102

Table 106. TMUX_THS_PORT_CTL, Transmit High-speed Port Control Parameters (R/W) .............................103

Table 107. TMUX_THS_TO H_CTL, Transm it Hig h-speed Control Parameters (R/ W) .......................................103

Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-speed Control Parameters (R/W) .............................105

Table 109. TMUX_TLRDI_CTL, Transmit Hig h-speed Line RDI Co ntrol Parameters (R/W) ..............................109

Table 110. TMUX_TPRDI_CTL, Transmit High-speed Path RDI Control Parameters (R/W) .............................109

Table 111. TMUX_TZ0_INS_V A L, Transmit TOH and POH Insert Values (R/W) .............................................. 110

Table 112. TMUX_TS1 _F1_ INS_VA L, Transmit TOH and POH Insert Values (R/W) ........................................110

Table 113. TMUX_TAPS_IN S_V AL, Transmit TOH and POH Insert Values (R/W) .. .........................................110

Table 114. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Valu es (R/W) ............................. 110

Table 115. TMUX_TBERINS_CTL , Transmit High-speed Error Insertion Control Parameters (R/W) ................ 112

Table 116. TMUX_THS_ER R_CTL, Transm it Hig h-speed Error Insertion Control Parameters (R/W) ............... 113

Table 117. TMUX_TOA C_CT L, Receive/Transmit TOAC /P OA C C ontrol Parameters (R/W) .............................113

Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) ..........................115

Table 119. TMUX_TFRAM EO FF SET, Transmit H igh-speed Offset Control Parameters (R/W) ......................... 116

Table 120. TMUX_S D_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) ..........................1 16

Page 76

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

76 Agere Systems Inc.

8 TMUX Registers

(continued)

Table of Contents

(continued)

Tables Page

Table 121. TMUX_S F_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W) ................................... 117

Table 122. TMUX_B 3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W) ........................... 117

Table 123. TMUX_B 3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W) ................................... .118

Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO) .............................................................................. 118

Table 125. TMUX_B2ECNT_17_16 an d TMUX_B2ECNT_15_0, Receive B2 Error Cou nt s (RO ) .... .. . .. .. ... .. .. . .. 11 9

Table 126. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO) ....................................................................119

Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO) ................... 120

Table 128. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO) ................................................................... 120

Table 129. TMUX_RPTR_INCCNT[1—3], Re ceive Poin ter Increment Count (RO ) ............................................ 121

Table 130. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO) ......................................... 121

Table 131. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W) ................................................. 121

Table 132. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO) ....................................................1 21

Table 133. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W) ..................................................................121

Table 134. TMUX_RJ1EXPECTED1_[1—32], Expecte d J1 Byt e Val u e for Port 1 (R/W) ................... .......... ...... 122

Table 135. TMUX_RJ1EXPECTED2_[1—32], Expecte d J1 Byt e Val u e for Port 2 (R/W) ................... .......... ...... 122

Table 136. TMUX_RJ1EXPECTED3_[1—32], Expecte d J1 Byt e Val u e for Port 3 (R/W) ................... .......... ...... 122

Table 137. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO) .......................................... 122

Table 138. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO) .......................................... 122

Table 139. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO) .......................................... 123

Table 140. TMUX_TJ1VALUE_1[1—32], J1 Byte Transmit In se rt for STS #1 (R/W) ................ ......... .......... ...... 123

Table 141. TMUX_TJ1VALUE_2[1—32], J1 Byte Transmit In se rt for STS #2 (R/W) ................ ......... .......... ...... 123

Table 142. TMUX_TJ1VALUE_3[1—32], J1 Byte Transmit In se rt for STS #3 (R/W) ................ ......... .......... ...... 123

Table 143. TMUX Register Map .......................................................................................................................... 124

Page 77

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

77Agere Systems Inc.

8 TMUX Registers

(continued)

8.1 TMUX Register Des criptions

This section provides a brief description of each register bit and its functionality. The abbreviations after each register indicate if the register is read only (RO), clear-on-read/clear-on- write (COR /C OW), or read/writ e ( R /W).

Table 77. TMUX_ID_R, TMUX Identification Register (RO)

Table 78. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)

Table 79. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W)

Address Bit Name Function Reset Default

0x40000 15:11 — Reserved. 0x0

10:8 TMUX_VERSION[2:0] Block Version Number. Block vers io n register w ill

change each time the device is changed.

0x0

7:0 TMUX_ID[7:0] Block ID Number. 0x04

Address Bit Name Function Reset Default

0x40002 15:8 — Reserved. 0x00

7 TMUX_B3SFCLEAR B3 Signal Fail Clear . Allo ws the signal f ail algorithm

to be forced into the normal state.

6 TMUX_B3SFSET B3 Signal Fail Set. Al lows the signal fail algorithm

to be forced into the failed state.

5 TMUX_B3SDCLEAR B3 Signal Degrade Clear. Allows the signal

degrade algorithm to be forced into the normal state.

4 TMUX_B3SDSET B3 Signal Degrade Set. Allows the signal degrade

algorithm to be forced into the degraded state.

3 TMUX_SFCLEAR Signal Fail Clear. Allows the signal fail algorithm to

be forced into the normal state.

2 TMUX_SFSET Signal Fail Set. All ows the signal f ail algorithm to be

forced into the failed state.

1 TMUX_SDCLEAR Signal Degrade Clear. Allows the signal degrade

algorithm to be forced into the normal state.

0 TMUX_SDSET Signal Degrade Set. Allows the signal degrade

algorithm to be forced into the degraded state.

Address Bit Name Function Reset Default

0x40003 15:1 — Reserved. 0x000

0 TMUX_STS1MODE STS-1 Mode Control Bit. A 1 indicates that the

received and transmitted high-speed data is STS-1 data operating at 52 MHz. A 0 indicates that the received and transmitted high-speed data operates at 155 MHz.

Page 78

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

78 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 80. TMUX_TX_DLT, Delta/Event (COR/COW)

Table 81. TMUX_RPS_DLT, Delta/Event (COR/COW)

Address Bit Name Function Reset

Default

0x40004 15:7 — Reserved. 0x000

6:4 TMUX_TLSPARE[3:1] Transmit Low-speed Parity Error Event (Input Port Num-

ber). This event bit indicates a byte transfer parity error was detected on the respective STS-1/AU-3 input. The mask bits are TMUX_TLSPARM[3:1] (Table 84).

3TMUX_TPOAC_PETransmit Path Overhead Access Channel (TPOAC) Par-

ity Error Event. This event bit indicates a parity error was detected on the incoming transmit path overhead access channel. The mask bit is TMUX_TPOAC_PM (Table 84).

2TMUX_TTOAC_PETran sm it Transport Overhead Access Channel (TTOAC)

Parity Error Event. This event bit indicates a parity error was detected on the incoming transmit transport overhead access channel. The mask bit is TMUX_TTOAC_PM (Table 84).

1TMUX_THSILOFDTransm it High-speed Input Loss of Frame Delta. This

delta bit in dicates a change of state for the transmit loss of frame bit TMUX_THSILOF (Table 89). The mask bit is TMUX_THSILOFM (Table 84).

0 TMUX_THSILOCD Transmit High-speed Input Loss of Clock Delta. This

delta bit in dicates a change of state for the transmit loss of high-speed clock bit TMUX_THSILOC (Table 89). The mask bit is TMUX_THSILOCM (Table 84).

Address Bit Name Function Reset

Default

0x40005 15:6 — Reserved. 0x000

5TMUX_RPSLOFDReceive Protection High-speed Loss of Frame Delta. This

delta bit indicates a change in state of TMUX_RPSLOF (Table 90). The mask bit is TMUX_RPSLOF M (Table 85).

4 TMUX_RPSOOFD Receive Protection High-speed Out of Frame Delta. This

delta bit indicates a change in state of TMUX_RPSOOF (Table 90). The mask bit is TMUX_RPSOOF M (Table 85).

3TMUX_RPSILOCDReceive Protection High-speed Loss of Input Clock

Delta. This delta bit indicates a change in state of the TMUX_RPSILOC (Table 90) state bit. The mask bit is TMUX_RPSILOCM (Table 85).

2TMUX_RPSB2EReceive Protection High-speed B2 Error Event. This event

bit indicates a B2 error was detected in the receive protection input. The mask bit is TMUX_RPSB2M (Table 85).

1 TMUX_RPSLREIE Receive Protection High-speed Line REI Event. This

event bit indicates a line REI error was detected in the receive protection input. The mask bit is TMUX_RPSLREIM (Table 85).

0 — Reserved. 0

Page 79

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

79Agere Systems Inc.

8 TMUX Registers

(continued)

Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW)

Address Bit Name Function Reset Default

0x40006 15 — Reserved. 0

14 TMUX_RS1BABE Receive S1 Babble Event. This event bit indicates an

inconsistent S1 value is being received. The event is triggered if TMUX_CNTDS1FRAME[3:0] (Table 98) co nsecutive frames pass without a validated message occurring. The mask bit is TMUX_RS1BABM (Table 86).

13 TMUX_RS1MOND Receive S1 Monitor Delta. This delta bit indicates a

change of state for TMUX_RS1MON[7:0] (Table 103). A new S1 value is detected after TMUX_CNTDS1[3:0] (Table 98) consecutive occurrences of a consistent new value in the S1 byte. The mask bit is TMUX_RS1MONM.

12 TMUX_RLRDIMOND Receive Line RDI Monitor Delta. This delta bit indi-

cates a change in state for TMUX_RLRDIMON (Table 91) when the pattern 110 is detected/not detected TMUX_CNTDK2[3:0] (Table 98) cons ec uti v e ti mes in th e incoming STS-3/S TM-1 frame. The mask bit is TMUX_RLRDIMONM (Table 86).

11 TMUX_RLAISMOND Receive Line AIS Monitor Delta. This de lt a bit i ndi -

cates a change in state for TMUX_RLAISMON (Table 91) when the pattern 111 is detected/not detected TMUX_CNTDK2[3:0] consecutive times in the incoming STS-3/STM-1 frame. The mask bit is TMUX_RLAISMONM (Table 86).

10 TMUX_RK2MOND Receive K2 Monitor Delta. This delta bit indicates a

change in state for TMUX_K2MON[2:0] (Table 102 on

page 100). A new K2 value is detected after

TMUX_CNTDK2[3:0] consecutive occurrences of a consistent new value in the three least significant bits of the incoming K2 byte. Note that this de lta bit may be coincident with TMUX_RLRDIMOND and TMUX_RLAISMOND. The mask bit is TMUX_RK2MONM (Table 86).

9 TMUX_RAPSBABE Receive APS Babble Event. This event bit indicates

when an inconsistent APS value has been detected TMUX_CNTDK1K2[3:0] (Table 98) times in the incoming TMUX_CNTDK1K2FRAME[3:0] (Table 98) consecutive frames. The mask bit is TMUX_RAPSBABM (Table 86

on page88 ).

8 TMUX_RAPSMOND Receive APS Monitor Delta. This delta bit indicates a

change in state in the received APS value TMUX_RAPSMON[12:0] (Table 102) when a new consistent value is detected TMUX_CNTDK1K2[3:0] times in the K1 and K2[7:3] bits. The mask bit is TMUX_RAPSMONM (Table 86).

Page 80

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

80 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset Default

0x40006 7 TMUX_RF1MOND Receive F1 Monitor Delta. This delta bit i n di c ates a

change in state of TMUX_RF1MON0[7:0] and TMUX_R F1MON1[7 :0] (Table 101) when a consistent new value is detected in the incoming F1 byte for TMUX_CNTDF1[3:0] (Table 98) continuous frames. The current value is stored in TMUX_RF1MON0[7:0] and the previous value is stored in TMUX_RF1MO N0[7:0]. The mask bit is TMUX_RF1MONM (Table 86).

6TMUX_RTIMSDReceive Section Trace Identifier Mismatch Delta. This

delta bit indicates a change in state in the received 16byte J0 sequence of bytes if the J0 mode is programmed to receive a 16-byte sequence. The mask bit is TMUX_RTIMSM (Table 86).

5 TMUX_RHSSFD Receive High-speed Signal Fail BER Algorithm Delta.

This delta bit indicates a change of state for the signal fail BER algorithm s tate bit TMUX_RHSSF (Table 91). The mask bit for this delta bit is TMUX_RHSSFM (Table 86).

4 TMUX_RHSSDD Receive High-speed Signal Degrade BER Algorithm

Delta. This delta bit indicates a change of state for the signal degrade BER algorithm state bit TMUX_RHSSD (Table 91). The mask bit is TMUX _RHSS DM (Table 86).

3 TMUX_RHSLOSD Receive High-speed Loss of Signal Delta. This delta

bit indicates a change i n state of either TM UX_RHSLOS (Table 91) or TMUX_RHSLOS EXT I (Table 91). TMUX_RHSLOSEXTI is an external input from a device pin. TMUX_RHSLOS is an interna lly generated state bit based on monitoring for a consecutive 0/1s pattern in the data input. The mask bit is TMUX_RHSLOSM (Table 86).

2 TMUX_RHSLOFD Receive High-speed Loss of Frame Delta. This delta

bit indicates a change in state of TMUX_RH SLOF (Table 91). The mask bit is TMUX_RHSLOFM (Table 86).

1 TMUX _RHSOO FD Receive High-speed Out of Frame Delta. T his delta bi t

indicates a change in state of TMUX_RHSOOF (Table 91). The mask bit is TMUX_RHSOOFM (Table 86).

0 TMUX _RHSILOCD Receive High-speed Loss of Input Clock Delta. This

delta bit indicates a change in state of the TMUX_RHSILOC (Table 91) state bit. The mask bit is TMUX_RHSILOCM (Table 86).

Page 81

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

81Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW)

Address Bit Name Function Reset

Default

0x40007 15 TMUX_RSFB3D1 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSFB31 (Table 92) at the path level for port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RSFB3M1 (Table 87).

14 TMUX_RSDB3D1 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSDB31 (Table 92) at the path level for port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The m as k bit is TMUX_RSDB3M1 (Table 87).

13 TMUX_RUNEQPE1 Receive Path Unequipped Event. T his event bit indicates

that the current value of the received C2 (signal label) byte, TMUX_C2MON1[7:0] (Table 104), has a value 0x00, indicat- ing unequipped payload on port 1. Only p ort 1 information is valid in AU-4 mode an d in STS-1 mode. The mask bit is TMUX_RUNEQPM1 (Table 87).

12 TMUX_RPLMPE1 Receive Path Payload Label Mismatch Event. This event

bit indicat es that the current value of the received C2 (signal label) byte, TMUX_C2MON1[7:0], differs from the expected C2 value, TMUX_C2EXP1[7:0] (Table 100) for port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RPLMPM1 (Table 87).

11 TMUX_RN1MOND1 Receive N1 Monitor Delta. This delta bit indicates a change

in state in TMUX_N1MON1[7:0] (Table 104). The N 1 c urrent value is updated when a consecutive and consistent value is detected in the incoming N1 byte for TMUX_CNTDN1[3:0] (Table 99) frames on port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RN1MONM1 (Table 87).

10 TMUX_RK3MOND1 Receive K3 Monitor Delta. This delta bit indicates a change

in state in TMUX_K3MON1[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming K3 byte for TMUX_CNTDK3[3:0] (Table 99) frames on port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RK3MONM1 (Table 87).

9 TMUX_RF3MOND1 Receive F3 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F3MON01[7:0] (Table 104), whi ch is updated when a consecutive and con- sistent value is detected in the incoming F3 byte for TMUX_CNTDF3[3:0] (Table 99) frames on port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF3MONM1 (Table 87).

Page 82

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

82 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40007 8 TMUX_RF2MOND1 Receive F2 (Path User Byte) Monitor Delta. This delta b it

indicates a change in state in TMUX_F2MON01[7:0] (Table 104), which is updated when a con secutive and consistent value is detected in the incoming F2 byte for TMUX_CNTDF2[3:0] (Table 99) frames on port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF2MONM1 (Table 87).

7 TMUX_RRDIPD1 Receive Path RDI (Remote Defect Indication) Monitor

Delta. This delta bit indicates a change in state in TMUX_RDIPMON1[2:0] (Table 104) that occurs when a con- secutive and consistent new value is detected in the incoming G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames on port 1. The device monitors either G1 bit 3 or G1[3:1] depending on TMUX_REPRDI_MODE ( Table 95). Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RRDIPM1 (Table 87).

6 TMUX_RC2MOND1 Receive C2 (Signal Label) Monitor Delta. This de lt a bit

indicates a change in state in TMUX_C2MON1[7:0] (Table 104), which is updated when a con secutive and consistent value is detected in the incoming C2 byte for TMUX_CNTDC2[3:0] (Table 99) frames on po rt 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RC2MONM1 (Table 87).

5 TMUX_RTIMPD1 Recei ve Path Trace Identifier Mismatch Delta. This delta

bit indicates a change in state in the received 16-byte J1 sequence on port 1 if the J1 mode is programmed to receive a 16-byte sequence. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RTIMPM1 (Table 87).

4 T MUX_RNDFE 1 Receive New Data Flag Event. This event bit indicates that

the incoming pointer has the new data flag enabled, causing a jump in the current pointer location for port 1. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RNDFM1 (Table 87).

3 TMUX_RDECE1 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indi cati on wa s received on port 1. Only port 1 information is valid in AU-4 mode and in S TS-1 mode. The mask bit is TMUX_RDECM1 (Table 87).

2 TMUX_RINCE1 Receive Pointer Increment Event. This event bit indicates

that a valid incoming pointer increment indication was received on port 1. Only port 1 information is valid in AU-4 mode and in S TS-1 mode. The mask bit is TMUX_RINCM1 (Table 87).

Page 83

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

83Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x4007 1 TMUX_RPAISD1 Receive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS1 (Table 92) state bit, which designates that the port 1 pointer interpreter is in the alarm indication signal state. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RPAISM1 (Table 87).

0 T MUX_RLOPD1 Recei ve Loss of Pointer Delta. This delta bit indicates a

change in state of the TMUX_RLOP1 (Table 92) state bit, which designates that the port 1 pointer interpreter is in the loss of pointer state. Only port 1 information is valid in AU-4 mode. The mask bit is TMUX_RLOPM1 (Table 87).

0x40008 15 TMUX_RSFB3D2 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSFB32 (Table 92) at the path level for port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RSFB3M2 (Table 87).

14 TMUX_RSDB3D2 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER algorithm state bit TMUX_RSDB32 (Table 92) at the path level for port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The m as k bit is TMUX_RHSSDB3M2.

13 TMUX_RUNEQPD2 Receive Path Unequipped Delta. This delt a bit i ndi cate s

that the current value of the received C2 (signal label) byte, TMUX_C2MON2[7:0] (Table 104), has a value 0x00, indicat- ing unequipped payload for port 2. Only port 1 information is valid in AU-4 mode an d in STS-1 mode.Th e mask bit is TMUX_RUNEQPM2 (Table 87).

12 TMUX_RPLMPD2 Receive Path Payload Label Mismatch Delta. This event

bit indicates that the current value of the received C2 (signal label) byte, TMUX_C2MON2[7:0], differs from the expected C2 value, TMUX_C2EXP2[7:0] (Table 100) for port 2. Only port 1 information is valid in AU-4 mode and in ST S -1 mode.The mask bit is TMUX_RPLMPM2 (Table 87).

11 TMUX_RN1MOND2 Receive N1 Monitor Delta. This delta bit indicates a change

in state in TMUX_N1MON2[7:0] (Table 104). The N1 current value is updated when a consecutive and consistent value is detected in the incoming N1 byte for TMUX_CNTDN1[3:0] (Table 99) frames on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RN1MONM2 (Table 87).

10 TMUX_RK3MOND2 Receive K3 Monitor Delta. This delta bit indicates a change

in state in TMUX_K3MON2[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming K3 byte for TMUX_CNTDK3[3:0] (Table 99) frames on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RK3MONM2 (Table 87).

Page 84

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

84 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Address Bit Name Functi on Reset

Default

0x40008 9 TMUX_RF3MOND2 Receive F3 (Path User Byte) Monitor Delta. This delta bit indi-

cates a change in state in TM UX_F3MON02[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming F3 byte for TMUX_CNTDF3[3:0] (Table 99) frames on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF3 MONM2 ( Table 87).

8 TMUX_RF2MO ND2 Receive F2 (Path User Byte) Monitor Delta. This delta bit indi-

cates a change in state in TM UX_F2MON02[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming F2 byte for TMUX_CNTDF2[3:0] (Table 99) frames on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF2 MONM2 ( Table 87).

7 TMUX_RRDIPD2 Receive Path RDI (Remote Defect Indication) Monitor Delta.

This delta bit indicates a change in state in TMUX_RDIPMON2[2:0] (Table 104) which occurs when a con- secutive and consistent new value is detected in the incoming G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames on por t 2. The device m onitors either G1 bit 3 or G1[3:1] depending on TMUX_REPRDI_MODE (Table 95). Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RRDIPM2 (Table 87).

6 TMUX_RC2MOND2 Receive C2 (Signal Label) Monitor Delta. This delta b it indi-

cates a change in state in TMUX_C2MON2[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the i ncoming C2 byte fo r TMUX_CNTDC2[3:0 ] (Table 99) frames on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RC2MONM2 (Table 87).

5 TMUX_RTIMPD2 Receive Path Trace Identifier Mismatch Delta. T h is delta b it

indicates a change in state in the received 16-byte J1 sequence for port 2 if the J1 mode is programmed to receive a 16-byte sequence. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RTIMPM2 (Table 87).

4 TMUX_RNDFE2 Receive New Data Flag Event. This event bit indicates that the

incoming pointer has the new data flag enabled for port 2, causing a jump in the current pointer location. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RNDFM2 (Table 87).

3 TMUX_RDECE2 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indication was received on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RDECM2 (Table 87). How- ever, increment and decrement event indication should be ignored during loss-of-pointer (LOP) condition.

Page 85

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

85Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Address Bit Name F un ction Reset

Default

0x40008 2 TMUX_RINCE2 Receive Pointer Increment Event. This event bit indicates

that a valid incoming pointer increment indication was received on port 2. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RINCM2 (Table 87). However, increment and decrement event indic a- tion should be ignored during loss-of-pointer (LOP) condition.

1 TMUX_RPAISD2 Receive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS2 (Table 92) state bit, which designates that the port 2 pointer interpreter is in the alarm indication signal state. Only port 1 information is valid in AU-4 mode an d in STS- 1 mode. The ma sk bit is TMUX_RPAISM2 (Table 87).

0 TMUX_RLOPD2 Receive Loss of Pointer Delta. This delta bit indicates a

change in state of the TMUX_RLOP2 (Table 92) state bit, which designates that the port 2 pointer interpreter i s in the loss of pointer state. Only port 1 information is valid in AU-4 mode. The mask bit is TMUX_RLO PM2 (Table 87).

0x40009 15 TMUX_RSFB3D3 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of s t at e for the signal fail BER algorithm state bit TMUX_RSFB32 (Table 92) at the path level f or port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RSFB3M3 (Table 87).

14 TMUX_RSDB3D3 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of sta te for the signal fail BER algorithm state bit TMUX_RSDB32 (Table 92) at the path level for port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The m as k bit is TMUX_RSDB3M3 (Table 87).

13 TMUX_RUNEQPE3 Receive Path Unequipped Event. This event bit indicates

that the current value of the received C2 (signal label) byte, TMUX_C2MON3[7:0] (Table 104), has a value 0x00, indicat- ing unequipped payload for p ort 3. Only port 1 information is valid in AU-4 mode and in STS -1 mode. The mask bit is TMUX_RUNEQPM3 (Table 87).

12 TMUX_RPLMPE3 Receive Path Payload Label Mismatch Event. This event

bit indicates that the current value of the received C2 (signal label) byte, TMUX_C2MON3[7:0], differs from the expected C2 value, TMUX_C2EXP3[7:0] (Table 100) for port 3. Only port 1 information is valid in AU-4 mode and in STS -1 mode. The mask bit is TMUX_RPLMPM3 (Table 87).

Page 86

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

86 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40009 11 TMUX_RN1MOND3 Receive N1 Monitor Delta. This delta bit indicates a change in

state in TMUX_N1MON3[7:0] (Table 104). The N1 current value is updated when a consecutive and consistent value is detected in the incoming N1 byte for TMUX_CNTDN1[3:0] (Table 99) frames on port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RN1MONM3 (Table 87).

10 TM UX_ RK3 MOND3 Receive K3 Monitor Delta. This delta bit indicates a change in

state in TMUX_K3MON3[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming K3 byte for TMUX_CNTDK3[3:0] (Table 99) frames on port 2. Only por t 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RK3MONM3 (Table 87).

9TMUX_RF3MOND3Receive F3 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F3MON03[7:0] (Table 104), wh ich is updated when a consecutive and consis- tent value is detected in the incoming F3 byte for TMUX_CNTDF3[3:0] (Table 99) frames on port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF3MONM3 (Table 87).

8TMUX_RF2MOND3Receive F2 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F2MON03[7:0] (Table 104), wh ich is updated when a consecutive and consis- tent value is detected in the incoming F2 byte for TMUX_CNTDF2[3:0] (Table 99) frames on port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RF2MONM3 (Table 87).

7 TMUX_RDIPD3 Receive Path RDI (Remote Defect Indication) Monitor

Delta. This delta bit indicates a change in state in TMUX_RDIPMON3[2:0] (Table 104) which occurs when a consecutive and consistent new value is detected in the incoming G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames on port 3. The devi ce monitors either G1 bit 3 or G1[3:1] depending on TMUX_REPRDI_MODE (Table 95). Only por t 1 i nformation is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RRDIPM3 (Table 87).

6 TMUX_RC2MOND3 Receive C2 (Signal Label) Monitor Delta. Thi s delta bit indi-

cates a change in state in TMUX_C2MON3[7:0] (Table 104), which is updated when a consecutive and consistent value is detected in the incoming C2 byte for TMUX_CNTDC2[3:0] (Table 99) frames on port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RC2MONM3 (Table 87).

5 TMUX_RTIMPD3 Receive Path Trace Identifier Mismatch Delta. This delta bit

indicates a change in state in the received 16-byte J1 sequence for por t 3 if the J1 mode is programmed to receiv e a 16-byte sequence. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RTIMPM3 (Table 87).

Page 87

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

87Agere Systems Inc.

8 TMUX Registers

(continued)

Table 8 3. TMUX_RP OH[1—3]_DLT, Del ta/Eve nt (COR/COW) (continued)

Note: In Table 84, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Address Bit Name Function Reset

Default

0x40009 4 TMUX_RNDFE3 Receive New Data Flag Event. This event bit indicates that the

incoming pointer has the new data flag enabled, causing a jump in the current pointer location for port 3. Only por t 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RNDFM3 (Table 87).

3 TMUX_RDECE3 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indication was received on port 3. Only p ort 1 infor mation is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RDECM3 (Table 87).

2 TMUX_RINCE3 Receive Pointer Increment Event. This event bit indicates that

a valid incoming pointer increment indication was received on port 3. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RINCM3 (Table 87).

1 TMUX_RPAISD3 Receive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS3 (Table 92) state bit, which designates that the port 3 pointer interpreter is in the alar m indication signal state. Only port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RPAISM3 (Table 87).

0 TMUX_RLOPD3 Receive Loss of Pointer Delta. This del ta bit indicates a

change in state of the TMUX_RLOP3 (Table 92) state bit, which designates that the port 3 pointer interpreter is in the loss of pointer state. Only port 1 information is valid in AU-4 mode. The mask bit is TMUX_RLOPM3 (Table 87).

Address Bit Name Function Reset

Default

0x4000A 15:7 — Reserved. 0x000

6:4 TMUX_TLSPARM[3:1] Transmit Low-speed Parity Error Mask (Input Port Num-

ber). See Table 80 for description.

3TMUX_TPOAC_PMTransmit Path Overhead Access Channel (TPOAC) Par-

ity Error Mask. See Table 80 for description.

2TMUX_TTOAC_PMT ransmit T ransport Overhead Access Channel (TTOA C)

Parity Error Mask. See Table 80 for description.

1 TMUX_THSILOFM Transmit High-speed Input Loss of Fram e Mask. See

Table 80 for description.

0TMUX_THSILOCMTransmit High-speed Input Loss of Clock Mask. See

Table 80 for description.

Page 88

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

88 Agere Systems Inc.

8 TMUX Registers

(continued)

Note: In Table 85, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Note: In Table 86, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Address Bit Name Function Reset

Default

0x4000B 15:6 — Reserved. 0x000

5 TMUX_RPSLOFM Receive Protection High-speed Loss of Frame Mask. See

Table 81 for description.

4 TMUX_RPSOOFM Receive Protection High-speed Out of Frame M ask. See

Table 81 for description.

3 TMUX_RPSILOCM Receive Protection High-speed Loss of Input Clock Mask.

See Table 81 for description.

2 TMUX_RPSB2M Receive Protection High-speed B2 Error Mask. See

Table 81 for description.

1 TMUX_RPSLREIM Receive Protection High-speed Line REI Mask. See

Table 81 for description.

Address Bit Name Function Reset

Default

0x4000C 15 — Reserved. 0

14 TMUX_RS1BABM Receive S1 Babble Mask. See Table 82 for description. 1 13 TMUX_RS1MONM Receive S1 Monitor Mask. See Table 82 for description. 1 12 TM UX_RLRDIMONM Receive Line RDI Monitor Mask. See Table 82 for descrip-

tion.

11 TMUX_RLAISMONM Receive Line AIS Monitor Mask. See Table 82 for descrip-

tion.

10 TMUX_RK2MONM Receive K2 Monitor Mask. See Table 82 for description. 1

9 TMUX_RAPSBABM Receive APS Babble Mask. See Table 82 for description. 1 8 TMUX_RAPSMONM Recei ve APS Monit o r Mask . See Table 82 for description. 1 7TMUX_RF1MONMReceive F1 Monitor Mask. See Table 82 for description. 1 6 TMUX_RTIMSM Receive Section T race Identifier Mismatch Mask. See

Table 82 for description.

5 TMUX_RHSSFM Receive High-speed Signal Fail BER Algorithm Mask.

See Table 82 for description.

4 TMUX_RHSSDM Receive High-speed Signal Degrade BER Algorithm

Mask. See Table 82 for description.

3 TMUX_RHSLOSM Receiv e High-speed Loss of Signal Mask. See Table 82

for description.

2 T M UX_ RHS LOF M Receive High-speed Loss of Frame Mask. See Table 82

for description.

1 TMUX_RHSOOFM Receive High-speed Out of Frame Mask. See Table 82 for

description.

0 TM UX_RHSILOCM Receive High-speed Loss of Input Clock Mask. See

Table 82 for description.

Page 89

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

89Agere Systems Inc.

8 TMUX Registers

(continued)

Note: In Table 87, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 8 7 . TMUX_RPOH[ 1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Address Bit Name Function Reset

Default

0x4000D 15 TMUX_RSFB3M1 Receive Path Signal Fail BER Algorithm Mask. See Table 83

for description.

14 TMUX_RSDB3M1 Rece ive Path Signal Degrade BER Algorithm Mask. See

Table 83 for description.

13 TMUX_RUNEQPM1 Receive Path Unequipped Mask. See Table 83 for description. 1 12 TMUX_RPLMPM 1 Receive Path Payload Label Mismatch Mask. See Table 83

for description.

11 TMUX_RN1MONM1 Receive N1 Monitor Mask. See Table 83 for description. 1 10 TMUX_RK3MONM1 Receive K3 Monitor Mask. S ee Table 83 for description. 1

9 TMUX_RF3MONM1 Receive F3 (Path User Byte) Monitor Mask. See Table 83 for

description.

8 TMUX_RF2MONM1 Receive F2 (Path User Byte) Monitor Mask. See Table 83 for

description.

7 TMUX_RRDIPM1 Receive Path RDI (Remote Defect Indication) Monitor Mask.

See Table 83 for description.

6 TMUX_RC2MONM1 Rece ive C2 (Signal Label) Monitor Mask. See Table 83 for

description.

5 TMUX_RTIMPM1 Receive Path Trace Identifier Mismatch Mask. See Table 83

for description.

4 TMUX_RNDFM1 Receive New Data Flag Mask. See Table 83 for description. 1 3 TMUX_RDECM1 Receive Pointer Decrement Mask. See Table 83 for descrip-

tion.

2 TMUX_RINCM1 Receive Pointer Increment Mask. See Table 83 for descrip-

tion.

1 TMUX_RPAISM1 Receive Path AIS Mask. See Table 83 for description. 1 0 TMUX_RLOPM1 Receive Loss of Pointer Mask. See Table 83 for description. 1

0x4000E 15 TMUX_RSFB3 M2 Receive Path Signal Fail BER Algorithm Mask. See Table 83

for description.

14 TMUX_RSDB3M2 Rece ive Path Signal Degrade BER Algorithm Mask. See

Table 83 for description.

13 TMUX_RUNEQPM2 Receive Path Unequipped Mask. See Table 83 for description. 1 12 TMUX_RPLMPM 2 Receive Path Payload Label Mismatch Mask. See Table 83

for description.

11 TMUX_RN1MONM2 Receive N1 Monitor Mask. See Table 83 for description. 1 10 TMUX_RK3MONM2 Receive K3 Monitor Mask. S ee Table 83 for description. 1

9 TMUX_RF3MONM2 Receive F3 (Path User Byte) Monitor Mask. See Table 83 for

description.

8 TMUX_RF2MONM2 Receive F2 (Path User Byte) Monitor Mask. See Table 83 for

description.

7 TMUX_RRDIPM2 Receive Path RDI (Remote Defect Indication) Monitor Mask.

See Table 83 for description.

Page 90

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

90 Agere Systems Inc.

8 TMUX Registers

(continued)

Note: In Table 87, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) (c onti nued )

Address Bit Name Function Reset

Default

0x4000E 6 TMUX_RC2MONM2 Receive C2 (S ignal Label) Monitor Mask. See Table 83 for

description.

5 T MUX_RTIMPM2 Receive Path Trace Identifier Mismatch Mask. S ee

Table 83 for description.

4 TMUX_RNDFM2 Receive New Data Flag Mask. See Table 83 for description. 1 3 TMUX_RDECM2 Receive Pointer Decrement Mask. See Table 83 for

description.

2 T M UX_RINCM2 Receive Pointer Incremen t Mask. See Table 83 for descrip-

tion.

1 TMUX_RPAISM2 Receive Path AIS Mask. See Table 83 for description. 1 0 TMUX_RLOPM2 Receive Loss of Pointer Mask. See Table 83 for description. 1

0x4000F 15 TMUX_RSFB3M3 Receive Path Signal Fail BER Algorithm Mask. See

Table 83 for description.

14 TMUX_RSDB3M3 Receive Path Signal Degrade BER Algorithm Mask. See

Table 83 for description.

13 TMUX_RUNEQPM3 Receive Path Unequipped Mask. See Table 83 for descrip-

tion.

12 TMUX_RPLMPM3 Receive Path Payload Label Mismatch Mask. See Table 83

for description.

11 TMUX_RN1MONM3 Receive N1 Mon ito r Mask. See Table 83 for description. 1 10 TMUX_RK3MONM3 Receive K3 Monitor Mask. See Table 83 for description. 1

9 TMUX_RF3MONM3 Receive F3 (Path User Byte) Monitor Mask. See Ta ble 83

for description.

8 TMUX_RF2MONM3 Receive F2 (Path User Byte) Monitor Mask. See Ta ble 83

for description.

7 TMUX_RRDIPM3 Rec eive Path RDI (Remo te Defect Indication) Monitor

Mask. See Table 83 for description.

6 TMUX_RC2MONM3 Receive C2 (S ignal Label) Monitor Mask. See Table 83 for

description.

5 T MUX_RTIMPM3 Receive Path Trace Identifier Mismatch Mask. S ee

Table 83 for description.

4 TMUX_RNDFM3 Receive New Data Flag Mask. See Table 83 for description. 1 3 TMUX_RDECM3 Receive Pointer Decrement Mask. See Table 83 for

description.

2 T M UX_RINCM3 Receive Pointer Incremen t Mask. See Table 83 for descrip-

tion.

1 TMUX_RPAISM3 Receive Path AIS Mask. See Table 83 for description. 1 0 TMUX_RLOPM3 Receive Loss of Pointer Mask. See Table 83 for description. 1

Page 91

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

91Agere Systems Inc.

8 TMUX Registers

(continued)

Note: In Table 88, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

T able 88. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Note: When state bits are set in Table 89, the corresponding function has occurred.

Table 89. TMUX_TX_STATE, State Parameters (RO)

Note: When state bits are set in Table 90, the corresponding function has occurred.

Table 90. TMUX_RPS_STATE, State and Value Parameters (RO)

Address Bit Nam e Function Reset

Default

0x40011 15:8 — Reserv ed. 0x000

7 TMUX_RHSSF_APSM R eceive High -s peed Signal Fail B ER Algorithm

APSINT Mask. See Table 82 for description.

6 TMUX_RHSSD_APSM Receive High-speed Signal Degrade BER Algo-

rithm APSINT Mask. See Table 82 for description.

5 T MUX_RAPSMON_APSM Receive APS Monitor APSINT Mask. See Table 83

for description.

4 TMUX_RLAISMON_APSM Receive Line AIS Monitor APSINT Mask. See

Table 82 for description.

3 TMUX_RHSLOS_APSM Receive High-speed Loss of Signal APSINT Mask.

See Table 82 for description.

2 T MUX_RHSLOF_APSM Receive High-speed Loss of Frame APSINT Mask.

See Table 82 for description.

1 TMUX_RHSOOF_APSM Rece ive High-spe ed Out of Fram e A PSINT Mask.

See Table 82 for description.

0 TMUX_RHSILOC_APSM Receive Hi gh-speed L oss o f Inpu t Clock APSINT

Mask. See Table 82 for description.

Address Bit Name Function Reset

Default

0x40012 15:2 — Reserved. 0x000

1TMUX_THSILOFTr ansmi t High-speed Input Loss of Frame State. See

Table 80 for description.

0TMUX_THSILOCTransmit High-speed Input Loss of Clock State. See

Table 80 for description.

Address Bit Name Function Reset

Default

0x40013 15:6 — Reserved. 0x000

5 TMUX_RPSLOF Receive Protection High-speed Loss of Frame State. See

Table 81 for description.

4TMUX_RPSOOFReceive Protection High-speed Out of Frame State. See

Table 81 for description.

3 TMUX_RPSILOC Receive Protection High-speed Loss of Input Clock State.

See Table 81 for description.

2:0 — Reserved. 000

Page 92

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

92 Agere Systems Inc.

8 TMUX Registers

(continued)

Note: When state bits are set in Table 91, the corresponding function has occurred. Table 91. TMUX_RHS_STATE, State and Value Parameters (RO)

Note: When state bits are set in Table 92, the corresponding function has occurred.

Address Bit Name Function Reset

Default

0x40014 15:13 — Reserved. 000

12 TMUX_RLRDIMON Re ceiv e Line RDI Mon i tor State. See Table 82 for

description.

11 TMUX _RLAISMON Receive Line AIS M onit o r Sta te. See Table 82 for

description.

10:8 — Reserved. 000

7 TMUX_RHSLOSEXTI Reflects LOSEXT Pin (AE5) Input. — 6TMUX_RTIMSReflects Section-Level Trace Identifier Mismatch State. — 5 TMUX_RHSSF Rec eive High-speed Signal Fail B ER Algorithm S t at e.

See Table 82 for description.

4 TMUX_RHSSD Receive High-speed Signal Degrade BER Algorithm

State. See Table 82 for description.

3 TMUX_RHSLOS Receive High-speed Loss of Signal State. See Table 82

for description.

2 TMUX_RHSLOF Receive High-speed Loss of Frame State. See Table 82

for description.

1 TMUX_RHSOOF Receive High-speed Out of Frame State. See Table 82

for description.

0 TMUX_RHSILOC Receive High-speed Loss of Input Clock State. See

Table 82 for description.

Table 9 2 . TMUX_RPOH[ 1—3]_STATE, State and Value Parameters (RO )

Address Bit Name Function Reset

Default

0x40015 15 TMUX_RSFB31 Receive Path Signal Fail BER Algorithm State.

See Table 83 for description.

14 TMUX_RSDB31 Receive Path Signal Degrade BER Algorithm

State. See Table 83 for description.

13 TMUX_RUNEQP1 Receive Path Unequipped State. See Table 83

for description.

12 TMUX_RPLMP1 Receive Path Payload Label Mismatch State.

See Table 83 for description.

11:6 — Reserved. 0x00

5 T MUX_RTIMP1 Receive Path Trace Identifier Mismatch State.

See Table 83 for description.

4:2 — Reserved. 000

1 TMUX_RPAIS1 Receive Path AIS State. See Table 83 for descrip-

tion.

0TMUX_RLOP1Receive Loss of Pointer State. See Table 83 for

description.

Page 93

Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

8 TMUX Registers

(continued)

93Agere Systems Inc.

Address Bit Name Function Reset

Default

0x40016 15 TMUX_RSFB32 Receive Path Signal Fail BER Algorithm State.

See Table 83 for description.

14 TMUX_RSDB32 Receive Path Signal Degrade BER A lg or ithm

State. See Table 83 for description.

13 TMUX_RUNEQP2 Receive Path Unequipped State. See Table 83

for description.

12 TMUX_RPLMP2 Receive Path Payload Label Mismatch State.

See Table 83 for description.

11:6 — R eserved. 0x000

5 T MUX_RTIMP2 Receive Path Trace Identifier Mismatch State.

See Table 83 for description.

4 — Reserved. 0

3:2 TMUX _CONCAT _STATE2[1:0] C oncatenation Pointer State Machine State.

State bits indicate the state of the concatenation state machine (LOPC = 10, AISC = 01, CONC = 00) for port 2. These values only have meaning in the AU-4 mode with the TMUX_RCONCATMODE bit (Table 95) set to the concatenation mode (1).

1 TMUX_RPAIS2 Receive Path AIS State. See Table 83 for descrip-

tion.

0TMUX_RLOP2Receive Loss of Pointer State. See Table 83 for

description.

0x40017 15 TMUX_RSFB33 Receive Path Signal Fail BER Algorithm State.

See Table 83 for description.

14 TMUX_RSDB33 Receive Path Signal Degrade BER A lg or ithm

State. See Table 83 for description.

13 TMUX_RUNEQP3 Receive Path Unequipped State. See Table 83

for description.

12 TMUX_RPLMP3 Receive Path Payload Label Mismatch State.

See Table 83 for description.

11:6 — R eserved. 0x000

5 T MUX_RTIMP3 Receive Path Trace Identifier Mismatch State.

See Table 83 for description.

4 — Reserved. 0

3:2 TMUX _CONCAT _STATE3[1:0] C oncatenation Pointer State Machine State.

State bits indicate the state of the concatenation state machine (LOPC = 10, AISC = 01, CONC = 00) for port 3. These values only have meaning in the AU-4 mode and the TMUX_RCONCATMODE bit (Table 95) set to the concatenation mode (1).

1 TMUX_RPAIS3 Receive Path AIS State. See Table 83 for descrip-

tion.

0TMUX_RLOP3Receive Loss of Pointer State. See Table 83 for

description.

Table 92. TMUX_RPOH[1—3]_ STA TE, State and Value Parameters (RO) (continued)

Page 94

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

94 Agere Systems Inc.

8 TMUX Registers

(continued)

T able 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W)

Address Bit N ame Function Reset Default

0x40019 15:4 — Reserved. 0x000

3 TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity.

0 = active-low. 1 = active-high.

2 TMUX_RPSMUXSEL1 Receive Protection Switch Control. Control bit,

when s et to a logic 1, causes the receive protection switch data and clock inputs t o be s el e c ted; otherwise, the normal receive high-speed data input is selected.

1 TMUX_THS2RHSLB Transmit High-speed to Receive High-speed

Loopback Control. Control bit, when set to a logic 1, causes the transmit output STS-3/STM-1 (AU-4) signal to be looped back to the receive input; otherwise, the loopback is di sable d.

0 TMUX_RHSDSCR Receive High-speed Descramble Enable. Con-

trol bit, when set to a logic 1, causes the input STS-3/STM-1 (AU-4) signal to be descrambled; otherwise, the signal is not descrambled.

Table 94. TMUX_RLS_BITBLK_CTL, Receiv e Low-speed Control Parameters (R/W)

Address Bit Name Function Reset Default

0x4001A 15:9 — Reserved. 0x00

8:7 TMUX_RCV_S S_ EXP[1 :0] Expected Receive Pointer Size Bits Value.

Expected value of incoming pointer SS bits.

6 TMUX_RCV_SS_ENB Receive Size Bits Enable. Control bit, when set to

a logic 0, causes the received size bits to be ignored by the pointer interpreter; otherwise, the received size bits must equal the expected size bits or the received pointer value will be invalid.

5 — Reserved. 0 4 T MUX_BITBLKG1 Receive Bit/Block Error Count Control. Control

bit, when set to a logic 0, causes the receive error counter to count bit errors; otherwise, count block errors (a block equals one frame).

3 TMUX_BITBLKM1 Receive Bit/Block E rror Count Control. Control

bit, when set to a logic 0, causes the receive error counter to count bit errors; otherwise, count block errors (a block equals one frame).

2 TMUX_BITBLKB3 Receive Bit/Block Error Count Control. Control

bit, when set to a logic 0, causes the receive error counter to count bit errors; otherwise, count block errors (a block equals one frame).

1 TMUX_BITBLKB2 Receive Bit/Block Error Count Control. Control

bit, when set to a logic 0, causes the receive error counter to count bit errors; otherwise, count block errors (a block equals one frame).

0 TMUX_BITBLKB1 Receive Bit/Block Error Count Control. Control

bit, when set to a logic 0, causes the receive error counter to count bit errors; otherwise, count block errors (a block equals one frame).

Page 95

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

95Agere Systems Inc.

8 TMUX Registers

(continued)

Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001B 15:14 — Reserved. 00

13 TMUX_RPAIS_INS Receive Force Path AIS Insertion. Control bit, when

set to a logic 1, causes the receive low-speed signal to carry PAIS as well as asserting all AUTO_AIS[1—3] (pins AC6, AE6, and AD6) (Table 3) outputs.

12 TMUX_8ORMAJORITY Receive Control Bit for Pointer Justifications. Con-

trol bit, when set to a logic 1, causes the pointer interpreter to accept an increment or decrement only if 8 out of 10 bits are correct; otherwise, it will accept an increment or decrement based on maj ority vote only.

11 TMUX_SDB1B2SEL Receive Signal Degrade Algorithm Input Selection.

Control bit, when set to a logic 1, causes the B2 errors to contribute to the signal degrade calculation; otherwise, the B1 error count is used.

10 TMUX_SFB1B2SEL Receive Signal Fail Algorithm Input Selection. Con-

trol bit, when set to a logic, causes the B2 errors to contribute to the signal degrade calculation; otherwise, the B1 error count is used.

9:7 TMUX_J1MONMODE[2:0] Receive J1 Monitor Mode. Th ere are six m odes, as

defined in J1 monitor on page 377.

000

6:4 TMUX_J0MONMODE[2:0] Receive J0 Monitor Mode. Th ere are six m odes, as

defined in Section 17.5.5 J0 M onit or on page 370.

000

3 TMUX_S1MODE4 Receive S1 Monitor Mode. Control bit, when set to a

logic 1, causes the most significant nibble of the S1 byte to be monitored; otherwise, the entire S1 byte is monitored.

2 TMUX_RLSPAROEG Receive Low-speed Parity Odd or Even Generation.

Control bit, when set to a logic 1, forces the output parity bit to be even; otherw ise, the parity is odd.

1 TMUX_RCONCATMODE Receive Concatenation Mode. Control bit, when set to

a logic 1, causes the input pointer interpreter to operate in concatenation mode. This mode is most likely used in AU-4 mode; otherwise, three independent pointers are expected.

0 TMUX_REPRDI_MODE Receive Enhanced Path RDI Mode. Control bit, when

set to a logic 1, causes the receive path RDI monitor to monitor the enhanced (3-bit found in G1[3:1]) value of path RDI; otherwise, a 1-bit value (G1[3]) is monitored.

Page 96

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

96 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W)

Address Bit Nam e F un ction Reset

Default

0x4001C 15 TMUX_R_M1_BIT7 Receiv e M1 MSB Mode. Control bit, when set to a logic

1, causes the most s ign ificant bit in the M1 byte to be ignored for line REI accumulation; otherwise, the MSB is included.

14 TMUX_RSDB3_AISINH Receive B3 Signal Degrade AIS Inhibit. Control bit,

when set to a logic 1, inhibit the associated alarm from causing the assertion of t he AUTO_AIS output; otherwise, the associated failure causes assertion o f the corresponding AUTO_AIS output signal.

13 TMUX_RSFB3_AISINH Receive B3 Signal Fail AIS Inhibit. Control bit, when

set to a logic 1, inhibit the associated alarm from causing the assertion of the AUTO_AI S output ; oth erwise, the associated failure causes assertion of the corresponding AUTO_AIS output signal.

12:10 TMUX_RTIMP_AISINH[3:1] Receive Path Trace Identifier Mismatch AIS Inhibit

Bits. Control bits, when set to a logic 1, inhibit the associated alarm from causing the assertion of the AUTO_AIS output; otherwise, the associated failure causes assertion of the corresponding AUT O_AIS output signal.

9 TMUX_RUNEQP_AISINH Receive Path Unequip AIS Inhibit . Control bit, when

set to a logic 1, inhibit the associated alarm from causing the assertion of the AUTO_AI S output ; oth erwise, the associated failure causes assertion of the corresponding AUTO_AIS output signal.

8 TMUX_RPLMP_AISINH Receive Path Payload Label Mismatch AIS Inhibit .

Control bit, when set to a logic 1, inhibit the associated alarm from causing the assertion of the AUTO_AIS output; otherwise, the associated failure causes assertion of the corresponding AUTO_AIS output signal.

7 TMUX_RHSSD_AISINH Receive High-speed Signal Degrade AIS Inhibit. Con-

trol bits, when set to a l ogic 1, inhibit the associated alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3 outputs as well as the assertion of AUTO_AIS outputs.

6 TMUX_RHSSF_AISINH Receive High-speed Signal Fail AIS Inhibit. Control

bits, when set to a logic 1, inhibit the associated alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS -1 /AU-3 outputs as well as the assertion of AUTO_AIS outputs.

5 TMUX_RPAISLOP_AISINH Receive Path AIS or LOP AIS Inhibit . Control bits,

when set to a logic 1, inhibit the associated alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3 outputs as well as the assertion of AUTO_AIS outputs.

Page 97

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

97Agere Systems Inc.

8 TMUX Registers

(continued)

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) (continued)

Table 97. TMUX_LOSDETCNT, Receive Low-speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001C 4 TMUX_RLAISMON_A ISINH Receive Line AIS Monitor AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3 outputs as well as the assertion of AUTO_AIS outputs.

3TMUX_RLOF_AISINHReceive Loss-of-Frame AIS Inhibit. Control bit,

2 TMUX_ROOF_AISINH Receive High-speed Out-of-Frame AIS Inhibit.

Control bit, when set to a logic 1, inhibits the associated alarm from causing AIS generation; otherwise, the associated failure causes AIS generation on all STS-1/AU-3 outputs as well as the assertion of AUTO_AIS outputs.

1 TMUX_RHSLOS_AISINH Receive High-speed Loss-of-Signal AIS Inhibit.

0 TMUX_RILOC_AISINH Receive Input Loss-o f-C lock AIS Inhibit. Control

bit, when set to a logic 1, inhibits the associated alarm from causing the assertion of the AUTO_AIS outputs; otherwise, the associated failure causes assertion of all AUTO_AIS output signals.

Address Bit Name Function Reset

Default

0x4001D 15:14 — Reserved. 00

13:11 TMUX_FORCEC2DEF[2:0] Force TMUX_RPLMP Defects. These bits (one for

each STS-1 in an STS-3) will force TMUX_RPLMP defects on certain conditions as shown in Table 524 (STS Signal Label Defect Conditions).

000

10:0 TMUX_LOSDETCNT[10:0] Loss-of-Signal Detection Count. Control bits are the

number of consecutive all-0s/1s pattern detected to declare LOS state in the unscrambled STS-3/STM-1 (AU-4) input frame. A val ue of 0x02D equals 2.3 µs while a value of 0x798 equals 100 µs.

0x02D

Page 98

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

98 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 98. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001E 15:12 TMUX_CNTDK1K2FRAME [3:0] Continuous N-Times Detect for APS Frame

Bytes. Sets the number of CNTD frames within

which an inconsistent APS value is detected in the incoming STS-3/STM-1 (AU-4). This value is used in the APS babble algorithm. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0xC

11:8 TMUX_CNTDK1K 2[3 :0] Continuous N-Times Detect for APS (K1, K2[7:3])

Bytes. Sets the number of CNTD occurrences of a consistent APS value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF . Invalid values will be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDF1[3:0] Continuous N-Times Detect for F1 Byte. Sets the

number of CNTD occurrences of a consistent F 1 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNT DJ0[3 :0] Continuous N-Times Detect for J0 Byte. Sets the

number of CNTD occurrences of a consistent J0 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

0x4001F 15:14 — Reserved. 00

13:12 TMUX_CTDLOPCNT[1:0] Continuous N-Times Detect for Loss of Pointer

State. Control bits are the number of consecutive conditions for invalid pointer and invalid concatenation indication (pointer interpretation). Valid values are the following: 00 = 8, 01 = 9, 10 = 10, and 11 = 8.

0x0

11:8 TMUX_CNTDS1FRAME[3:0] Continuou s N-Times Detect for S1 Frame Bytes.

Sets the number of CNTD frames within which an inconsistent S1 value is detected in the incoming STS-3/STM-1 (AU-4). This value is used in the S1 babble algorithm. The valid range for this register is 0x3—0xF . Invalid values will be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDS1[3:0] Continuous N-Times Detect for S1 Byte. Sets the

number of CNTD occurrences of a consistent S1 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDK2[3:0] Continuous N-Times Detect for K2[2:0] Byte.

Sets the number of CNTD occurrences of a consistent K2[2:0] value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF . Invalid values will be mapped to a value of 0x3.

0xC

Page 99

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

99Agere Systems Inc.

8 TMUX Registers

(continued)

Table 99. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40020 15:12 TMUX_CNTDF2[3:0 ] Continuous N-Time s Detect for F2 Byte. Sets the num-

ber of CNTD occurrences of a consistent F2 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

11:8 TMUX_CNTDRDIP[3:0] Continuous N-Times Detect for G1[3:1] Byte. Sets the

number of CNTD occurrences of a consistent G1[3:1] value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDC2[3:0] Continuous N-Times Detect for C2 Byte. Sets the nu m-

ber of CNTD occurrences of a consistent C2 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDJ1[3:0] Continuous N-Times Detect for J1 Byte. Sets th e num-

ber of CNTD occurrences of a consistent J1 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

0x40021 15:13 — Reserved. 000

12 TMUX_CTDB1SEL Cont inuous N-Ti mes AUTO AIS Select. Control bit,

when set to a logic 1, causes TOH CNTD co unters to be reset whenever the AUTO_AIS signal is asserted.

11:8 TM UX_CNTDN1[3:0] Continuous N-Times Detect for N1 Byte. Sets the num-

ber of CNTD occurrences of a consistent N1 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDK3[3:0] Continuous N-Times Detect for K3 Byte. Sets the num-

ber of CNTD occurrences of a consistent K3 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDF3[3:0] Continuo us N-Times Detect for F3 Byte. Sets the num-

ber of CNTD occurrences of a consistent F3 value in the incoming STS-3/STM- 1 (AU-4) frame. The valid range for this regis ter is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

0x3

Page 100

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SD H x28/x21 DS1/E 1 May 2001

100 Agere Systems Inc.

8 TMUX Registers

(continued)

Table 100. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Cont rol Param eters (R/W)

Table 101. TMUX_RF1MON, Receive Monitor Values (RO)

Table 102. TMUX_RAPSMON, Receive Monitor Values (RO)

Table 103. TMUX_RS1MON, Receive Monitor Values (RO)

Address Bit Name Function Reset

Default

0x40022 15:8 — Reserved. 0x00

7:0 TMUX_C2EXP1[7:0] Expected C2 Byte for Port 1. Should be programmed to

contain expected signal label (C2) for port 1.

0x00

0x40023 15:8 TMUX_C2EXP3[7:0] Expected C2 Byte for Port 3. Should be programmed to

contain expected signal label (C2) for port 3.

0x00

7:0 TMUX_C2EXP2[7:0] Expected C2 Byte for Port 2. Should be programmed to

contain expected signal label (C2) for port 2.

0x00

Address Bit Name Function Reset

Default

0x40024 15:8 TMUX_RF1MON1[7:0] Receive F1 Previous Monitor Value. See Section 17.5.7

F1 Monitor on page 371.

0x00

7:0 T MUX_RF1MON0[7:0] Receive F1 Current Monitor Value. See Section 17.5.7

F1 Monitor on page 371.

0x00

Address Bit Name Function Reset

Default

0x40025 15:3 TMUX_

RAPSMON[12:0]

Receive APS Monitor Value. See Section 17.5.9 Auto-

matic Protection Switch (APS) Monitor on page 371.

0x00

2:0 TMUX_K2MON[2:0] Receive K2 Monitor Value. See Section 17.5.9 Automatic

Protection Switch (APS) Monitor on page 371.

0x0

Address Bit Name Function Reset

Default

0x40026 15:8 — Reserved. 0x00

7:0 TMUX_ RS1MON[7:0] Receive S1 Monitor Value. See Section 17.5.12 Sync

Status Monitor on page 372.

0x00

Datasheet TMXF281553BAL-2-DB Datasheet (Lucent Technologies)

Specifications and Main Features

Frequently Asked Questions

User Manual