Datasheet TLV987CPFB Datasheet (Texas Instruments)

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

10-Bit, 27 MSPS, A/D Converter

D

Single 3-V Supply Operation

D

Low Power: 200 mW Typical at 3 V, 2 mW
Power-Down Mode

D

Differential Nonlinearity Error: <±0.6 LSB
Typ

D

Integral Nonlinearity Error: <±2 LSB Typ

D

Programmable Gain Amplifier (PGA) With
0-dB to 36-dB Gain Range (0.09 dB/step)

D

Automatic or Programmable Black Level
and Offset Calibration

D

Additional DACs for External Analog
Setting

D

Serial Interface for Register Configuration

D

Internal Reference Voltages

D

48-Pin TQFP Package

applications

D

Digital Still Camera

D

Digital Camcorder

D

Digital Video Camera

description

The TLV987 is a highly integrated monolithic analog signal processor/digitizer designed to interface the area
charge-coupled device (CCD) sensors in digital camera applications. The TLV987 performs all the analog
processing functions necessary to maximize the dynamic range, corrects various errors associated with the
CCD sensor, and then converts the results from analog to digital using the on-chip high-speed analog-to-digital
converter (ADC). The key components of the TL V987 include input clamp circuitry, a correlated double sampler
(CDS), and a programmable gain amplifier (PGA). The PGA has 0-dB to 36-dB gain range. In addition, the
TL V987 has two internal digital-to-analog converters (DACs) for automatic or programmable optical black level
and offset calibration. The TLV987 also has two additional DACs for external system control, and internal
reference voltages. The TL V987 has a parallel data port for easy microprocessor interface and a serial port for
configuring internal control registers.

Designed in advanced CMOS process, the TLV987 operates from a single 3-V power supply with a normal
power consumption of 200 mW and a 2 mW power-down mode.

Very high throughput rate, single 3-V operation, low power consumption, and fully integrated analog processing
circuitry make the TLV987 an ideal CCD sensor interfacing solution for digital camera applications.

The device is available in a 48-pin TQFP package and is characterized for operation over 0°C to 70°C operating
free-air temperature range.

AVAILABLE OPTIONS

PACKAGE

T

A

TQFP (PFB)

0°C to 70°C TLV987CPFB

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

14 15

BLKG
TPP
TPM
AV

DD4

AGND4
OBCLP
STBY
RESET
CS
SDIN
SCLK
ADCCLK

36
35
34
33
32
31
30
29
28
27
26
25

16

1
2
3
4
5
6
7
8
9
10
11
12

DIN
PIN

AV

DD2

AGND2

DGND

DV

DD

D0
D1
D2
D3
D4
D5

17 18 19 20

AV

RPD

RMD

RBD

47 46 45 44 4348 42

CLREF

CLAMPSVSR

AGND1

DACO2

DACT

OE

D8

DIV

DIGND

AV

AGND3

40 39 3841

21 22 23 24

37

13

AGND5

AV

V

D7D6D9

PFB PACKAGE

(TOP VIEW)

SS

DD1

DD5

DD

DD3

DACO1

TI is a trademark of Texas Instruments Incorporated.

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Digital

Averager

SV

DIN

Digital Comparator
Fine Offset Control

Σ

DAC

Register

CDS

Three

State

Latch

8-Bit
DAC

Control

Logic

8-Bit
DAC

8-Bit
DAC

10-Bit

ADC

Offset

Register

Offset

Register

PGA

Register

V

b

Register

OB CAL

Register

Internal

Reference

Clamp

Serial

Port

CLAMP

PIN

DACO1

DACO2

OE

D0–D9

RESET
ADCCLK

CLREF TPP TPM RPD RBD RMD

SR
BLKG
OBCLP
STBY

CS
SCLK

SDIN

Σ

PGA

Coarse

Offset

Control

8-Bit
DAC

1.3 V

9

Overflow

DAC

Register

(40)

(47)

(48)

(34)

(39)

(35)

(1)
(2)

(21)

(22)

(24)

(38)

(7-16)

(29)
(25)

(46)
(45)
(36)

(31)
(30)

(28)
(26)

(27)

(23)

DACT

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ADCCLK 25 I ADC clock input.
AGND1 44 Analog ground for internal CDS circuits
AGND2 4 Analog ground for internal PGA circuits
AGND3 20 Analog ground for internal DAC circuits
AGND4 32 Analog ground for internal ADC circuits
AGND5 37 Analog ground for internal REF circuits
AV

DD1

43 Analog supply voltage for internal CDS circuits, 3 V

AV

DD2

3 Analog supply voltage for internal PGA circuits, 3 V

AV

DD3

19 Analog supply voltage for internal DAC circuits, 3 V

AV

DD4

33 Analog supply voltage for internal ADC circuits, 3 V

AV

DD5

41 Analog supply voltage for internal ADC circuits, 3 V
BLKG 36 I Control input. CDS operation is disabled when BLKG is pulled low.
CLAMP 47 I CCD signal clamp control input
CLREF 48 O Clamp reference voltage output.
CS 28 I Chip select. A logic low on this input enables the TLV987.
DACO1 21 O Digital-to-analog converter output1
DACO2 22 O Digital-to-analog converter output2
DACT 23 O MUXed test output for internal offset DACs
DGND 5 Digital ground
DIGND 18 Digital interface circuit ground
DIN 1 I Input signal from CCD
DIV

DD

17 Digital interface circuit supply voltage, 1.8 V to 4.4 V
DV

DD

6 Digital supply voltage, 3 V
D0 – D9 7 – 16 O 10-bit three-state ADC output data or of fset DACs test data
OBCLP 31 I Optical black level and offset calibration control input. Active low.
OE 24 I Output data enable. Active low.
PIN 2 I Input signal from CCD
RBD 38 O Internal bandgap reference for external decoupling
RMD 39 O Ref– output for external decoupling
RPD 40 O Ref+ output for external decoupling
RESET 29 I Hardware reset input, active low. This signal forces a reset of all internal registers.
SCLK 26 I Serial clock input. This clock synchronizes the serial data transfer.
SDIN 27 I Serial data input to configure the internal registers.
SR 45 I CCD reference level sample clock input
STBY 30 I Hardware power-down control input, active low
SV 46 I CCD signal level sample clock input
TPM 34 O MUXed test output: PGA noninverting output or inverted PGA clock
TPP 35 O MUXed test output: PGA inverting output or inverted CDS clock
V

SS

42 Silicon substrate, normally connected to analog ground

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, AVDD, DVDD, DIVDD –0.3 V to 6.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DV

DD

+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN NOM MAX UNIT

Analog supply voltage, A V

DD

2.7 3 3.3 V

Digital supply voltage, DV

DD

2.7 3 3.3 V

Digital interface supply voltage, DIV

DD

1.8 4.4 V

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

DIVDD = 3 V 0.8DIV

DD

V

Low-level input voltage, V

IL

DIVDD = 3 V 0.2DIV

DD

V

Clock frequency, ADCCLK, f

clock1

DVDD = 3 V 27 MHz

Pulse duration, ADCCLK, high, t

w(CLKH)1

DVDD = 3 V 18.5 ns

Pulse duration, ADCCLK, low, t

w(CLKL)1

DVDD = 3 V 18.5 ns

Clock frequency, SCLK, f

clock2

DVDD = 3 V 40 MHz

Pulse duration, SCLK high, t

w(CLKH)2

DVDD = 3 V 12.5 ns

Pulse duration, SCLK low, t

w(CLKL)2

DVDD = 3 V 12.5 ns

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
AV

DD

= DVDD = 3 V, ADCCLK = 27 MHz (unless otherwise noted)

total device

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AI

CC

Analog operating supply current 66 mA

DI

CC

Digital operation supply current 1 mA
Device power consumption 200 mW

Power consumption in power-down mode 2 mW
DNL Full channel differential nonlinearity –1 ±0.6 1.5 LSB
INL Full channel integral nonlinearity ±2 LSB

analog-to-digital converter (ADC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC resolution 10 Bits

Full-scale input span 2 V

PP

Conversion rate 27 MHz

ADC output latency 4.5

CLK

cycles

No missing codes Assured

correlated double sampler (CDS) and programmable gain amplifier (PGA)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CDS and PGA sample rate 27 MHz

CDS full-scale input span Single-ended input 1 V

Input capacitance of CDS 4 pF

Minimum PGA gain 0 1 dB

Maximum PGA gain 35 36 37 dB

PGA gain resolution 0.09 dB

PGA programming code resolution 8-bit monotonic gain control 9 Bits

internal digital-to-analog converters (DAC) for offset correction

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC resolution 8 Bits
INL Integral nonlinearity ±0.6 ±1.2 LSB
DNL Differential nonlinearity ±0.5 ±.99 LSB

Output settling time To 1% accuracy 80 ns

user digital-to-analog converters (DAC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC resolution 8 Bits
INL Integral nonlinearity ±0.5 ±1.2 LSB
DNL Differential nonlinearity ±0.5 ±.99 LSB

Output voltage 0 AV

DD

V

Output settling time 10-pF external load, Settle to 1 mV 4 µs

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
AV

DD

= DVDD = 3 V, ADCCLK = 27 MHz (unlessotherwise noted)

reference voltages

TEST CONDITIONS MIN TYP MAX UNIT

Internal bandgap voltage reference 1.43 1.5 1.58 V
T emperature coef ficient 100 ppm/°C
Voltage reference noise 0.5 LSB
Positive reference voltage, ADC Ref+ Externally decoupled 1.8 2 2.2 V
Negative reference voltage, ADC Ref– Externally decoupled 0.8 1 1.2 V

digital specifications

PARAMETER TEST CONDITIONS

MIN TYP MAX UNIT

LOGIC INPUTS

I

IH

High-level input current DIVDD = 3 V –10 10 µA

I

IL

Low-level input current DIVDD = 3 V –10 10 µA

C

i

Input capacitance 5 pF

LOGIC OUTPUTS

V

OH

High-level output voltage IOH = 50 µA, DIVDD = 3 V DIVDD–0.4 V

V

OL

Low-level output voltage IOL = 50 µA, DIVDD = 3 V 0.4 V

I

OZ

High-impedance output current –10 10 µA

C Output capacitance 5 pF

timing requirements

PARAMETER TEST CONDITIONS

MIN TYP MAX UNIT

t

w(SR)

Pulse duration, SR 50% to 50% 10 ns

t

w(SV)

Pulse duration, SV 50% to 50% 10 ns

t

su1

Setup time, OBCLP ↓ before ADCCLK ↑ Minimum 0.25 × ADCCLK clock cycle

t

h2

Hold time, ADCCLK ↓ after OBCLP ↑

t

d

Delay time, ADCCLK ↓ to ADCOUT valid 4 9 ns

t

su2

Setup time, CS ↓ before SCLK ↑ 0 ns

t

h1

Hold time, SCLK ↓ after CS ↑ 5 ns

0

5

10

15

20

25

30

35

40

0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504

Gain – dB

PGA – Gain Code

Figure 1. TL V987 PGA Gain Code vs Gain

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

P ARAMETER MEASUREMENT INFORMATION

Optical Black Interval

ADC OUT

ADCCLK

OBCLP

CLAMP

BLKG

SV

SR

CCD

Output

Dummy Black

(Blanking) Interval

Signal Interval

t

su1

t

h1

t

w(SV)

n

n n+1

n+1

t

w(SR)

Latency = 4.5 Cycles

t

d

Figure 2. System Operation Timing Diagram

t

su2

SCLK

SDIN

CS

t

h2

DI15 DI14 DI13 DI12 DI10 DI9 DI8 DI0

12345 6716

Figure 3. Timing Diagram

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

BLKG
TPP
TPM

OBCLP
STBY
RESET
CS
SDIN
SCLK
ADCCLK

AV

DD

0.1 µF

10 µF

0.1 µF

1 µF

0.1 µF

0.1 µF

AREA

CCD

0.1 µF

0.1 µF

1 µF

1 µF

1 µF

1 µF0.1 µF

0.1 µF 0.1 µF

AV

DD

AV

DD

SR

SV

CLAMP

AV

DD

DV

DD

D (9–0)

DIV

DD

AV

DD

DV

DD

DIV

DD

3 V
3 V

1.8 V to 4.4 V

Analog Ground
Digital Ground

BLKG

TPP

TPM

OBCLP

STBY

RESET

CS

SDIN

SCLK

ADCCLK

DIN

AV

DD4

AGND4

PIN
AV

DD2
AGND2
DGND

DV

DD
D0

D1
D2
D3
D4
D5

CLREF

CLAMP

SV

SR

AGND1

AV

VAVRPD

RBD

AGND5

RMD

DACT
DACO2
DACO1

AV

DD

1
2
3
4
5
6
7
8
9

10
11

12

SS

DD1

DD5

4847464544434241403938

37

1314151617181920212223

24

D6D7D8D9DIV

DIGNDAVAGND3

DACO1

DACO2

DACT

OE

DD3

DD

36
35
34
33
32
31
30
29
28
27
26
25

TLV987CPFB

OE

(see Note D)

NOTES: A. All analog outputs should be buffered if the load is resistive or if the load is capacitive with more than 2-pF loading.

B. When using the TPP and TPM pins to test internal PGA, the AVDD supply voltage should be 3.3 V .
C. Clock signals on the TPP and TPM pins are inverted.
D. These two capacitors should be placed as close to the device as possible.

Figure 4. Typical Application Connections

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

register definitions

serial input data format

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0

0 0 0 0 Control register.
0 0 0 1 PGA gain register
0 0 1 0 User DAC 1 register
0 0 1 1 User DAC 2 register
0 1 0 0 Coarse offset DAC
0 1 0 1 Fine offset DAC
0 1 1 0 Digital Vb register. Set reference code level at the ADC output during the optical black interval
0 1 1 1 Optical black register. Set the number of black pixels per line and number of lines for digital

averaging

1 0 0 0 T est register

D9 – D0 10-bit data to be written into the selected register

control register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

STBY PDD1 PDD2 ACD AFD X X X RTOB RTSY

control register description

BIT NAME DESCRIPTION

D9 STBY Device power down control: 1 = standby, 0 = active (default)
D8 PDD1 Power down the user DAC1: 1 = standby, 0 = active (default)
D7 PDD2 Power down the user DAC2: 1 = standby, 0 = active (default)
D6 ACD Coarse offset DAC mode control:

0 = Auto calibration (default)
1 = Bypass auto calibration

Note: When D6 is set to 0, D5 must also be set to 0 (auto mode); otherwise, the

auto mode will be disabled on both offset DACs.

D5 AFD Fine offset DAC mode control:

0 = Auto calibration (default)
1 = Bypass auto calibration

Note: D5 can be set to 0 with or without D6 being set to 0.

D4 – D2 X Reserved

D1 RTOB A write of a 1 to this bit resets the calculated black level results in the digital averager.
D0 RTSY A write of a 1 to this bit resets the entire system to the default settings.

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

PGA register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Default PGA gain = X000000000 or 0dB

user DAC1 and DAC2 registers format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Default user DAC register value = XX00000000

coarse offset DAC register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SIGN Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

coarse offset DAC register description

BIT NAME DESCRIPTION

D9 X Reserved
D8 SIGN Coarse DAC sign bit, 0 = + sign (default), 1 = – sign
D7–D0 Coarse DAC control data when D6 in the control register is set to 1

Default coarse DAC register value = X000000000

fine offset DAC register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SIGN Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

fine offset DAC register description

BIT NAME DESCRIPTION

D9 X Reserved
D8 SIGN Fine DAC sign bit, 0 = + sign (default), 1 = – sign
D7–D0 Fine DAC control data when D5 in the control register is set to 1

Default fine DAC register value = X000000000

digital Vb (optical black level) register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Default Vb register value = 40 Hex.

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

optical black calibration register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

OMUX1 OMUX0 LN4 LN3 LN2 LN1 MP PN2 PN1 PN0

optical black calibration register description

BIT NAME DESCRIPTION

D9, D8 OMUX1,

OMUX0

These two bits multiplex digital output (data presented at D(9–0) pins:
OMUX1 OMUX0

0 0 D(9–0) = ADC output (default)
0 1 D(9–0) = ADC output
1 0 D9 = Fine/coarse (1/0) auto-correction flag

D8 = Coarse DAC sign

D(7–0) = Coarse DAC value
1 1 D9 = Fine/coarse (1/0) auto-correction flag
D8 = Fine DAC sign
D(7–0) = Fine DAC value

D7–D4 LN4–LN0 Number of black lines for moving average = 2

L

L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8. Or number of lines can be 1 (default), 2 4,
8, 16, 32, 64, 128, and 256.
The maximum number of lines is 256 even if L > 8.

D3 MP When this bit is 1, the number of black pixels to be averaged per line (2N) is

multiplied by 3.

By setting the MP and PN2–PN0 bits together, the number of optical black
pixels can be programmed to have the following numbers: 1, 2, 3 (1 x 3), 4,
6 (2 x 3), 8, 12 (4 x 3), 16, 24 (8 x 3), 32, 48 (16 x 3), 64, 96 (32 x 3), and
192 (64 x 3).

Default: MP = 0, no multiplication

D2–D0 PN2–PN0 Number of black pixels per line to average = 2

N

N can be 0, 1, 2, 3, 4, 5, and 6. Or number of pixels per line can be 1, 2, 4, 8
(default), 16, 32, and 64.
The maximum number of pixels per line is 64 even if N > 6.

Default optical black calibration register value = 0000000011

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

test register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

Default test register value =1010000000

test register description

BIT NAME DESCRIPTION

D9 – D6 TB9 – TB6 These four bits are used to program the internal DC bias current. The bias current

programming uses the following equation:

I

bias

= 8 µA + (code) x 2 µA

Hence, I

bias

varies from 8 µA (code=0000) to 38 µA (code=11 1 1), with a linear step
of 2 µA.
The recommended setting of the code is 1010 which sets the nominal I

bias

value to

28 µA.

D5, D4 TB5, TB4 Test outputs (pin 34/35 – TPM/TPP) control:

TB5 TB4

0 0 or 1 High impedance outputs at pin TPP and TPM.
1 0 Inverted internal CDS clock at pin TPP,

Inverted internal PGA clock at pin TPM.

1 1 PGA non-inverting output at pin TPP,

PGA inverting output at pin TPM.

D3 TB3 1 = Use external reference, power down internal reference

0 = Use internal reference (default).

D2 TB2 Reserved
D1, D0 TB1, TB0 Test output (pin 23, DACT) control for of fset DACs:

TB1 TB0

0 0 or 1 High impedance outputs at pin DACT (default = 00)
1 0 Fine offset DAC output at pin DACT
1 1 Coarse offset DAC output at pin DACT

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

CDS/PGA signal processor

The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled
and held during the reset reference interval and the video signal interval. By subtracting two resulting voltage
levels, the CDS removes low-frequency noise from the output of the CCD sensor and obtains the voltage
difference between the CCD reference level and the video level of each pixel. Two sample and hold control
pulses (SR

and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TL V987. The ac coupling capacitor is clamped to establish proper
dc bias during the dummy pixel interval by the CLAMP

input. The bias at the input to the TL V987 is set to 1.3

V. Normally, CLAMP

is applied at the sensor’s line rate. A capacitor, with a value ten times larger than that of

the input ac coupling capacitor, should be connected between the CLREF pin and the AGND pin.
When operating the TL V987 at its maximum speed, the CCD internal source resistance should be smaller than

50 Ω. Otherwise, CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 dB to

36 dB by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit
resolution on a linear dB scale, resulting in a 0.09-dB gain step. The gain can be expressed by the following
equation:

Gain = PGA code × 0.09375 dB
Where, the PGA code has a range of 0 to 383.
For example, if the PGA code = 64, then the PGA gain = 6 dB (or gain of 2)
The TLV987 has direct access to the PGA outputs through the TPP pin and the TPM pin. See

test register

description

paragraph for details.

ADC

The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully
differential implementation and digital error correction ensure 10-bit resolution.

The latency of the ADC data output is 4.5 ADCCLK cycles as shown in Figure 2. Pulling the OE pin (pin 24) high
puts the ADC output in high impedance.

user DACs

The TLV987 includes two user DACs that can be used for external analog settings. The output voltage of each
DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When the user
DACs are not used in a camera system, they can be put in the standby mode by programming control bits in
the control register.

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

internal timing

The SR and SV signals are required to operate the CDS as previously explained. The user needs to synchronize
the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by
the ADCCLK signal that is also used internally to control both ADC and PGA operations. It is required that the
positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as shown in Figure 2.
The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance.

The TLV987 has direct access to the CDS and PGA internal clocks through the TPP pin and the TPM pin, which
may be used to assist timing alignment. See

test register description

paragraph for details.

The CLAMP signal is used to activate the input clamping, and the OBCLP signal is used to activate auto optical
black and offset correction.

input blanking function

During some periods of operation, large input transients may occur at the TL V987 input, which can saturate the
input circuits and cause long recovery time. To prevent circuit saturation under such a situation, the TLV987
includes an input blanking function that blocks the input signals by disabling CDS operation whenever the BLKG
input is pulled low.

3-wire serial interface

A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of
the TL V987. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16 bits
long. After two leading null bits, there are four address bits for which internal register is to be updated, the
following ten bits are the data to be written to the register. To enable the serial port, the CS

pin must be held

low. The data transfer is initiated by the incoming SCLK after CS falls.

device reset

When the reset pin (pin 29) is pulled low, all internal registers are set to their default values. The device also
resets itself when it is first powered on. In addition, the TLV987 has a software-reset function that resets the
device when writing a control bit to the control register.

See

test register description

paragraph for the register default values.

voltage references

An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate
the ADC Ref– voltage of 1 V and Ref+ voltage of 2 V. All internally-generated voltages are fixed values and
cannot be adjusted.

power-down mode (standby)

The TLV987 implements both hardware and software power-down modes. Pulling the STBY pin (pin 30) low
puts the device in the low-power stand-by mode. Total supply current drops to about 0.6 mA. Setting a
power-down control bit in the control register can also activate the power-down mode. The user can still program
all internal registers during the power-down mode.

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

power supply

The TLV987 has several power supply pins. Each major internal analog block has a dedicated A VDD supply pin.
All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3 V nominal.

The DIVDD and DIGND pins supply power to the output digital driver (D9–D0). The DIVDD pin is independent
of the DVDD pin and can be operated from 1.8 V to 4.4 V . This allows the outputs to interface with digital ASICs
requiring different supply voltages.

grounding and decoupling

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In the case of power supply decoupling, 0.1-µF ceramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Recommended external decoupling for the three voltage reference pins is
shown in Figure 3. Since their effectiveness depends largely on the proximity to the individual supply pin, all
decoupling capacitors should be placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that the digital ground and analog
ground be shorted immediately outside the package. This can be accomplished by running a low impedance
line between the DGND and AGND pins, under the package.

automatic optical black and offset correction

In the TL V987, the optical black and system channel offset corrections are performed by an auto digital feedback
loop. Two DACs are used to compensate for both channel offset and the optical black of fset. A coarse correction
DAC (CDAC) is located before the PGA gain stage and a fine correction DAC (FDAC) is located after the gain
stage. The digital calibration system is capable of correcting the optical black and channel offset down to one
ADC LSB accuracy.

The TLV987 automatically starts auto-calibration whenever the OBCLP

input is pulled low. The OBCLP pulse

should be wide enough to cover one positive half cycle of the ADCCLK as shown in Figure 1.
For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the

ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared
digitally with the desired output code stored in the Vb register (default is 40h), then control logic adjusts the
FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (±255 ADC LSBs),
the error is corrected by both the CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB
depending on whether the offset is negative or positive, until the output is within the range of the FDAC. The
remaining residue is corrected by the FDAC.

The relationship among the FDAC, CDAC, and ADC in terms of the number of ADC LSBs is as follows:

1 FDAC LSB = 1 ADC LSB,

1 CDAC LSB = 0.5 x PGA linear gain × 1 ADC LSB.
For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 1 ADC LSB.
After auto-calibration is complete, the ADC digital output during CCD signal interval can be expressed by the

following equation:

ADC output [D9–D0] = CCD_input × PGA gain + Vb,
Where, Vb is the desired black level selected by the user. The total offset including optical black offset is

calibrated to be equal to the Vb by adjusting the offset correction DAC during auto-calibration.

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The number of black pixels in each line and the number of lines are programmable. The number of black pixels
per line that can be averaged is equal to 2N, where N can be 0, 1, 2, 3, 4, 5, and 6. In addition, if the MP bit is
set to 1, then the number of black pixels that are averaged per line will be 3  2

N

. The number of lines is equal

to 2L, where L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8.
The auto-calibration feature can be bypassed if the user prefers to directly program the offset DAC registers.

Switching from auto-calibration mode to direct programming mode requires two register writes. First, the control
bits for the offset DACs in the control register need to be changed, then the desired offset value for the register
is loaded into the offset DAC registers for proper error correction. If the total offset including optical black level
is less than ±255 ADC LSBs, only the FDAC needs to be programmed. When switching from the direct
programming mode to the auto-calibration mode, the previous DAC register values are used as starting offsets
rather than default DAC register values.

A detailed block diagram for internal automatic optical black and offset correction is shown in Figure 5. The
timing diagram in Figure 6 illustrates the operation of the calibration system. In the example, the TLV987 is
programmed to average four black pixels (N = 2) per line for two lines (L = 1).

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

CDS

REGISTER

TIMING AND

CALIBRATION LOGIC

VB

ADCPGA

COARSE

DAC

SIGN + CDAC <7:0>

ADC<9:0>

BYPASS

AUTOCOARSE

SP<8:0>

SIGN_CDAC

ADC<9:0>

FDAC CDAC

AUTO CDAC CONTROL

VB<9:0>

L<3:0>,N<2:0>

ADCCLK

OBCLP

RESET

0

1

1 0

SERIAL

PORT

CS

SCLK

SDIN

SP<9:0>

1COARSE DAC

LSB = 0.5 ADC

LSB x PGA Gain

OBREG

FINE
DAC

1FINE DAC

LSB = 1 ADC

LSB

BYPASS
AUTOFINE

SP<8:0>

SIGN + FDAC

<7:0>

DATA

OUT

REGISTER

1 0

PGA GAIN
REGISTER

SIGN_FDAC

AUTO FDAC CONTROL

Figure 5. Optical Black and Offset Correction Block Diagram

TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

First Line

CCD1CCD2CCD3CCD

4

CCD1CCD2CCD3CCD

4

2∧N+1 PIXELS

During this interval an offset of 255 LSB is

intentionally added to the PGA output (see Note)

ADC OUT

for black pixels

OBLC (internal)

OBPC (internal)

ADD255 (internal)

ADCCLK

OBCLP

CDS OUT (internal)

CCD output

SV

SR

PGA samples

”CCD1”

Initiates internal counters, etc.

ADC1ADC2ADC3ADC

4

Second Line

2∧N+1 PIXELS

DACs are updated

3 half cycles

allow settling

Latency = 4.5 Cycles

Figure 6. Optical Black and Offset Correction Timing

T o avoid the ADC being clipped on differential negative input signals, an internal of fset that is equal to 255 ADC
LSBs is intentionally added to the PGA output signal. This offset is only added during the optical black pixel
interval with a total duration of 2

N

+ 3 pixels, where three additional pixels are necessary for accommodating

internal latency adjustment.

TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

24

25

13

12

SQ

36

37

7,20
6,80

48

1

5,50 TYP

SQ

8,80

9,20

1,05
0,95

1,20 MAX

0,08

0,50

M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated