Datasheet TLV986CPFB Datasheet (Texas Instruments)

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Page 1

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10-bit, 12.5 MSPS, A/D Converter

Single 3 V Supply Operation

Low Power: 140 mW Typical at 3-V, 2 mW Power-Down Mode

Full Channel Differential Nonlinearity Error: <±0.5 LSB Typical

Full Channel Integral Nonlinearity Error: <±1 LSB Typical

Programmable Gain Amplifier (PGA) With 0 dB to 36 dB Gain Range (0.1 dB/Step)

Automatic or Programmable Black Level and Offset Calibration

Additional DACs for External Analog Setting

Serial Interface for Register Configuration

Internal Reference Voltages

48-pin TQFP Package

applications

PC Camera

Digital Still Camera

Digital Video Camera

description

The TLV986 is a highly integrated monolithic analog signal processor/digitizer designed to interface the area charge-coupled device (CCD) sensors in digital camera applications. The TLV986 performs all the analog processing functions necessary to maximize the dynamic range, corrects various errors associated with the CCD sensor, and then digitizes the results with an on-chip high-speed analog-to-digital converter (ADC). The key components of the TLV986 include: input clamp circuitry and a correlated double sampler (CDS), a programmable gain amplifier (PGA) with 0 to 36 dB gain range, two internal digital-to-analog converters (DAC) for automatic or programmable optical black level and offset calibration, a 10-bit, 12.5 MSPS pipeline ADC, a parallel data port for easy microprocessor interface, a serial port for configuring internal control registers, two additional DACs for external system control, and internal reference voltages.

Designed in advanced CMOS process, the TLV986 operates from a single 3-V power supply with a normal power consumption of 140 mW and a 2 mW power-down mode.

Single 3-V operation, low power consumption, and fully integrated analog processing circuitry make the TL V986 an ideal CCD sensor interfacing solution for the digital camera applications.

The part is available in a 48-pin TQFP package and is specified over 0_C to 70_C operating temperature range.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

14 15

BLKG TPP TPM AV

DD4

AGND4 OBCLP STBY RESET CS SDIN SCLK ADCCL

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9 10 11 12

DIN PIN

DD2

AGND2

DGND

D0 D1 D2 D3 D4 D5

17 18 19 20

RPD

RMD

RBD

47 46 45 44 4348 42

CLREF

CLAMPSVSR

AGND1

DAC02

DACT

DIGND

DD3

AGND3

DAC01

40 39 3841

21 22 23 24

AGND5

D7D6D9

PFB PACKAGE

(TOP VIEW)

DIV

DD5

DD1

TLV986CPFB

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

TQFP (PFB)

–0_C to 70_C TLV986CPFB

functional block diagram

CLAMP CLREF AV

DD1–5

TPP TPM RPD RBD RMD

INT. REF.

DIV

CLAMP 1.2 V

CDS

DIN PIN

∑

PGA

8–BIT

DAC

OFFSET

REG

COARSE

OFFSET

CONTROL

PGA REG

10–BIT

ADC

∑

8–BIT

DAC

OFFSET

REG

DIGITAL COMPARATOR

FINE OFFSET CONTROL

REG

DIGITAL

AVERAGER

OB CAL

REG

DAC01

DAC02

8–BIT

ADC

DAC REG

8–BIT

ADC

DAC REG

OVERFLOW

CONTROL

LOGIC

RESET CLK SV SR BLKG OBCLP STBY

SERIAL

PORT

CS SCLK SDIN

THREE

STATE

LATCH

AGND1–5 DACTV

DGND DIGND

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TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ADCCLK 25 I ADC clock input AGND1 44 Analog ground for internal CDS circuits AGND2 4 Analog ground for internal PGA circuits AGND3 20 Analog ground for internal DAC circuits AGND4 32 Analog ground for internal ADC circuits AGND5 37 Analog ground for internal REF circuits AV

DD1

43 Analog supply voltage for internal CDS circuits, 3 V

DD2

3 Analog supply voltage for internal PGA circuits, 3 V

DD3

19 Analog supply voltage for internal DAC circuits, 3 V

DD4

33 Analog supply voltage for internal ADC circuits, 3 V

DD5

41 Analog supply voltage for internal ADC circuits, 3 V BLKG 36 Control input. The CDS operation is disabled when the BLKG is pulled low. CLAMP 47 I CCD signal clamp control input CLREF 48 O Clamp reference voltage output CS 28 I Chip Select. A logic low on this input enables the TLV986. D0–D9 7–16 O 10-bit 3-state ADC output data or offset DACs test data DACO1 21 O Digital-to-analog converter output1 DACO2 22 O Digital-to-analog converter output2 DACT 23 O MUXed test output for internal offset DACs DGND 5 Digital ground DIGND 18 Digital interface circuit ground DIN 1 I Input signal from CCD DIV

17 Digital interface circuit supply voltage, 1.8 V – 4.4 V DV

6 Digital supply voltage, 3-V OBCLP 31 I Optical black level and offset calibration control input, active low OE 24 I Output data enable, active low PIN 2 I Input signal from CCD RESET 29 I Hardware reset input, active low. This signal forces a reset of all internal registers. RBD 38 O Internal bandgap reference for external decoupling RMD 39 O Ref– output for external decoupling RPD 40 O Ref+ output for external decoupling SCLK 26 I Serial clock input. This clock synchronizes the serial data transfer. SDIN 27 I Serial data input to configure the internal registers SR 45 I CCD reference level sample clock input STBY 30 I Hardware power-down control input, active low SV 46 I CCD signal level sample clock input TPM 34 O Muxed test output: PGA noninverting output or inverted PGA clock TPP 35 O Muxed test output: PGA inverting output or inverted CDS clock V

42 Silicon substrate, normally connected to analog ground

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, AVDD, DVDD, DIVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to AV

+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

STG

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN NOM MAX UNIT

Analog supply voltage, A V

2.7 3 3.3 V

Digital supply voltage, DV

2.7 3 3.3 V

Digital interface supply voltage, DIV

1.8 4.4 V

digital inputs

MIN NOM MAX UNIT

High–level input voltage, V

DIVDD = 3 V 0.8DIV

Low–level input voltage, V

DIVDD = 3 V 0.2DIV

V Input ADCCLK frequency DVDD = 3 V 12.5 MHz ADCCLK pulse duration, clock high, t

w(MCLK)

DVDD = 3 V 40 ns

ADCCLK pulse duration, clock low, t

w(MCLKL)

DVDD = 3 V 40 ns Input SCLK frequency DVDD = 3 V 40 MHz SCLK pulse duration, clock high, t

w(SCLKH)

DVDD = 3 V 12.5 ns SCLK pulse duration, clock low, t

w(SCLKL)

DVDD = 3 V 12.5 ns

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TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, T

= 25°C, AVDD = DVDD = 3 V, ADCCLK = 12.5 MHz (unlessotherwise noted)

total device

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AVDD operating current 41 mA DVDD operation current 6 mA Device power consumption 140 mW Power consumption in power–down mode 2 mW

INL Full channel integral nonlinearity

±1 ±2 LSB

DNL Full channel differential nonlinearity

= 2.7 V – 3.

–1 ±0.5 1.5 LSB

No missing code Assured Full channel output latency 4.5

CLK

cycles

analog-to-digital converter (ADC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC resolution 10 Bits Full scale input span

2 V

P-P

Conversion rate 12.5 MHz

correlated double sampler (CDS) and programmable gain amplifier (PGA)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CDS and PGA sample rate 12.5 MHz CDS full scale input span Single-ended input 1 V Input capacitance of CDS 4 pF Minimum PGA gain 0 1 dB Maximum PGA gain 35 36 37 dB PGA gain resolution 0.1 dB PGA programming code resolution 8-bit monotonic gain control 9 Bits

internal digital-to-analog converters (DAC) for offset correction

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC resolution 8 Bits INL Integral nonlinearity ±0.5 ±1.2 LSB DNL Dif ferential nonlinearity ±0.5 ±0.9 LSB

Output settling time To 1% accuracy 80 ns

user digital-to-analog converters (DAC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC resolution 8 Bits INL Integral nonlinearity ±0.5 ±1.2 LSB DNL Dif ferential nonlinearity ±0.6 ±0.9 LSB

Output voltage range 0 3 V

Output settling time 10 pF external load. Settle to 1 mV. 4 µs

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, T

= 25°C, AVDD = DVDD = 3 V, ADCCLK = 12.5 MHz (unlessotherwise noted) (continued)

reference voltages

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Internal bandgap voltage reference 1.43 1.50 1.58 V T emperature coef ficient 100 ppm/°C ADC Reference+

1.8 2 2.2 V

ADC Reference–

Externally decoupled

0.9 1 1.1 V

digital specifications

logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input current

–10 10 µA

Low-level input current

DIV

= 3

–10 10 µA

Input capacitance 5 pF

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage IOH = 50 µA, DIVDD = 3 V DIVDD–0.4 V

Low-level output voltage IOL= 50 µA, DIVDD = 3 V 0.4 V

High-impedance-state output current –10 10 µA

Output capacitance 5 pF

key timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SRW)

SR pulse width

10 ns

(SVW)

SV pulse width

Measured at 50% of pulse height

10 ns

(OBS)

OBCLP falling edge to ADCCLK rising edge Minimum 0.25 × one ADCCLK cycle

(OBE)

ADCCLK falling edge to OBCLP rising edge Not critical, but should not exceed 2N pixels

(OD)

ADCCLK to output data delay 4 9 ns

(CSF)

CS falling edge to SCLK rising edge 0 ns

(CSR)

SCLK falling edge to CS rising edge 5 ns

0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504

Gain – dB

PGA – Gain Code

TLV986 GAIN

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TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

n+1

CCD

OUTPUT

Optical

Black

Interval

Dummy

Black (Blanking)

Interval

Signal Interval

SRW

SVW

BLKG

CLAMP

OBCLP

OBS

OBE

ADCCLK

ADC OUT

Latency: 4.5 ADC Cycles

Figure 1. System Operation Timing Diagram

SDIN

CSF

DI15 DI14 DI13 DI12 DI10 DI9 DI8 DI0

SCLK

CSR

234567 16

Figure 2. Serial Interface Timing Diagram

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

BLKG

TPP

TPM

DD4

AGND4 OBCLP

STBY

RESET

SDIN

SCLK

ADCCLK

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9

DIN PIN AV

DD2

AGND2 DGND DV

D0 D1 D2 D3 D4 D5

TLV986CPFB

1 µF

Input

CLAMP

Input

0.1 µF

1 µF

0.1 µF

1 µF

BLKG

Input

TPP Output

TPM Output

OBCLP

Input

STBY

Input

RESET

Input

SDIN Input

SCLK Input

ADCCLK Input

0.1 µF

DACT Output DAC02 Output DAC01 Output

OE Input

0.1 µF

DIV

D (0–9)

0.1 µF

AREA

CCD

Analog Ground

Digital Ground

3 V

DIV

1.8 V to 4.4 V

4847464544434241403938

1314151617181920212223

CLREF

CLAMP

AGND1

RPD

RMD

RBD

AGND5

DD1

DD5

DD3

VDD

D6D7D8

DIGND

AGND3

DAC01

DAC02

DACT

See Note D

NOTES: A. All analog outputs should be buffered if the load is resistive If the load is capacitive with more than 2 pF loading.

B. When using the TPP and TPM pins to test internal PGA, the AVDD supply voltage should be 3.3 V. C. Clock signals on the TPP and TPM terminals are inverted. D. Place these two capacitors as close to the device as possible.

Figure 3. Typical Application Connection

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TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

serial input data format

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 D9–D0

0 0 0 0 Control register 10-bit data to be written into the selected register 0 0 0 1 PGA gain register 0 0 1 0 User DAC1 register 0 0 1 1 User DAC2 register 0 1 0 0 Coarse offset DAC 0 1 0 1 Fine offset DAC 0 1 1 0 Digital Vb register (set reference code level at the ADc output during the optical black interval) 0 1 1 1 Optical black register (set the number of black pixels per line and number of the lines for digital averaging) 1 0 0 0 Test register

control register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

STBY PDD1 PDD2 ACD AFD X X X RTOB RTSY

control register description

BIT NAME DESCRIPTION

D9 STBY Device power down control: 1 = standby, 0 = active (default) D8 PDD1 Power down the user DAC1: 1 = standby, 0 = active (default) D7 PDD2 Power down the user DAC2: 1 = standby, 0 = active (default) D6 ACD Coarse offset DAC mode control:

0 = Auto calibration (default), 1 = Bypass auto calibration Note: When D6 is set to 0, D5 must also be set to 0 (automode). Otherwise, the automode will be disabled on both offset DACs.

D5 AFD Fine offset DAC mode control:

0 = Auto calibration (default), 1 = Bypass auto calibration. Note: D5 can be set to 0 with or without the D6 being set to 0.

D4–D2 X Reserved

D1 RTOB Write 1 to this bit will reset calculated black-level results in the digital averager. D0 RTSY #Write 1 to this bit will rewet entire system to the default settings.

PGA register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Default PGA gain = X000000000 or 0 dB

user DAC1 and DAC2 registers format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

S S BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Default user DAC register value = XX00000000

Page 10

TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

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coarse offset DAC register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SIGN BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

coarse offset DAC register description

BIT NAME DESCRIPTION

D9 X Reserved D8 SIGN Coarse DAC sign bit, 0 = + sign (default), 1 = – sign

D7–D0 Coarse DAC control data when the D6 in the control register is set at 1.

Default coarse DAC register value = X000000000

fine offset DAC register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SIGN BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

fine offset DAC register description

BIT NAME DESCRIPTION

D9 X Reserved D8 SIGN Fine DAC sign bit, 0 = + sign (default), 1 = – sign

D7–D0 Fine DAC control data when the D5 in the control register is set at 1.

Default fine DAC register value = X000000000

digital Vb (optical black level) register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Default Vb register value = 40 hex

Page 11

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

optical black calibration register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

OMUX1 OMUX0 LN4 LN3 LN2 LN1 MP PN2 PN1 PN0

optical black calibration register description

BIT NAME DESCRIPTION

D9, D8 OMUX1, OMUX0 These two bits multiplex digital output (data presented at D[9:0] pins):

OMUX1 OMUX0 0 0 D[9:0] = ADC output (default) 0 1 D[9:0] = ADC output 1 0 D[9] = fine/coarse (1/0) auto–correction flag 1 1 D[9] = fine/coarse (1/0) auto–correction flag

D[8] = fine DAC sign D[7:0] = fine DAC value

D7–D4 LN4–LN0

Number of black lines for moving average = 2L. The L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8. Or number of lines can be 1(default), 2, 4, 8, 16, 32, 64, 128, and 256. The maximum number of lines is 256 even if L>8.

D3 MP

When this bit is 1, the number of black pixels to be averaged per line (2N) is multiplied by 3. By setting the MP and PN2–PN0 bits together, the number of optical black pixels can be programmed to have

the following numbers: 1, 2, 3 (1X3), 4, 6 (2×3), 8, 12 (4×3), 16, 24 (8×3), 32, 48 (16×3), 64, 96 (32×3), and 192 (64×3). Default: MP = 0, no multiplication.

D2–D0 PN2–PN0

Number of black pixels per line to average = 2

The N can be 0, 1, 2, 3, 4, 5, and 6. Or number of pixels per line can be 1, 2, 4, 8 (default), 16, 32, and 64. The maximum number of pixels per line is 64 even if N>6.

Default optical black calibration register value = 0000000011

Page 12

TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

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optical black calibration register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

Default test register value = 0110000000

test register description

BIT NAME DESCRIPTION

D9–D6 TB9–TB6

These four bits are used to program the internal dc bias current. The bias current programming uses following equation:

bias

= 8 µA + (code) × 2 µA

Hence, I

bias

varies from 8 µA (code=0000) to 38 µA (code=1111), with a linear step of 2 µA.

Recommend to set the code to 0101.

D5, D4 TB5, TB4 Test outputs (pin 34/35 – TPM/TPP) control:

TB5 TB4 0 0 or 1 High impedance outputs at pin TPP and TPM. 1 0 Inverted internal CDS clock at pin TPP.

Inverted internal PGA clock at pin TPM.

1 1 PGA noninverting output at pin TPP.

PGA inverting output at pin TPM.

D3 TB3 1 – use external reference, power down internal reference

0 – use internal reference (default).

D2 TB2 Reserved

D1, D0 TB1, TB0 T est output (pin 23 – DACT) control for offset DACs:

TB1 TB0 0 0 or 1 High impedance outputs at pin DACT (default = 00) 1 0 DACT = fine offset DAC output at pin DACT 1 1 DACT = coarse offset DAC output at pin DACT

Page 13

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

CDS/PGA signal processor

The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor and obtains the voltage difference between the CCD reference level and the video level of each pixel. T wo sample/hold control pulses (SR

and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TL V986. The ac coupling capacitor is clamped to establish proper dc bias during the dummy pixel interval by the CLAMP

input. The bias at the input to the TL V986 is set to 1.2

V . Normally, the CLAMP

is applied at sensor’s line rate. Connect a capacitor with a value ten times larger than

the input ac coupling capacitor between the CLREF terminal and the AGND. When operating the TLV986 at its maximum speed, the CCD internal source resistance should be less than

50 Ω. Otherwise, the CCD output buffering is required. The signal is sent to the PGA after the CDS function is complete. The PGA gain is adjustable from 0 to 36 dB

by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit resolution on a linear dB scale, resulting in a 0.09 dB gain step. The gain can be expressed by the following equation,

Gain = PGA code × 0.09375 dB Where: PGA code has a range of 0 to 383 For example, If PGA code = 64, then the PGA Gain = 6 db (or gain of 2) The TLV986 has direct access to the PGA outputs through the TPP terminal and the TPM terminal. See

Test

for details.

ADC

The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully differential implementation and digital error correction ensure 10-bit resolution.

The latency of the ADC data output is 4.5 ADCCLK cycles as shown in Figure 1. Pulling OE (terminal 24) high puts the ADC output in high impedance.

user DACs

The TLV986 includes two user DACs that can be used for external analog settings. The output voltage of each DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When the user DACs are not in use in a camera system, they can be put in the standby mode by programming control bits in the control register.

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

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PRINCIPLES OF OPERATION

internal timing

Operating the CDS requires signals SR and SV as previously explained. The user needs to synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by the ADCCLK signal that is also used internally to control both ADC and PGA operations. It is necessary that the positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as shown in Figure 1. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance.

The TLV986 has direct access to the CDS and PGA internal clocks through the TPP and TPM terminal. The TPP and TPM assist the user in timing alignment. See

Test Register Description

for details.

The CLAMP signal activates the input clamping and the OBCLP signal activates auto optical black and offset correction.

input blanking function

During some period of operation, large input transients may occur at the TLV986’s input, saturating the input circuits and causing long recovery time. T o prevent the circuit saturation, the TL V986 includes an input blanking function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulled low.

3-wire serial interface

A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of the TLV986. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16bits long. After two leading null bits, there are four address bits for which internal register is to be updated; the following ten bits are the data to be written to the register. To enable the serial port, the CS pin must be held low. The data transfer is initiated by the incoming SCLK after the CS

falls.

device reset

When the reset (terminal 29) is pulled low, all internal registers are set to their default values. The device also resets itself when it is first powered on. In addition, the TLV986 has a software-reset function that resets the device when writing a control bit to the control register. See

section for the register default

values.

device reset

section for the register default

values.

power-down mode (standby)

The TL V986 has both hardware and software power–down modes. Pulling the STBY (terminal 30) low puts the device in the low-power standby mode. Total supply current drops to ~0.6 mA. Setting a power-down control bit in the control register can also activate the power-down mode. The user can still program all internal registers during the power-down mode.

Page 15

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

voltage references

An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate the ADC Ref– voltage of 1 V and Ref+ of 2 V. It also sets the clamp voltage. All internally-generated voltages are fixed values and cannot be adjusted.

power supply

The TLV986 has several power supply pins. Each major internal analog block has a dedicated AVDD supply terminal. All internal digital circuitry is powered by the DVDD. Both AVDD and DVDD are 3 V nominal.

The DIVDD and DIGND pins supply power to the output digital driver (D9–D0). The DIVDD is independent of the DVDD and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiring different supply voltages.

grounding and decoupling

General practices apply to the PCB design to limit high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference terminals be sufficiently bypassed. In the case of power supply decoupling. A 0.1 µF ceramic chip capacitor are adequate to keep the impedance low over a wide frequency range. Recommended external decoupling for the three voltage reference terminals is shown in Figure 3. Since their effectiveness depends largely on the proximity to the individual supply terminal, all decoupling capacitors should be placed as close to the supply terminals as possible.

To reduce high-frequency and noise-coupling, it is highly recommended that digital and analog ground be shorted immediately outside the package. This can be accomplished by running a low impedance line between the DGND and AGND, under the package.

automatic optical black and offset correction

In the TL V986, the optical black and system channel offset corrections are performed by an auto digital feadback loop. Two DACs are used to compensate for both channel offset and the optical black of fset. A coarse correction DAC (CDAC) is located before PGA gain stage and a fine correction DAC (FDAC) is located after the gain stage. The digital calibration system is capable of correcting the optical black and channel offset down to one ADC LSB accuracy .

The TLV986 automatically starts the auto-calibration whenever the OBCLP input is pulled low , the OBCLP pulse should be wide enough to cover one positive half cycle of the ADCCLK as shown in Figure 1.

For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared digitally with the desired output code stored in the Vb register (default is 40H), then control logic adjusts the FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (±255 ADC LSBs), the error is corrected by both CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB depending on whether the offset is negative of positive, until the output is within the range of the FDAC. The remaining residue is corrected by the FDAC.

The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows,

1 FDAC LSB = 1 ADC LSB,

1 CDAC LSB = 0.5 x PGA linear gain × 1 ADC LSB. For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 1 ADC LSBs.

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TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

automatic optical black and offset correction (continued)

After the auto-calibration is complete, the ADC’s digital output during CCD signal interval can be expressed by the following equation,

ADC output [D9–D0] = CCD_input × PGA gain + Vb, Where: Vb is the desired black level selected by user. The total offset including optical black offset is calibrated to be equal to the Vb by adjusting the offset correction

DACs during the auto-calibration. The number of black pixels in each line and number of lines are programmable. The number of black pixels per

line that can be averaged equals to 2

, where N can be 0, 1, 2, 3, 4, 5, and 6. The number of lines equals to

2L, where L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8. The auto-calibration feature can be bypassed if the user prefers to directly program the offset DAC registers.

Switching the auto-calibration mode to the direct programming mode requires two register writes. First, the control bits for the offset DACs in the control register needs to be changed then desired offset value for the register is loaded to the offset DAC registers for proper error correction. If the total offset including optical black level is less than ±255 ADC LSBs, only the FDAC needs to be programmed. When switching from the direct programming mode to the auto-calibration mode, the previous DAC register values are used as starting offsets rather than default DAC register values.

A detailed block diagram for the internal automatic optical black and offset correction is shown in Figure 4. The timing diagram in Figure 5 illustrates the operation of the calibration system. In the example, the TLV986 is programmed to average four black pixels (N=2) per line for two lines (L=1).

Page 17

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

CDS

TIMING AND

CALIBRATION LOGIC

ADCPGA

COARSE

DAC

SIGN + CDAC <7:0>

ADC<9:0>

BYPASS

AUTOCOARSE

SP<8:0>

SIGN_CDAC

ADC<9:0>

FDAC CDAC

AUTO CDAC CONTROL

VB<9:0>

L<3:0>,N<2:0>

ADCCLK

OBCLP

RESET

1 0

SERIAL

PORT

SCLK

SDIN

SP<9:0>

1COARSE DAC

LSB = 0.5 ADC

LSB x PGA Gain

OBREG

FINE DAC

1FINE DAC

LSB = 1 ADC

LSB

BYPASS AUTOFINE

SP<8:0>

SIGN + FDAC

<7:0>

DATA

OUT

1 0

PGA GAIN REGISTER

SIGN_FDAC

AUTO FDAC CONTROL

Figure 4. Optical Black and Offset Correct Block Diagram

Page 18

TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

CCD1CCD2CCD3CCD

CCD

Output

CDS OUT

(Internal)

OBCLP

ADCCLK

ADD255 (Internal)

OBPC

(Internal)

OBLC

(Internal)

ADC OUT

For Black Pixels

ADC

Initiates Internal Counters, etc.

2^N + 1 PIXELS

First Line Second Line

PGA Samples

CCD1

During this interval an offset of 255 LSB is

intentionally added to the PGA output (see Note)

3 Half Cycles Allow Settling

DACs Are Updated

2^N + 1 PIXELS

NOTE: T o avoid the ADC being clipped on dif ferential negative input signals, an internal offset that equals to 255 ADC LSBs is intentionally added

to the PGA output signal. This offset is only added during optical black pixel interval with a total duration of 2N + 3 pixels, where three additional pixels are necessary for accommodating internal latency adjustment.

Figure 5. Optical Black and Offset Correction Timing

Page 19

TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JUL Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

7,20 6,80

5,50 TYP

8,80

9,20

1,05 0,95

1,20 MAX

0,08

0,50

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

Page 20

IMPORTANT NOTICE

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Datasheet TLV986CPFB Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual