Datasheet TLV5638 Datasheet (TEXAS INSTRUMENTS)

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8
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6
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DIN

SCLK

CS

OUTA

V

DD

OUTB
REF
AGND

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18

16
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1312119 10

5

4

6
7
8

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OUTB
NC
REF
NC

NC

SCLK

NC
CS
NC

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DIN

NC

NC

OUTA

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AGND

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DD

V

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH
INTERNAL REFERENCE AND POWER DOWN

FEATURES

• Dual 12-Bit Voltage Output DAC

• Programmable Internal Reference

• Programmable Settling Time:

– 1 µs in Fast Mode,
– 3.5 µs in Slow Mode

• Compatible With TMS320 and SPI™ Serial

Ports

• Differential Nonlinearity <0.5 LSB Typ

• Monotonic Over Temperature

APPLICATIONS

• Digital Servo Control Loops

• Digital Offset and Gain Adjustment

• Industrial Process Control

• Machine and Motion Control Devices

• Mass Storage Devices

TLV5638

DESCRIPTION

The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows
glueless interface to TMS320, SPI™, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serial
string containing 4 control and 12 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the
designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the
TLV5638 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an
8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperature
ranges. It is also available in JG and FK packages in the military temperature range.

SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 1999–2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Serial

Interface

and

Control

12-Bit

DAC B

Latch

SCLK

DIN

CS

OUTA

Power-On

Reset

x2

12

2-Bit

Control

Latch

Power

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

12-Bit

DAC A

Latch

12

REF AGND V

DD

2

12 12

OUTB

x2

Buffer

12

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

T

A

0 ° C to 70 ° C TLV5638CD — —

40 ° C to 85 ° C TLV5638ID — —
40 ° C to 125 ° C — —
55 ° C to 125 ° C — TLV5638MJG TLV5638MFK

AVAILABLE OPTIONS

PACKAGE

SOIC CERAMIC DIP 20 PAD LCCC

(D) (JG) (FK)

TLV5638QD

TLV5638QDR

FUNCTIONAL BLOCK DIAGRAM

2

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SLAS225C – JUNE 1999 – REVISED JANUARY 2004

Terminal Functions

TERMINAL

NAME NO.

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
OUT A 4 O DAC A analog voltage output
OUT B 7 O DAC B analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V

DD

I/O/P DESCRIPTION

8 P Positive power supply

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage (V
Reference input voltage range -0.3 V to V
Digital input voltage range -0.3 V to V
Operating free-air temperature range, T

Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C

(1) Stresses beyond those listedunder, , absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings

only, and functional operation of the deviceat these or any other conditions beyond those indicated under, , recommended operating
conditions” is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect devicereliability.

to AGND) 7 V

DD

A

TLV5638C 0 ° C to 70 ° C
TLV5638I -40 ° C to 85 ° C
TLV5638Q -40 ° C to 125 ° C
TLV5638M -55 ° C to 125 ° C

stg

(1)

UNIT

+ 0.3 V

DD

+ 0.3 V

DD

-65 ° C to 150 ° C

TLV5638

DISSIPATION RATING TABLE

PACKAGE

D 635 mW 5.08 mW/ ° C 407 mW 330 mW 127 mW
FK 1375 mW 11.00 mW/ ° C 880 mW 715 mW 275 mW
JG 1050 mW 8.40 mW/ ° C 672 mW 546 mW 210 mW

(1) This is the inverse of thetraditional Junction-to-Ambient thermal Resistance (R θJA). Thermal Resistances are not production testedand

are for informational purposes only.

TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C TA= 125 ° C

POWER RATING ABOVE TA= 25 ° C

(1)

POWER RATING POWER RATING POWER RATING

3

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TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

RECOMMENDED OPERATING CONDITIONS

V

= 5 V 4.5 5 5.5 V

Supply voltage, V

DD

Power on reset, POR 0.55

High-level digital input voltage, V

Low-level digital input voltage, V

Reference voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C
Clock frequency, f

to REF terminal V

ref

to REF terminal V

ref

L

L

CLK

Operating free-air temperature, T

IH

IL

A

(1) This parameter is not testedfor Q and M suffix devices.
(2) Due to the x2 output buffer,a reference input voltage ≥ (V

internal reference must be disabled, if an externalreference is used.

DD

V

= 3 V 2.7 3 3.3 V

DD

V

= 2.7 V 2 V

DD

V

= 5.5 V 2.4

DD

V

= 2.7 V 0.6 V

DD

V

= 5.5 V V

DD

= 5 V

DD

= 3 V

DD

TLV5638C and TLV5638I 1
TLV5638Q and TLV5638M 0.8

(2)
(2)

TLV5638C 0 70
TLV5638I 40 85
TLV5638Q 40 125
TLV5638M 55 125

-0.4 V)/2 causes clipping of the transfer function.The output buffer of the

DD

MIN NOM MAX UNIT

(1)

(1)

2

AGND 2.048 VDD-1.5 V
AGND 1.024 VDD-1.5 V

2 k Ω

100 pF

20 MHz

V

° C

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, V

POWER SUPPLY

PARAMETER TEST CONDITIONS UNIT

I

PSRR Power supply rejection ratio dB

(1) Power supply rejection ratioat zero scale is measured by varying VDDand is given by: PSRR = 20 log [(E
(2) Power supply rejection ratioat full scale is measured by varying VDDand is given by: PSRR = 20 log [(E

Power supply current All inputs = AGND or VDD,

DD

Power-down supply current 0.01 10 µA

-E

(V

min))/V

ZS

DD

-E

min))/V

G(VDD

max]

DD

max]

DD

ref

No load,
DAC latch = 0x800

Zero scale,
Full scale,

= 2.048 V, V

(1)

(2)

= 1.024 V (unless otherwise noted)

ref

VDD= 5 V,
Int. ref.

V

= 3 V,

DD

Int. ref.
V

= 5 V,

DD

Ext. ref.
V

= 3 V,

DD

Ext. ref.

TLV5638C, I

TLV5638M

MIN TYP MAX

Fast 4.3 7
Slow 2.2 3.6
Fast 3.8 6.3
Slow 1.8 3.0
Fast 3.9 6.3
Slow 1.8 3.0
Fast 3.5 5.7
Slow 1.5 2.6

65
65

(V

max)

ZS

DD

max)

G(VDD

mA

mA

mA

mA

4

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TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating conditions, V

STATIC DAC SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits

INL See

DNL Differential nonlinearity See
E

ZS

EZSTC See

E

G

EGT

C

OUTPUT SPECIFICATIONS

V

O

REFERENCE PIN CONFIGURED AS OUTPUT (REF)

Vref(OUTL) Low reference voltage 1.003 1.024 1.045 V
Vref(OUTH) High reference voltage V
Iref(source) Output source current 1 mA
Iref(sink) Output sink current -1 mA

PSRR Power supply rejection ratio -65 dB

REFERENCE PIN CONFIGURED AS INPUT (REF)

V

I

R

I

C

I

DIGITAL INPUTS

I

IH

I

IL

C

i

(1) The relative accuracy orintegral nonlinearity (INL) sometimes referred to as linearity error, is themaximum deviation of the output from

the line between zero and full scaleexcluding the effects of zero code and full-scale errors. Tested from code 32to 4095.

(2) The differential nonlinearity(DNL) sometimes referred to as differential error, is the difference betweenthe measured and ideal 1 LSB

amplitude change of any two adjacent codes.Monotonic means the output voltage changes in the same direction (or remainsconstant)

as a change in the digital input code.
(3) Zero-scale error is thedeviation from zero voltage output when the digital input code iszero.
(4) Zero-scale-error temperaturecoefficient is given by: E
(5) Gain error is the deviationfrom the ideal output (2V
(6) Gain temperature coefficientis given by: EGTC = [EG(T
(7) Reference feedthrough ismeasured at the DAC output with an input code = 0x000.

Integral nonlinearity, end point ad­justed

Zero-scale error (offset error at zero
scale)

Zero-scale-error temperature coef­ficient

Gain error See
Gain error temperature coefficient See

Output voltage RL= 10 k Ω 0 VDD-0.4 V
Output load regulation accuracy VO= 4.096 V, 2.048 V, RL= 2 k Ω ± 0.25

Load capacitance 100 pF

Input voltage 0 VDD-1.5 V
Input resistance 10 M Ω
Input capacitance 5 pF

Reference input bandwidth REF = 0.2 Vpp+ 1.024 V dc

Reference feedthrough REF = 1 Vppat 1.024 V dc

HIgh-level digital input current VI= V
Low-level digital input current VI= 0 V -1 µA
Input capacitance 8 pF

= 2.048 V, V

ref

= 1.024 V (unless otherwise noted)

ref

C and I

(1)

suffixes
Q and M

suffixes

(2)

(3)

See

(4)

(5)

(6)

> 4.75 V 2.027 2.048 2.069 V

DD

± 1.7 ± 4 LSB

± 1.7 ± 6 LSB
± 0.4 ± 1 LSB

10 ppm/ ° C

10 ppm/ ° C

Fast 1.3 MHz
Slow 525 kHz

(7)

DD

TC =[E

ZS

- 1 LSB) withan output load of 10 k Ω excluding the effects of thezero-error.

ref

max

(T

) - EZS(T

ZS

max

) -E

)]/V

G(Tmin

× 10

ref

)]/V

min

6

/(T

max

6

× 10

/(T

ref

- T

).

min

-T

max

).

min

-80 dB

± 24 mV

± 0.6

1 µA

% full

scale V

% full

scale V

5

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t

wL

SCLK

CS

DIN

D15 D14 D13 D12 D1 D0 XX

1

X

2 3 4 5 15 16

X

t

wH

t

su(D)th(D)

t

su(CS-CK)

t

su(C16-CS)

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating conditions, V

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

s(FS)

t

s(CC)

SR Slew rate RL= 10 k Ω , CL= 100 pF, See

SNR Signal-to-noise ratio 69 74
S/(N+D) Signal-to-noise + distortion 58 67
THD Total harmonic distortion 69 57

(1) Settling time is the timefor the output signal to remain within ± 0.5 LSB of the final measured value fora digital input code change of
(2) Settling time is the timefor the output signal to remain within ± 0.5 LSB of the final measured valuefor a digital input code change of one
(3) Slew rate determines thetime it takes for a change of the DAC output from 10% to 90% full-scalevoltage.

Output settling time, full scale RL= 10 k Ω , CL= 100 pF, See

Output settling time, code to code RL= 10 k Ω , CL= 100 pF, See

Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = V

Spurious free dynamic range 57 72

0x020 to 0xFDF and 0xFDF to 0x020 respectively.Not tested, assured by design.

count. Not tested, assured bydesign.

= 2.048 V, V

ref

= 1.024 V (unless otherwise noted)

ref

fs= 480 kSPS, f
CL= 100 pF

(1)

= 1 kHz, RL= 10 k Ω ,

out

Fast 1 3
Slow 3.5 7

(2)

Fast 0.5 1.5
Slow 1 2

(3)

Fast 12
Slow 1.8

DD

5 nV-s

µs

µs

V/µs

dB

DIGITAL INPUT TIMING REQUIREMENTS

t

su(CS-CK)

t

su(C16-CS)

t

wH

t

wL

t

su(D)

t

h(D)

MIN NOM MAX UNIT

Setup time, CS low before first negative SCLK edge 10 ns
Setup time, 16

th

negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns
SCLK pulse width high 25 ns
SCLK pulse width low 25 ns
Setup time, data ready before SCLK falling edge 10 ns
Hold time, data held valid after SCLK falling edge 5 ns

PARAMETER MEASURMENT INFORMATION

6

Figure 1. Timing Diagram

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2.5

2

1.5

0.5
–40 –30–20 –10 0 10 20

3.5

4

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

4.5

30 50 60 90

3

1

40 70 80

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= Int. 2 V

Input Code = Full Scale (Both DACs)

– Supply Current – mAI

DD

TA – Free-Air Temperature – °C

1.4

1

0.4

0

0 10 20 30 40

– Power Down Supply Current – mA

2.2

2.4

POWER DOWN SUPPLY CURRENT

vs

TIME

2.6

50 60 70 80

2

1.8

1.6

1.2

0.8

0.6

0.2

t – Time – µs

I

DD

2.5

2

1.5

0.5
–40 –30–20 –10 0 10 20

3.5

4

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

4.5

30 50 60 90

3

1

40 70 80

Fast Mode

Slow Mode

VDD = 3 V
V

ref

= Int. 1 V

Input Code = Full Scale (Both DACs)

– Supply Current – mAI

DD

TA – Free-Air Temperature – °C

2.058

2.054

2.052

2.05
0 0.5 1 1.5 2 2.5 3

– Output Voltage – V

2.06

2.062

Source Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

2.064

3.5 4

2.056

V

O

Fast Mode

Slow Mode

VDD = 3 V
V

ref

= Int. 1 V

Input Code = 4095

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

TYPICAL CHARACTERISTICS

Figure 2. Figure 3.

Figure 4. Figure 5.

7

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4.122

4.12

4.116

4.114
0 0.5 1 1.5 2 2.5 3

4.124

4.126

4.128

3.5 4

4.118

– Output Voltage – V

Source Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

V

O

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= Int. 2 V

Input Code = 4095

1.5

1

0.5

0

0 0.5 1 1.5 2 2.5 3

2

2.5

3

3.5 4

– Output Voltage – V

Sink Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

V

O

Fast Mode

Slow Mode

VDD = 3 V
V

ref

= Int. 1 V

Input Code = 0

3.5

2

1

0

0 0.5 1 1.5 2 2.5 3

4

4.5

5

3.5 4

3

2.5

1.5

0.5

– Output Voltage – V

Sink Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

V

O

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= Int. 2 V

Input Code = 0

–40
–50

–80

–100

100 1000

THD+N – Total Harmonic Distortion and Noise – dB

–20

–10

f – Frequency – Hz

TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

0

10000 100000

–30

–60

–70

–90

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

TYPICAL CHARACTERISTICS (continued)

8

Figure 6. Figure 7.

Figure 8. Figure 9.

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–40
–50

–80

–100

100 1000

THD – Total Harmonic Distortion – dB

–20

–10

f – Frequency – Hz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

10000 100000

–30

–60

–70

–90

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

–1

–4

0 1024 2048

2

3

INTEGRAL NONLINEARITY ERROR

4

3072 4096

INL – Integral Nonlinearity Error – LSB

Digital Code

1
0

–2
–3

–0.4

–1

0 1024 2048

0.6

0.8

DIFFERENTIAL NONLINEARITY ERROR

1

3072 4096

0.4

0.2
0

–0.2

–0.6
–0.8

Digital Code

TYPICAL CHARACTERISTICS (continued)

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

Figure 10.

Figure 11.

Figure 12.

9

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2 REF

CODE

0x1000

[V]

TMS320

DSP

FSX

CLKX

DX

TLV5638

SCLK

DIN

CS

SPI

I/O

SCK

MOSI

TLV5638

SCLK

DIN

CS

Microwire

I/O

SK

SO

TLV5638

SCLK

DIN

CS

f

sclkmax



1

t

whmin

 t

wlmin

 20 MHz

f

updatemax



1

16t

whmin

 t

wlmin



 1.25 MHz

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

APPLICATION INFORMATION

GENERAL FUNCTION

The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).

SERIAL INTERFACE

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI™, and Microwire™.

Figure 13. Three-Wire Interface

Notes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to FS. If the word width is 8 bits (SPI™ and Microwire™), two write operations
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control
register are updated automatically on the 16

th

positive clock edge.

SERIAL CLOCK FREQUENCY AND UPDATE RATE

The maximum serial clock frequency is given by:

The maximum update rate is:

Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5638 has to be considered, too.

10

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SLAS225C – JUNE 1999 – REVISED JANUARY 2004

APPLICATION INFORMATION (continued)
DATA FORMAT

The 16-bit data word for the TLV5638 consists of two parts:

• Program bits (D15..D12)

• New data (D11..D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWR R0 12 Data bits

SPD: Speed control bit 1 → fast mode 0 → slow mode
PWR: Power control bit 1 → power down 0 → normal operation

The following table lists the possible combination of the register select bits:

REGISTERED SELECT BITS

R1 R0 REGISTER

0 0 Write data to DAC B and BUFFER
0 1 Write data to BUFFER
1 0 Write data to DAC A and update DAC B with BUFFER content
1 1 Write data to control register

TLV5638

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:

DATA BITS: DAC A, DAC B and BUFFER

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

New DAC Value

If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:

DATA BITS: CONTROL

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X X X REF1 REF0

REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.

REFERENCE BITS

REF1 REF0 REFERENCE

0 0 External
0 1 1.024 V
1 0 2.048 V
1 1 External

CAUTION:

If external reference voltage is applied to the REF pin, external reference MUST
be selected.

11

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TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

EXAMPLES OF OPERATION:

1. Set DAC A output, select fast mode, select internal reference at 2.048 V:
a. Set reference voltage to 2.048 V (CONTROL register)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0

b. Write new DAC A value and update DAC A output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 New DAC A output value

The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the

CONTROL register again.

2. Set DAC B output, select fast mode, select external reference:
a. Select external reference (CONTROL register):

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

b. Write new DAC B value to BUFFER and update DAC B output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 New BUFFER content and DAC B output value

The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the

CONTROL register again.

3. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference
at 1.024 V:

a. Set reference voltage to 1.024 V (CONTROL register)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1

b. Write data for DAC B to BUFFER:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 New DAC B value

c. Write new DAC A value and update DAC A and B simultaneously:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 New DAC A value

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the

CONTROL register again.

1. Set power-down mode:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X 1 X X X X X X X X X X X X X

#IMPLIED. X = Don't care

12

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DAC Code

Output

Voltage

0 V

Negative

Offset

TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 14 .

Figure 14. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full-scale code and the lowest code that produces a positive output voltage.

13

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TLV5638

SLAS225C – JUNE 1999 – REVISED JANUARY 2004

DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY

Integral Nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.

Differential Nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.

Zero-Scale Error (E

)

ZS

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

Gain Error (E

)

G

Gain error is the error in slope of the DAC transfer function.

Total Harmonic Distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The
value for THD is expressed in decibels.

Signal-to-Noise Ratio + Distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of
the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

14

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

8

1

5

4

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.023 (0,58)

0.015 (0,38)

0.280 (7,11)

0.245 (6,22)

0.310 (7,87)

0.290 (7,37)

0.200 (5,08) MAX
Seating Plane

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

4040107/C 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

21

22

23

24

25

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342
(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358
(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307
(7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850
(21,6)

1.047
(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358
(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858
(21,8)

1.063
(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

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