Datasheet TLV5626 Datasheet (TEXAS INSTRUMENTS)

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TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

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DIN

SCLK

D PACKAGE

(TOP VIEW)

1 2 3 4

8 7 6 5

OUTB REF AGND

features

Dual 8-Bit Voltage Output DAC

Programmable Internal Reference

Programmable Settling Time:

0.8 µs in Fast Mode ,

2.8 µs in Slow Mode

Compatible With TMS320 and SPI Serial

OUTA

Ports

Differential Nonlinearity <0.1 LSB Typ

Monotonic Over Temperature

applications

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

description

The TL V5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 2 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5626 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

0°C to 70°C TLV5626CD

–40°C to 85°C TLV5626ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SOIC

(D)

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TLV5626

I/O/P

DESCRIPTION

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

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functional block diagram

DIN

SCLK

Power-On

Reset

Serial

Interface

and

Control

Power

and Speed

Control

2-Bit

Control

Latch

Buffer

PGA With

Output Enable

Voltage

Bandgap

8 8

8-Bit

DAC A

Latch

8-Bit

DAC B

Latch

REF AGND V

OUTA

OUTB

Terminal Functions

TERMINAL

NAME NO.

AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUTA 4 I DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input V

8 P Positive power supply

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Suppl

oltage, V

Operating free-air temperature, T

°C

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5626C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5626I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

y v

Power on threshold voltage, POR 0.55 2 V High-level digital input voltage, V Low-level digital input voltage, V Reference voltage, V Reference voltage, V Load resistance, R Load capacitance, C Clock frequency, f

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ (VDD – 0.4 V)/2 causes clipping of the transfer function. The output buffer of the

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

ref

CLK

internal reference must be disabled, if an external reference is used.

VDD = 5 V 4.5 5 5.5 V VDD = 3 V 2.7 3 3.3 V

VDD = 2.7 V to 5.5 V 2 V VDD = 2.7 V to 5.5 V 0.8 V

2 kΩ

100 pF

20 MHz TLV5626C 0 70 TLV5626I –40 85

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TLV5626

IDDPower supply current

All inputs

AGND or V

PSRR

Power supply rejection ratio

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electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

VDD = 5 V, Int. ref.

VDD = 3 V, Int. ref.

VDD = 5 V, Ext. ref.

VDD = 3 V, Ext. ref.

No load,

Power-down supply current 1 µA

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

DAC latch = 0x800

Zero scale, See Note 2 –65 Full scale, See Note 3 –65

Fast 4.2 7 mA Slow 2 3.6 mA

Fast 3.7 6.3 mA Slow 1.7 3.0 mA

Fast 3.8 6.3 mA Slow 1.7 3.0 mA

Fast 3.4 5.7 mA Slow 1.4 2.6 mA

UNIT

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits INL Integral nonlinearity, end point adjusted See Note 4 ±0.4 ±1 LSB DNL Differential nonlinearity See Note 5 ±0.1 ±0.5 LSB E

EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C E

EG T

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

Zero-scale error (offset error at zero scale) See Note 6 ±24 mV

Gain error See Note 8 ±0.6

Gain error temperature coefficient See Note 9 10 ppm/°C

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

8. Gain error is the deviation from the ideal output (2V

9. Gain temperature coefficient is given by: EGTC = [EG(T

– 1 LSB) with an output load of 10 k excluding the effects of the zero-error .

ref

max

) – EG (T

max

min

) – EZS(T

)]/V

× 106/(T

ref

min

)]/V

max

× 106/(T

ref

– T

min

– T

min

max

% full

scale V

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOOutput voltage RL = 10 kΩ 0 VDD–0.4 V

Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kΩ vs 10 k ±0.25

% full

scale V

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Reference input bandwidth

REF

024 V dc

Output settling time, full scale

Output settling time, code to code

Slew rate

V/µs

out

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electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ref(OUTL)

ref(OUTH)

ref(source)

ref(sink)

PSRR Power supply rejection ratio –65 dB

reference pin configured as input (REF)

VIInput voltage 0 V RIInput resistance 10 MΩ CIInput capacitance 5 pF

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

Low reference voltage 1.003 1.024 1.045 V High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V Output source current 1 mA Output sink current –1 mA Load capacitance 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD–1.5

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

= 0.2

+ 1.

Fast 1.3 MHz Slow 525 kHz

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I I C

High-level digital input current VI = V

Low-level digital input current VI = 0 V –1 µA

Input capacitance 8 pF

1 µA

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

s(FS)

s(CC)

SNR Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range 50 62

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

Glitch energy

of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

= 10 kΩ,C

See Note 11 R

= 10 kΩ,C

See Note 12 R

= 10 kΩ,C

See Note 13 DIN = 0 to 1, f

= V

= 480 kSPS, f

RL = 10 kΩ,CL = 100 pF

= 100 pF,

= 100 kHz,

CLK

= 1 kHz,

Fast 0.8 2.4 Slow 2.8 5.5 Fast 0.4 1.2 Slow 0.8 1.6 Fast 12 Slow 1.8

5 nV–S

48 47

–50 –48

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digital input timing requirements

su(CS–CK)

su(C16-CS)

su(D)

h(D)

Setup time, CS low before first negative SCLK edge 10 ns Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns SCLK pulse width high 25 ns SCLK pulse width low 25 ns Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edge 5 ns

PARAMETER MEASUREMENT INFORMATION

MIN NOM MAX UNIT

SCLK

DIN

su(D)th(D)

su(CS-CK)

2 3 4 5 15 16

D15 D14 D13 D12 D1 D0 XX

su(C16-CS)

Figure 1. Timing Diagram

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TYPICAL CHARACTERISTICS

SUPPLY CURRENT

FREE-AIR TEMPERATURE

4.5

Fast Mode

3.5

2.5

– Supply Current – mA

1.5

0.5 –40–30 –20 –10 0 10 20

TA – Free-Air Temperature – °C

Slow Mode

VDD = 5 V V

= Int. 2 V

ref

Input Code = 1023 (Both DACs)

Figure 2

POWER DOWN SUPPLY CURRENT

TIME

2.6

2.4

2.2 2

1.8

1.6

1.4

1.2 1

0.8

0.6

– Power Down Supply Current – mA

0.4

0.2 0

010203040

t – Time – µs

Figure 4

30 40 50 90

60 70 80

50 60 70 80

SUPPLY CURRENT

FREE-AIR TEMPERATURE

4.5

3.5

2.5

– Supply Current – mA

1.5

0.5 –40–30 –20 –10 0 10 20

Fast Mode

VDD = 3 V V

ref

Input Code = 1023 (Both DACs)

TA – Free-Air Temperature – °C

Figure 3

OUTPUT VOLTAGE

LOAD CURRENT

2.064

2.062

2.06

2.058

2.056

– Output Voltage – V

2.054

2.052

2.05 0 0.5 1 1.5 2 2.5 3

Fast Mode

Slow Mode

Source Current – mA

Figure 5

Slow Mode

= Int. 1 V

30 40 50 90

60 70 80

VDD = 3 V V

= Int. 1 V

ref

Input Code = 4095

3.5 4

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TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

LOAD CURRENT

4.128

4.126

4.124

4.122

4.12

– Output Voltage – V

4.118

4.116

4.114 0 0.5 1 1.5 2 2.5 3

Fast Mode

Slow Mode

Source Current – mA

Figure 6

OUTPUT VOLTAGE

LOAD CURRENT

VDD = 5 V V

4.5 4

= Int. 2 V

ref

Input Code = 0

VDD = 5 V V

ref

Input Code = 4095

= Int. 2 V

3.5 4

OUTPUT VOLTAGE

LOAD CURRENT

VDD = 3 V V

= Int. 1 V

ref

Input Code = 0

2.5

1.5

– Output Voltage – V

0.5

0 0.5 1 1.5 2 2.5 3

Fast Mode

Slow Mode

Sink Current – mA

Figure 7

TOTAL HARMONIC DISTORTION AND NOISE

FREQUENCY

–10 –20

VDD = 5 V V

= 1 V dc + 1 V p/p Sinewave

ref

Output Full Scale

3.5 4

– Output Voltage – V

3.5

Fast Mode

2.5 2

1.5

0.5 0

0 0.5 1 1.5 2 2.5 3

Sink Current – mA

Figure 8

–30

–40 –50

–60

–70 –80

Slow Mode

3.5 4

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–90

–100

THD+N – Total Harmonic Distortion and Noise – dB

100 1000

f – Frequency – Hz

Figure 9

Slow Mode

Fast Mode

10000 10000

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TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

FREQUENCY

–10 –20

–30

–40 –50

–60

VDD = 5 V V

= 1 V dc + 1 V p/p Sinewave

ref

Output Full Scale

–70 –80

THD – Total Harmonic Distortion – dB

–90

–100

100 1000

0.20

0.15

0.10

0.05 –0.00 –0.05 –0.10 –0.15

–0.2

DNL – Differential Nonlinearity – LSB

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

Slow Mode

Fast Mode

10000 100000

f – Frequency – Hz

Figure 10

DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

Digital Output Code

Figure 11

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TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

1.0

0.8

0.6

0.4

0.2 –0.0 –0.2 –0.4 –0.6 –0.8

INL – Integral Nonlinearity – LSB

–1.0

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

Digital Output Code

Figure 12

APPLICATION INFORMATION

general function

The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to 0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI, and Microwire.

TMS320

DSP

CLKX

FSX

TLV5626 CS DIN SCLK

SPI

I/O

MOSI

SCK

TLV5626 CS DIN SCLK

Figure 13. Three-Wire Interface

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Microwire

I/O SO SK

TLV5626 CS DIN SCLK

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APPLICATION INFORMATION

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TL V5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16

serial clock frequency and update rate

The maximum serial clock frequency is given by:

positive clock edge.

TLV5626

sclkmax

whmin

)

wlmin

20 MHz

The maximum update rate is:

whmin

)

wlmin

1.25 MHz

updatemax

16ǒt

The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TL V5626 has to be considered, too.

data format

The 16-bit data word for the TLV5626 consists of two parts:

Program bits (D15..D12)

New data (D11..D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWR R0 12 Data bits

SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation

The following table lists the possible combination of the register select bits:

R1 R0 REGISTER

0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value:

data bits: DAC A, DAC B and BUFFER

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

New DAC Value 0 0 0 0

If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:

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APPLICATION INFORMATION

data bits: CONTROL

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X X X REF1 REF0

X: don’t care

REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.

reference bits

REF1 REF0 REFERENCE

0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External

CAUTION:

If external reference voltage is applied to the REF pin, external reference MUST be selected.

examples of operation:

Set DAC A output, select fast mode, select internal reference at 2.048 V:

1. Set reference voltage to 2.048 V (CONTROL register):

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0

2. Write new DAC A value and update DAC A output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 New DAC A output value 0 0 0 0

The DAC A output is updated on the rising clock edge after D0 is sampled. T o output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

Set DAC B output, select fast mode, select external reference:

3. Select external reference (CONTROL register):

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

4. Write new DAC B value to BUFFER and update DAC B output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 New BUFFER content and DAC B output value 0 0 0 0

X = Don’t care

The DAC A output is updated on the rising clock edge after D0 is sampled. T o output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

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APPLICATION INFORMATION

examples of operation: (continued)

Set DAC A value, set DAC B value, update both simultaneously , select slow mode, select internal reference at 1.024 V:

1. Set reference voltage to 1.024 V (CONTROL register):

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1

2. Write data for DAC B to BUFFER:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 New DAC B value 0 0 0 0

X = Don’t care

3. Write new DAC A value and update DAC A and B simultaneously:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 New DAC A value 0 0 0 0

X = Don’t care

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.

Set power-down mode:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X 1 X X X X X X X X X X X X X

X = Don’t care

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.

Output

Voltage

0 V

Negative

Offset

DAC Code

Figure 14. Effect of Negative Offset (single supply)

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APPLICATION INFORMATION

This offset error , not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (EZS)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 15

TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

0.069 (1,75) MAX

0.020 (0,51)

0.014 (0,35) 8

0.010 (0,25)

0.004 (0,10)

DIM

0.157 (4,00)

0.150 (3,81)

PINS **

0.010 (0,25)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

0.008 (0,20) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

Page 16

IMPORTANT NOTICE

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safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Datasheet TLV5626 Datasheet (TEXAS INSTRUMENTS)

Specifications and Main Features

Frequently Asked Questions

User Manual