Datasheet TLV5625CD, TLV5625IDR, TLV5625ID, TLV5625CDR Datasheet (Texas Instruments)

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

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features

D

Dual 8-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time
– 2.5 µs in Fast Mode
– 12 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity <0.2 LSB Max

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5625 is a dual 8-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface is compatible with TMS320, SPI,
QSPI, and Microwire serial ports. It is
programmed with a 16-bit serial string containing
4 control and 8 data bits.

The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC
allows the designer to optimize speed versus power dissipation.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

0°C to 70°C TLV5625CD

–40°C to 85°C TLV5625ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW

Copyright  2000, Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

OUTA

V

DD

OUTB
REF
AGND

D PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

TLV5625

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functional block diagram

Serial

Interface

and

Control

8-Bit

DAC B

Latch

SCLK

DIN

CS

OUTA

Power-On

Reset

x2

8

Power and

Speed Control

2

8-Bit

DAC A

Latch

8

REF AGND V

DD

8 8

OUTB

x2

Buffer

8

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs.
DIN 1 I Digital serial data input
OUTA 4 O DAC A analog voltage output
OUTB 7 O DAC B analog voltage output
REF 6 I Analog reference voltage input
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5625C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5625I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5

V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3
Power on reset, POR 0.55 2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5625C 0 70

°

Operating free-air temperature, T

A

TLV5625I –40 85

°C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function.

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electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

pp

No load, All inputs = AGND or VDD,

Fast 1.8 2.3

I

Power su ly current

DD

mA

DD

y

DAC latch

= 0x

800

Slow

0.8

1

Power-down supply current 1 3 µA

pp

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
INL Integral nonlinearity See Note 4 ±0.3 ±0.5 LSB
DNL Differential nonlinearity See Note 5 ±0.07 ±0.2 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±12 mV
EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.5

% full

scale V

EG TCGain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.

5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale error temperature coef ficient is given by: EZS TC = [EZS (T

max) – EZS

(T

min

)]/2V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ.

9. Gain temperature coefficient is given by: EG TC = [EG (T

max) – Eg

(T

min

)]/2V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage range RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V RL = 2 kΩ ±0.29 % FS

reference input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage range 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 1.3 MHz

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

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electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 2.5

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 12

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 1

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 3

SR

Slew rate

L

,

L

,

See Note 13

Slow 0.5

V/µs

Glitch energy

DIN = 0 to 1, FCLK = 100 kHz,
CS

= V

DD

5 nV–s

SNR Signal-to-noise ratio 52 54
SINAD Signal-to-noise + distortion

f

= 102 kSPS, f

= 1 kHz,

48 49

THD Total harmonic distortion

s

,

out

,

RL = 10 kΩ,CL = 100 pF

–50 –48

dB

SFDR Spurious free dynamic range 48 50

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.

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digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–CK)

Setup time, CS low before first negative SCLK edge 10 ns

t

su(C16-CS)

Setup time, 16th negative SCLK edge before CS rising edge 10 ns

t

wH

SCLK pulse width high 25 ns

t

wL

SCLK pulse width low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 10 ns

t

h(D)

Hold time, data held valid after SCLK falling edge 5 ns

timing requirements

t

wL

SCLK

CS

DIN

D15 D14 D13 D12 D1 D0 XX

1

X

2 3 4 5 15 16

X

t

wH

t

su(D)th(D)

t

su(CS-CK)

t

su(C16-CS)

Figure 1. Timing Diagram

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TYPICAL CHARACTERISTICS

Figure 2

2.046

2.044

2.040

2.038

2.036

2.050

2.042

0.00 –0.01–0.02–0.05–0.10–0.20–0.51

2.048

Load Current - mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

–1.02–2.05

– Output Voltage – V
V

O

VDD=3 V
V

REF

=1 V

Full scale

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

Figure 3

4.095

4.090

4.080

4.075

4.070

4.105

4.085

4.100

OUTPUT VOLTAGE

vs

LOAD CURRENT

– Output Voltage – V
V

O

VDD=5 V
V

REF

=2 V

Full scale

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

0.00 –0.02–0.04–0.10–0.20–0.41–1.02
Load Current - mA

–2.05–4.10

Figure 4

0.16

0.14

0.10

0.08

0.06

0.20

0.12

0.00 0.01 0.02 0.05 0.10 0.20 0.51

0.18

Load Current - mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

1.02 2.05

– Output Voltage – V
V

O

3 V Slow Mode, SINK

3 V Fast Mode, SINK

0.04

0.02

0.00

VDD=3 V
V

REF

=1 V

Zero scale

Figure 5

0.25

0.20

0.10

0.05

0.00

0.35

0.15

0.00 0.02 0.04 0.10 0.20 0.41 1.02

0.30

Load Current - mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

2.05 4.09

– Output Voltage – V
V

O

5 V Slow Mode, SINK

5 V Fast Mode, SINK

VDD=5 V
V

REF

=2 V

Zero scale

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TYPICAL CHARACTERISTICS

Figure 6

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

–40.00–20.00 0.00 20.00 40.00 60.00 80.00100.00120.00

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

TA - Free-Air Temperature - C

VDD=3 V
V

REF

=1 V

Full scale

Fast Mode

Slow Mode

I

DD

– Supply Current – mA

Figure 7

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

–40.00–20.00 0.00 20.00 40.00 60.00 80.00100.00120.0

0

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

TA - Free-Air Temperature - C

VDD=5 V
V

REF

=2 V

Full scale

Fast Mode

Slow Mode

I

DD

– Supply Current – mA

Figure 8

–90.00

–80.00

–70.00

–60.00

–50.00

–40.00

–30.00

–20.00

–10.00

0.00

1 10 100

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

f - Frequency - kHz

V

REF

= 1 V + 1 V

P/P

Sinewave,

Output Full Scale

3 V Fast Mode

5 V Fast Mode

THD

-

T

o

t

a

l

H

armon

i

c

Di

s

t

or

ti

on -

dB

Figure 9

–90.00

–80.00

–70.00

–60.00

–50.00

–40.00

–30.00

–20.00

–10.00

0.00

1 10 100

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

V

REF

= 1 V + 1 V

P/P

Sinewave,

Output Full Scale

5 V Slow Mode

THD - Total Harmonic Distortion - dB

3 V Slow Mode

f - Frequency - kHz

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TYPICAL CHARACTERISTICS

Figure 10

–0.10

–0.08

–0.06

–0.04

–0.02

0.00

0.02

0.04

0.06

0.08

0.10

0 255

DNL – Differential Nonlinearity – LSB

Digital Output Code

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

12864 192

Figure 11

–0.5

–0.4

–0.3

–0.2

–0.1

–0.0

0.1

0.2

0.3

0.4

0.5

0 255

INL – Integral Nonlinearity – LSB

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

64 128 192

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APPLICATION INFORMATION

general function

The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by the reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0. A power-on
reset initially puts the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS

rises, the content of the shift register is moved to the

target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI, and Microwire.

TMS320

DSP

FSX

CLKX

DX

TLV5625

SCLK

DIN

CS

SPI

I/O

SCK

MOSI

TLV5625

SCLK

DIN

CS

Microwire

I/O

SK

SO

TLV5625

SCLK

DIN

CS

Figure 12. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS

. If the word width is 8 bits (SPI and Microwire) two write operations
must be performed to program the TLV5625. After the write operation(s), the holding registers or the control
register are updated automatically on the 16th positive clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

f

sclkmax

+

1

t

whmin

)

t

wlmin

+

20 MHz

The maximum update rate is:

f

updatemax

+

1

16ǒt

whmin

)

t

wlmin

Ǔ

+

1.25 MHz

Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5625 should also be considered.

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APPLICATION INFORMATION

data format

The 16-bit data word for the TLV5625 consists of two parts:

D

Program bits (D15..D12)

D

New data (D11..D4)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWR R0 MSB 8 Data bits LSB 0 0 0 0

SPD: Speed control bit 1 → fast mode 0 → slow mode
PWR: Power control bit 1 → power down 0 → normal operation
On power up, SPD and PWD are reset to 0 (slow mode and normal operation)

The following table lists all possible combination of register-select bits:

register-select bits

R1 R0 REGISTER

0 0 Write data to DAC B and BUFFER
0 1 Write data to BUFFER
1 0 Write data to DAC A and update DAC B with BUFFER content
1 1 Reserved

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:

examples of operation

D

Set DAC A output, select fast mode:
Write new DAC A value and update DAC A output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 New DAC A output value 0 0 0 0

The DAC A output is updated on the rising clock edge after D0 is sampled.

D

Set DAC B output, select fast mode:
Write new DAC B value to BUFFER and update DAC B output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 New BUFFER content and DAC B output value 0 0 0 0

The DAC A output is updated on the rising clock edge after D0 is sampled.

D

Set DAC A value, set DAC B value, update both simultaneously, select slow mode:

1. Write data for DAC B to BUFFER:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 New DAC B value 0 0 0 0

2. Write new DAC A value and update DAC A and B simultaneously:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 New DAC A value 0 0 0 0

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APPLICATION INFORMATION

examples of operation (continued)

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.

D

Set power-down mode:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X 1 X X X X X X X X X X X X X

X = Don’t care

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 13. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error , produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.

power-supply bypassing and ground management

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between V

DD

and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.

Figure 14 shows the ground plane layout and bypassing technique.

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APPLICATION INFORMATION

0.1 µF

Analog Ground Plane

1
2
3
4

8
7
6
5

Figure 14. Power-Supply Bypassing

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

ZS

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E

G

)

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.

PRODUCT PREVIEW

TLV5625

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN

SLAS233A – JULY 1999 – REVISED MARCH 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

PRODUCT PREVIEW

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