Datasheet TLV5613IPWR, TLV5613IPW, TLV5613IDW, TLV5613CPWR, TLV5613CPW Datasheet (Texas Instruments)

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TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12-Bit Voltage Output DAC

Single Supply 2.7-V to 5.5-V Operation

Separate Analog and Digital Supplies

±0.4 LSB Differential Nonlinearity (DNL), ±1.5 LSB Integral Nonlinearity (INL)

Programmable Settling Time vs Power Consumption:

1 µs/4.2 mW in Fast Mode,

3.5 µs/1.2 mW in Slow Mode

8-Bit µController Compatible Interface (8+4 Bit)

Power-Down Mode (50 nW)

Rail-to-Rail Output Buffer

Synchronous or Asynchronous Update

Monotonic Over Temperature

applications

Digital Servo Control Loops

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Control

Speech Synthesis

Machine and Motion Control Devices

Mass Storage Devices

description

The TLV5613 is a 12-bit voltage output digital-to-analog converter (DAC) with a 8-bit microcontroller compatible parallel interface. The 8 LSBs, the 4 MSBs and 3 control bits are written using three different addresses. Developed for a wide range of supply voltages, the TLV5613 can be operated from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class A (slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by the control bits within the 16-bit data word.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20 pin SOIC in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(DW)

TSSOP

(PW)

0°C to 70°C TLV5613CDW TLV5613CPW

–40°C to 85°C TLV5613IDW TLV5613IPW

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

D2 D3 D4 D5 D6 D7 A1 A0

SPD

D1 D0 CS WE LDAC PWD GND OUT REF AV

DW OR PW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Page 2

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Interface

Control

4-Bit

DAC MSW

Holding

Latch

A(0–1)

OUT

Power-On

Reset

3-Bit

Control

Latch

Powerdown

and Speed

Control

12-Bit

DAC

Latch

12 12

REF

LDAC

8-Bit

DAC LSW

Holding

Latch

8 8

D(0–7)

PWD

SPD

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

11 Analog positive power supply A0 8 I Address input A1 7 I Address input CS 18 I Chip select. Digital input active low, used to enable/disable inputs DV

10 Digital positive power supply D0 (LSB) – D7 (MSB) 1–6, 19, 20 I Data input LDAC 16 I Load DAC. Digital input active low, used to load DAC output OUT 13 O DAC analog voltage output

PWD 15 I Power down. Digital input active low REF 12 I Analog reference voltage input SPD 9 I Speed select. Digital input GND 14 Ground

WE 17 I Write enable. Digital input active low, used to latch data

Page 3

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (DV

, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage difference, AVDD to DVDD – 2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to GND – 0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5613C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5613I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

5-V Supply 4.5 5 5.5

Suppl

y v

oltage, V

3-V Supply 2.7 3 3.3

Supply voltage difference, ∆VDD = AVDD – DV

–2.8 0 2.8 V Power on reset, POR 0.55 2 V High-level digital input voltage, V

DVDD = 2.7 V to 5.5 V 2 V

Low-level digital input voltage, V

DVDD = 2.7 V to 5.5 V 0.8 V 5-V Supply (see Note 1) GND 2.048 AVDD–1.5

Reference voltage, V

ref

REFIN terminal

3-V Supply (see Note 1) GND 1.024 AVDD–1.5

Load resistance, R

2 kΩ

Load capacitance, C

100 pF

TLV5613C 0 70 °C

Operating free-air temperature, T

TLV5613I –40 85 °C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD – 0.4)/2 causes clipping of the transfer function.

Page 4

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

Fast 1.6 3 mA

No load,

= 5

Slow 0.5 1.3 mA

IDDPower supply current

All inputs

GND or DV

DAC latch = 0x800

Fast 1.4 2.7 mA

= 3

Slow 0.4 1.1 mA

Power down supply current See Figure 14 0.01 10 µA

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:

PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax]

3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution V

ref(REFIN)

= 2.048 V , 1.024 V 12 bits

Integral nonlinearity (INL), end point adjusted V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 4 ±1.5 ±4 LSB

Differential nonlinearity (DNL) V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 5 ±0.4 ±1 LSB

Zero-scale error (offset error at zero scale) V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 6 ±3 ±20 mV

Zero-scale-error temperature coefficient V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 7 3 ppm/°C

Gain error V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 8 ±0.25 ±0.5

% of FS

voltage

Gain error temperature coefficient V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 9 1 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1

LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coef ficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

8. Gain error is the deviation from the ideal output (V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage RL = 10 kΩ 0 AVDD–0.4 V Output load regulation accuracy

O(OUT)

= 4.096 V , RL = 2 kΩ,

0.1 0.29

% of FS

voltage

AVDD = 5 V –100

OSC(

source

)

Out ut short circuit source current

O(OUT)

= 0 V,

in ut all 1s

AVDD = 3 V –25

AVDD = 5 V –10

OSC(sink)

Out ut short circuit sink current

100 Ω, in ut all 1s

AVDD = 3 V –10

Page 5

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ref

Input voltage reference See Note 10 0 AVDD–1.5 V RiInput resistance 10 MΩ CiInput capacitance 5 pF

Fast mode 1.6 MHz

Reference in ut bandwidth

REF

= 0.2

+ 1.024 V dc

Slow mode 1 MHz

Reference feed through

REF = 1 Vpp at 1 kHz + 1.024 V dc, See Note 10

–60 dB

NOTES: 10. Referen ce feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level digital input current VI = DV

1 µA

Low-level digital input current VI = 0 V –1 µA

Input capacitance 8 pF

operating characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 10 kΩ,

See Note 11

Fast 1 3

s(FS)

Output settling time, full scale

CL = 100 pF,

Slow 3.5 7

= 10 kΩ,

See Note 12

Fast 0.5 1.5

s(CC)

Output settling time, code-to-code

CL = 100 pF,

Slow 1 2

= 10 kΩ, See Note 13

Fast 8

Slew rate

CL = 100 pF,

Slow 1.5

V/µs

Glitch energy Code-to-code transition 1 nV–s S/N Signal-to-noise 65 78 S/(N+D) Signal-to-noise + distortion

= 480 KSPS, f

= 1 kHz,

58 69

THD T otal harmonic distortion

out

RL = 10 k, CL = 100 pF

–68 –60

Spurious free dynamic range 60 72

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0x3FF or 0x3FF to 0x020.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full scale.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

Page 6

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

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timing requirements

digital inputs

MIN NOM MAX UNIT

su(D)

Setup time, data ready before positive WE edge 9 ns

su(CS-WE)

Setup time, CS low before positive WE edge 13 ns

su(A)

Setup time, address bits A0, A1 17 ns

h(D)

Hold time, data held after positive WE edge 0 ns

tsu(WE-LD) Setup time, positive WE edge before LDAC low 0 ns tw(WE) Pulse duration, WE high 10 ns tw(LD) Pulse duration, LDAC low 10 µs

PARAMETER MEASUREMENT INFORMATION

X Data X

X Address X

su(D)

su(A)

h(D)

w(WE)

su(WE-LD)

w(LD)

su(CS-WE)

D(0–7)

A(0–1)

LDAC

Figure 1. Timing Diagram

Page 7

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

MSWX X LSW X

0XX1X

D(0–7)

A(0–1)

LDAC

Figure 2. Example of a Complete Write Cycle Using LDAC to Update the DAC

MSWX X LSW ControlXX

0XX13XX

D(0–7)

A(0–1)

LDAC

Figure 3. Example of a Complete Write Cycle Using the Control Word to Update the DAC

Page 8

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 4

2.5

1.5 100 K 10 K 1 K

– Output Voltage – V

3.5

MAXIMUM OUTPUT VOLTAGE

LOAD

4.5

100 10

AVDD = 5 V, V

ref

= 2 V,

Input Code = 4095

RL – Output Load – Ω

Figure 5

1.5

0.5 100 K 10 K 1 K

– Output Voltage – V

2.5

MAXIMUM OUTPUT VOLTAGE

LOAD

100 10

RL – Output Load – Ω

AVDD = 3 V, V

ref

= 1.2 V,

Input Code = 4095

Figure 6

–60

–80

–100

THD – Total Harmonic Distortion – dB

–40

–20

TOTAL HARMONIC DISTORTION

LOAD

100 K 10 K 1 K 100 10

AVDD = 5 V, V

ref

= 2 V,

Tone @ 1 kHz

RL – Output Load – Ω

Figure 7

–60

–80

–100

THD – Total Harmonic Distortion – dB

–40

–20

TOTAL HARMONIC DISTORTION

LOAD

100 K 10 K 1 K 100 10

AVDD = 3 V, V

ref

= 1.2 V,

Tone @ 1 kHz

RL – Output Load – Ω

Page 9

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

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TYPICAL CHARACTERISTICS

Figure 8

–30

–50

–70

–80

0 5 10 15 20

–20

–10

f – Frequency – kHz

25 30 35

TOTAL HARMONIC DISTORTION

FREQUENCY

–40

–60

THD – Total Harmonic Distortion – dB

AVDD = 5 V

Figure 9

–30

–50

–70

0 5 10 15 20

–20

–10

f – Frequency – kHz

25 30 35

TOTAL HARMONIC DISTORTION

FREQUENCY

–40

–60

THD – Total Harmonic Distortion – dB

AVDD = 3 V

Figure 10

0 5 10 15 20

SNRD – Signal-To-Noise Ratio + Distortion – dB

f – Frequency – kHz

SIGNAL-TO-NOISE + DISTORTION

FREQUENCY

25 30 35

AVDD = 5 V

Figure 11

0 5 10 15 20

SNRD – Signal-To-Noise Ratio + Distortion – dB

f – Frequency – kHz

SIGNAL-TO-NOISE + DISTORTION

FREQUENCY

25 30 35

AVDD = 3 V

Page 10

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

0.8

0.6

0.4

0.2 0

–0.2 –0.4 –0.6 –0.8

–1

DNL – Differential Nonlinearity – LSB

0 500 1000 1500 2000 2500 3000 3500 4000

Code

Figure 12. Differential Nonlinearity

1.5 1

0.5 0

–0.5

–1

–1.5

–2

0 500 1000 1500 2000 2500 3000 3500 4000

Code

INL – Integral Nonlinearity – LSB

–4

Figure 13. Integral Nonlinearity

Page 11

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

POWER DOWN SUPPLY CURRENT

TIME

0.00001

0.000001 100 300

t – Time – ms

0.01

0.001

0.0001

200 400 5000

0.1

600

– Supply Current – mA

Figure 14

APPLICATION INFORMATION

general function

The TLV5613 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, speed and power down control logic, a resistor string and a rail-to-rail output buffer . The output voltage (full scale determined by reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero).

parallel interface

The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register , depends on the address bits A1 and A0. LDAC

low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. Two more asynchronous inputs, SPD and PWD control the settling times and the power down mode:

SPD: Speed control 1 → fast mode 0 → slow mode PWD: Power control 1 → normal operation 0 → power down

Page 12

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

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APPLICATION INFORMATION

It is also possible to program the different modes (fast, slow , power down) and the DAC update latch using the control register. The following tables list the possible combination of the control signals and control bits.

PIN BIT

SPD SPD

MODE

0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast

PIN BIT

PWD PWD

POWER

0 0 Down 0 1 Down 1 0 Normal 1 1 Down

PIN BIT

LDAC RLDAC

LATCH

0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent

data format

The TL V5613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0.

ADDRESS BITS

A0 REGISTER

0 0 DAC LSW holding 0 1 DAC MSW holding 1 0 Reserved 1 1 Control

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X RLDAC PWD SPD

X: Don’t care SPD: Speed control bit 1 → fast mode 0 → slow mode PWD: Power control bit 1 → power down 0 → normal operation RLDAC: Load DAC latch 1 → latch transparent 0 → DAC latch controlled by LDAC

Page 13

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

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APPLICATION INFORMATION

layout considerations

T o achieve the best performance, it is recommended to have separate power planes for GND, A VDD, and DVDD. Figure 15 shows how to lay out the power planes for the TL V5613. As a general rule, digital and analog signals should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in parallel. The two positive power planes ( AV

and DVDD) should be connected together at one point with a

ferrite bead. A 100-nF ceramic low series inductance capacitor between DV

and GND and a 1-µF tantalum capacitor

between A V

and GND as close as possible to the supply pins are recommended for optimal performance.

Figure 15. TLV5613 Board Layout

linearity, offset, and gain error using single end supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 16.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 16. Effect of Negative Offset (Single Supply)

Page 14

TLV5613

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APPLICATION INFORMATION

This offset error, not the linearity error , produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage.

TLV5613 interfaced to an Intel MCS251 controller

The circuit in Figure 17 shows how to interface the TL V5613 to an Intel MCS251 microcontroller. The address bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. T o separate the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which is connected to a latch at port 0.

An address decoder is required to generate the chip select signal for the TLV5613. In this example, a simple 3-to-8 decoder (74AC138) is used for the interface as shown in Figure 17. The DAC is memory mapped at addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations (0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to generate the chip select signals for the entire system.

The data pins and the WE

pin of the TL V5613 can be connected directly to the multiplexed address and data

bus and the WR signal of the controller. LDAC is held high so that the output voltage is updated using the RLDAC bit in the control register. Hardware

power down mode is deactivated permanently by pulling PWD to DVDD.

P2 A(15–8)

P0 AD(7–0)

ALE

D(7–0)

B C

G2A

G2B

A1–0) D(7–0)

REF

REF191

A(15–0) AD(7–0)

CS(7–0)

74AC373

8xC251

74AC138

TLV5613

A15

A2 A3

Q(7–0)

Y(7–0)

G2A

SPD

PWD

LDAC

LE OE

OUT

Figure 17. TLV5613 Interfaced to an Intel MCS251 Controller

MCS is a registered trademark of Intel Corporation.

Page 15

TLV5613

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APPLICATION INFORMATION

software

In the following example, the code generates a waveform at 500 KSPS with 500 samples stored in a table within the program memory space of the microcontroller. The period of the waveform is 1 ms.

The waveform data is located in the program memory space from address 01000h to address 013E8h (2 × 500 = 1000 = 03E8h) beginning with the MSW of the first 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (the table is not shown in the code example).

The program consists of two parts:

A main routine, which is executed after reset and which initializes the timer and the interrupt system of the microcontroller.

An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC.

This example uses timer 0 in mode 3 (8-bit timer with auto reload). The clock of the timer is derived from the system clock and has a frequency of f

osc

/12. The timer overrun frequency f

tim

is given by the following equation:

tim

OSC

12(256–Reload)

and the reload value is given by Reload+256–

OSC

12 f

tim

To get a timer overrun frequency of 500 kHz at a system clock of 24 MHz, the reload value is:

Reload+256 –

12 0.5

256–4+252+0FCh

With this value, the timer generates an interrupt every 2 µs. The corresponding service routine T0_isr reads a sample from program memory and writes it to the DAC. First, it disables the update of the DAC output by clearing the RLDAC bit in the control register. Then it reads the MSW and the LSW from the waveform table and stores it in the MSW and LSW register of the TL V5613. The write cycle is completed by setting the RLDAC bit, which updates the DAC output. At the end of the interrupt service routine, the pointer to the waveform samples is increased and is checked to determine if it has reached the end of the table. If the pointer has reached the end of the table, the pointer is set to the start address of the table.

Page 16

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

;************************************************************************ ;* Title : Waveform generation with TLV5613 * ;* Version: 1.0 * ;* MCU : Intel MCS251, MCS51 * ;*  1998 Texas Instruments Inc. * ;************************************************************************

TABLE_START EQU 01000h ;start address of waveform data TABLE_END_H EQU 013h ;high byte – end address of waveform data TABLE_END_L EQU 0E8h ;low byte – end address of waveform data RELOAD EQU 0FCh ;timer reload value

ORG 00000h ;entry point JMP main ;jump to main program ORG 0000bh ;timer0 (T0) interrupt vector JMP T0_isr ;jump to T0 interrupt service routine

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;main: setup timer and interrupt, loop forever ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– main: CLR A

MOV A, IE0 ;disable all interrupts CLR TCON.4 ;stop T0 MOV A, #002h MOV TMOD, A ;set T0 to auto reload mode MOV A, #RELOAD MOV TH0, A ;set T0 reload value MOV TL0, A ;set T0 start value MOV P2, #080h ;set A15 of address bus to select DAC

MOV DPTR, #TABLE_START ;set data pointer to start of wave form data

SETB IE0.1 ;enable T0 interrupt SETB IE0.7 ;enable interrupts SETB TCON.4 ;start T0

idle_loop: SJMP idle_loop ;loop forever

Page 17

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;T0_isr: will be called on every timer interrupt. ;fetches a new 16–bit value from program memory space and writes it ;to the DAC. If end of table is reached, sets DPTR to table start addr. ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– T0_isr: MOV R0, #003h ;select DAC control register

MOV A, #001h ;RLDAC=0, PWD=0, SPD=1

;no DAC update, normal operation, fast mode

MOVX @R0, A ;write Accu to DAC control register

MOV R0, #001h ;select DAC MSW register CLR A MOVC A, @A+DPTR ;get MSW from code memory MOVX @R0, A ;write Accu to DAC MSW register

INC DPTR ;set DPTR to LSW data

MOV R0, #000h ;select DAC LSW register CLR A MOVC A, @A+DPTR ;get LSW from code memory MOVX @R0, A ;write Accu to DAC LSW register

MOV R0, #003h ;select DAC control register (to update DAC) MOV A, #005h ;DAC update, normal operation, fast mode MOVX @R0, A ;write Accu to DAC control register

INC DPTR ;set DPTR to next MSW

;test end of table MOV A, DPL CJNE A, #TABLE_END_L, T0_isr_end MOV A, DPH CJNE A, #TABLE_END_H, T0_isr_end MOV DPTR, #TABLE_START ;end of table reached –> start again

T0_isr_end: RETI

END

Page 18

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (EG)

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (SINAD)

Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency , including harmonics but excluding dc. The value for SINAD is expressed in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

T otal harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.

Page 19

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

4040000/D 02/98

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

Page 20

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/E 08/96

14 PIN SHOWN

Seating Plane

0,05 MIN

1,20 MAX

0,19

4,50 4,30

6,20

6,60

0,30

0,75 0,50

0,25

Gage Plane

0,15 NOM

0,65

0,10

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

4,90

5,10

6,60

6,404,90

5,10

7,70

7,90

9,60

9,80

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Page 21

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet TLV5613IPWR, TLV5613IPW, TLV5613IDW, TLV5613CPWR, TLV5613CPW Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual