Datasheet TLV5592EPWR Datasheet (Texas Instruments)

1
2
3
4
5
6
7

14
13
12
11
10

9
8

DV

DD

AV

DD

SIG

DC OFFSET

MID

GND

BW

CLK
TEST
TRACKINH
EXTS0
EXTS1
CON2
CON1

D PACKAGE

(TOP VIEW)

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Supports FLEXt Protocol Messaging Systems
With The TLV559X FLEX Decoder

D

3-Pole Butterworth Low-Pass Selectable
Dual-Bandwidth Audio Filter
– BW 1 = 1 kHz ±5% (– 3 dB)
– BW 2 = 2 kHz ±5% (– 3 dB)

D

Both Peak and Valley Detectors Available

D

2-Bit Analog-to-Digital Converter

D

Operating Temperature Range –20°C to 65°C

D

Four Modes of Operation:
– Fast Track
– Slow Track
– Hold
– Standby

D

1.8-V to 2.5-V Single Power Supply
Operation

applications

D

FLEX Protocol Numeric and
Alphanumeric Messaging Systems

D

One-Way or Two-Way

description

The T exas Instruments (TI) TLV5592 analog-to­digital converter (ADC) is a system level solution
to interface a 4-level baseband audio signal to a
digital decoder. The TLV5592 is a direct interface
to the TL V559X FLEX decoder . Designed primari­ly for messaging applications, the TL V5592 incor­porates signal conditioning, both peak and valley
detection along with analog-to-digital conversion.
A selectable third-order Butterworth filter with
cutoff frequencies of 1 kHz and 2 kHz is included.

The peak and valley detectors are implemented
with a unique design that does not require external
capacitors. Two 8-bit digital-to-analog converters
(DACs) are used in a feedback loop to
automatically adjust to the peak and valley levels.
The DAC outputs are used to set V

ref+

and V

ref–

for
the 2-bit ADC. Modes of operation include fast
track, slow track, hold, and standby . The standby
mode maximizes battery life. The TLV5592
operates on a single power supply from 1.8 V to

2.5 V.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(D)

–25°C to 65°C TLV5592ED

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FLEX is a trademark of Motorola Inc.
TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

_

+

8-Bit
DAC

CTR

2-Bit
ADC

fs = 1 kHz
Gain = 6 dB
nominal

3rd-Order Butterworth

3rd-Order Butterworth

Mode Control

and Enable

AV

DD

MID

Peak Detector

Valley Detector

REF +

REF –

EXTS0
EXTS1

DC OFFSET

SIG

CON1
CON2

BW

TRACKINH

11
10

5

2

4

3

8
9
7

12

Up/

Down

CLK

14

fs = 2 kHz
Gain = 6 dB
nominal

FILOUT

Σ

Σ

–

–

Decay

Counter

8-Bit
DAC

CTR

Up/

Down

Decay

Counter

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

NAME NO.

DESCRIPTION

AV

DD

2 I Analog supply voltage

BW 7 I Digital bandwidth select. A high level on BW selects the 2-kHz filter cutoff and a low level selects the 1-kHz

filter cutoff.
CON1 8 I Digital control 1 input. In conjunction with CON2, CON1 selects fast track, slow track, hold, or standby mode.
CON2 9 I Digital control 2 input. In conjunction with CON1, CON2 selects fast track, slow track, hold, or standby mode.
CLK 14 I Digital clock input. CLK input is a 50% duty cycle transistor-transistor logic (TTL)-level clock input with nominal

frequency of 38.4 kHz. The CLK input is edge sensitive in all non-test modes. For all test modes, the CLK input

is level sensitive.
DC OFFSET 4 I Analog dc offset correction input. The dc component of the audio signal should be applied to DC OFFSET.
DV

DD

1 I Digital supply voltage

EXTS0 11 O Digital output 0 of the ADC. Data bit 0 is the least significant bit (LSB).
EXTS1 10 O Digital output 1 of the ADC. Data bit 1 is the most significant bit (MSB).
GND 6 Return terminal for the IC current
MID 5 O Analog midpoint output. MID is a buffered output of AVDD/2.
SIG 3 I Analog audio signal input. An appropriate resistance capacitance (RC) low-pass filter (antialiasing filter)

should be connected to SIG.
TEST 13 I Digital test input enable. TEST should be connected to ground in normal operation.
TRACKINH 12 I Digital track inhibit logic input. A high level on TRACKINH disables the peak and valley detector counters; a

low level enables the peak and valley detector counters. The counters continue to decay at the decay rate while

TRACKINH is a low level.

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, AV

DD

, DVDD –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

–0.3 V to AV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, EXTS0, EXTS1 –0.3 V to DV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Offset input voltage, V

IO

–0.3 V to AV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

–20°C to 65° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, AVDD, DV

DD

1.8 2.5 V

Power supply ripple 0.001 V

pp

Input clock frequency, f

(CLK)

38.4 kHz
Input clock duty cycle 45 50 55 %
Voltage of fset applied at DC OFFSET, V

I(DC OFFSET)

(see Note 2) 0.25 VDD–0.25 V

Analog input voltage, V

I(pp)

(See Note 1 ) VDD = 2.0 V VIO–0.355 VIO+0.355 V

pp

High-level control input voltage, V

IH

VDD = 1.8 V to 2.4 V 0.2 DV

DD

V

Low-level control input voltage, V

IL

VDD = 1.8 V to 2.4 V 0.8 DV

DD

V

Operating free-air temperature, T

A

–25 65 °C

NOTES: 1. The TLV5592 functions and operates down to 1.8 V. Full electrical specifications are ensured from 1.8 to 2.5 V, unless otherwise

noted.

2.

V

I(MAXńMIN)

+

VIO"

ǒ

V

DD

2

*

0.25

Ǔ

ń

(FILTER MAX GAIN)

This equation is valid for input sinusoids of less than 800 Hz.

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
AV

DD

= DV

DD

= 1.8 V to 2.5 V, f

(CLK)

= 38.4 kHz (unless otherwise noted)

power

PARAMETER TEST CONDITIONS MIN MAX UNIT

I

DD

Operating supply current Fast track, slow track, or hold mode 250 µA

I

DD(standby)

Standby supply current

V

I(DC OFFSET)

= 0.8 V, V

I(SIG)

= 0.8 V
For all digital inputs,
0 < VI < 0.5 V or VI > DVDD –0.5 V.

1 µA

digital

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage IOH = –100 µA DVDD –0.5 V

V

OL

Low-level output voltage IOL = 100 µA 0.5 V

I

IH

High-level input current VI = DV

DD

1 2.5 µA

I

IL

Low-level input current VI = 0 –1 –2.5 µA

C

i

Input capacitance, digital input 10 pF

analog

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Voltage accuracy at MID VDD = 2 V, C

L(MID)

= 220 nF 1.42 1.0 1.05 V

Z

i

Input impedance at SIG (see Note 3) f

(IN)

= 1.0 kHz 1 MΩ

Z

i(offset)

Input impedance at DC OFFSET (see Note 3) 1 3 MΩ

I

I(SIG)

Average input current into SIG GND < VI < AV

DD

100 nA

C

i

Input capacitance, all inputs 10 pF

NOTE 3: The input is capacitive and, therefore, is dynamic. Impedance specifications are based on f

(CLK)

= 38.4 kHz.

operating characteristics over recommended operating free-air temperature range,
AV

DD

=DVDD=3 V, f

(CLK)

= 38.4 kHz (unless otherwise noted)

peak-and-valley DACs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Step size, LSB VDD/255 V

E

FS

Full-scale error 1 LSB

E

ZS

Zero-code error 3 LSB
Voltage output drift Hold mode 0 mV/ms

E

D

Differential nonlinearity (DNL) error 1 LSB

low-pass filter

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

G Pass-band filter gain V

I(DC OFFSET)

= 0.8 V, VI = ± 125 mV 5.75 6 6.25 dB

1-kHz filter VI = ± 500 mV f

I(SIG)

= 1 kHz 2 3 4

Filter attenuation

2-kHz filter VI = ± 500 mV f

I(SIG)

= 2 kHz 2 3 4

dB

t

s

Stabilization time Off mode to hold mode (see Table 1) 5 ms

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Value A Value B

Based on Value A Based on Value B

CLK

TRACKINH

(external)

TRACKINH

(internal)

Peak/Valley

Counter Value

EXTS0, EXTS1

Outputs

(See Note A)

NOTE A: Internally the device recognizes input conditions on the falling edge of the clock only.

Figure 1. Timing Diagram

CLK

CON1

CON2

TRACKINH

NOTES: A. Internally the device recognizes input conditions on the falling edge of the clock only.

B. On the next falling edge of the clock with the input conditions shown, the TLV5592 tracks signal in fast track mode (peak DAC

counter counts down by 8 and up by 4) in time A.

C. On the next falling edge of the clock with the input conditions shown, the TLV5592 tracks signal in slow track mode (peak DAC

counter counts up by 2 and down by 1 every 40 clock cycles) in time B.

D. On the next falling edge of the clock with the input conditions shown, the TLV5592 holds previous peak and valley levels in time

C. For the 2-bit output, when TRACKINH = 1, EXTS0 and EXTS1 outputs respond in real time to the condition of SIG and DC
OFFSET as long as the CLK signal is present.

(See Note B) (See Note C) (See Note D)Time A Time B Time C

See Note A

Figure 2. Track and Lock Timing

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 3

–6

–15

–21

–30

31.25 62.5 125 250 500 1 k

G – Nominal Gain – dB

0

9

f – Frequency – Hz

NOMINAL FILTER GAIN

vs

FREQUENCY

15

2 k 4 k 8 k

12

6
3

–3

–9

–12

–18

–24
–27

1-kHz Filter Response

Figure 4

–6

–15

–21

–30

62.5 125 250 500 1 k

G – Nominal Gain – dB

0

9

f – Frequency – Hz

NOMINAL FILTER GAIN

vs

FREQUENCY

15

2 k 4 k 8 k

12

6
3

–3

–9

–12

–18

–24
–27

2-kHz Filter Response

16 k

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

analog input operation

As shown in the functional block diagram, the signal input is dc-coupled using a single input terminal, SIG. A
voltage equivalent to the nominal dc voltage of the signal input at SIG should be supplied on an additional
terminal, DC OFFSET . This allows the device to increase the signal to acceptable levels for threshold detection
without saturating against the supplies. The signal processed by the device is effectively the voltage difference
between the SIG and DC OFFSET terminals.

There is no antialiasing filter incorporated in the device. TI recommends that an external RC filter be added and
set at the appropriate cutoff (see Figure 5).

The maximum peak analog signal voltage that can be applied to the SIG input terminal is given by:

V

I(MAXńMIN)

+

VIO"

ǒ

V

DD

2

*

0.25

Ǔ

ń

(FILTER MAX GAIN)

where:

V

DD

ń

2+the nominal output voltage at the MID terminal

V

I(MINńMAX)

+

Analog input voltage (SIG)

VIO+

Input offset voltage (dc offset)

The main signal path consists of a third-order switched-capacitor Butterworth filter, with a bandwidth that is
switchable between 1 kHz and 2 kHz to remove the noise from the input signal. The peak and valley amplitudes
of the filter output signal are detected and subsequently used to convert the 4-level audio into 2-level digital
signals using three switched capacitor comparators.

digital operation

The peak and valley detection is performed by a mixed mode solution using an 8-bit DAC and an up/down
counter that has nonsymmetrical up and down count rates. V arious modes are included to force the peak and
valley circuits to slow track, fast track, or hold. An off mode is included that forces the device into a low-power
condition. The decay rate of the peak and valley circuits is controlled by independent counters.

The device is clocked with a 38.4-kHz square wave supplied externally . The attack and decay times of the peak
and valley circuits and the filter cutoff frequencies are directly related to this clock frequency. The decay timer
is gated by the track inhibit input, TRACKINH, which is reset to 1 after an attack occurs and reset to 40 after
a decay enable. The TRACKINH also prevents attack enable inputs from affecting the peak and valley counters.

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

digital control

Five digital inputs and the CLK input control the TL V5592. The five signals are BW , CON1, CON2, TRACKINH
and TEST. All digital control inputs are latched internally on the falling edge of the CLK input. The BW input
selects the cutoff frequency of the input signal third-order Butterworth switched-capacitor filter . The CON1 and
CON2 inputs determine when the TL V5592 is in tracking fast, tracking slow , hold, or low-power standby mode.
In test mode the CLK input is level sensitive, and in all other modes the CLK input is edge sensitive.

Table 1 lists the functions for the five control inputs.

Table 1. Control Inputs Function Table

BW

SWITCHED-CAPACITOR FILTER

(– 3 dB POINT)

Low 1-kHz filter cutoff
High 2-kHz filter cutoff

CON1 CON2 MODE

Low Low Low-power standby (off) mode

Low High Fast track mode
High Low Hold mode
High High Slow track mode

TRACKINH RESULT

Low Tracking enabled
High Tracking disabled

track inhibit

The TRACKINH input enables the counters to the peak and valley detector DACs. When enabled, the counters
adjust to create a DAC output that is the same as the filtered input signal peak and valley . The counters decay
at the fast or slow decay rates while the TRACKINH input is held low. The TRACKINH line should be connected
to SYMCLK terminal on the TLV559X decoder.

analog-to-digital conversion

The TLV5592 employs a 2-bit ADC to convert a 4-level analog signal to digital data. The digital output is
presented on EXTS0 and EXTS1 with EXTS0 being the LSB. The peak and valley DACs provide the maximum
and minimum voltages (V

ref+

and V

ref–

) to the ADC. The input to the 2-bit ADC is the output of the Butterworth

low-pass filter, FILOUT, as shown in the block diagram. The ADC transfer function is shown in Table 2.

Table 2. Filter Output Voltage Selection (see Note 4)

EXTS1 EXTS0 FILTER OUTPUT VOLTAGE (FILOUT)

Low Low FILOUT < ((peak – valley) x 50/256) + valley
High Low ((peak – valley) x 50/256) + valley < FILOUT < ((peak – valley) x 134/256) + valley
High High ((peak – valley) x 134/256) + valley < FILOUT < (( peak – valley) x 217/256) + valley

Low High FILOUT > ((peak – valley) x 217/256) + valley

NOTE 4: The constants 50/256, 134/256, and 217/256 have a± 5% tolerance.

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The thresholds for the ADC comparators are set by capacitor ratios in switched-capacitor comparators. For a
2-bit ADC, three comparators are used with thresholds set as shown in Table 3.

Table 3. Comparators and Associated Threshold Values (see Notes 4 and 5)

COMPARATOR VALUE UNIT

Lower threshold ((peak – valley) x 50/256) + valley V
Middle threshold ((peak – valley) x 134/256) + valley V
Upper threshold ((peak – valley) x 217/256) + valley V

NOTES: 4. The constants 50/256, 134/256, and 217/256 have a ± 5% tolerance.

5. The comparator thresholds are measured with the input voltage level of the SIG terminal at 125 mV
ac centered on 800 mV dc, and the input voltage at the DC OFFSET terminal is 800 mV dc.

peak and valley timing

The peak and valley attack and delay times are controlled by two 8-bit up-down counters clocked by the CLK
input. The rate that the counters are clocked depends on whether the counters are in attack or decay mode.
The peak counter is in attack mode when the input signal amplitude is greater than the output voltage from the
peak DAC, and it is in decay mode when the input signal amplitude is less that the peak DAC output voltage.
The valley counter is in attack mode when the input signal amplitude is less than the output voltage from the
valley DAC, and it is in decay mode when the input signal amplitude is greater than the valley DAC output
voltage.

When TRACKINH is held high, the attack and decay enable inputs to the peak and valley counters are disabled.
When TRACKINH is held low, the attack and decay enable inputs to the peak and valley counters are enabled.
The effect of the TRACKINH signal is exactly the same as when the device is configured in hold mode.

slow track mode attack and decay times

The attack rate is calculated equal to [V

DD

×f

(CLK)

×2] / 256 / (TRACKINH duty cycle). So the peak and valley
counter is incremented or decremented by 2 on every clock cycle when the input signal amplitude is greater
than or less than the peak and valley DAC output voltage.

The decay rate is calculated equal to [V

DD

×f

(CLK)

] / (256 ×40) / (TRACKINH duty cycle). So the peak and valley
counter is decremented or incremented once every 40 clock cycles when the input signal amplitude is less than
or greater than the peak and valley DAC output voltage.

When the counters receive an attack enable at the same time as a decay enable, the attack enable takes
precedence. The decay counter is reset to 1 after an attack and reset to 40 following a decay.

The attack and decay times for a V

DD

supply variation of 1.8 V to 2.5 V and a fixed clock input of 38.4 kHz are

given in Table 4.

Table 4. Slow Track Mode Attack and Decay Times

DESCRIPTION CONDITIONS MIN MAX UNIT

Attack rate (ATTR) TRACKINH = Low 810 990 mV/ms

Decay rate (DECR) TRACKINH = Low 10.125 12.375 mV/ms

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

fast track mode attack and decay times

The attack rate is calculated equal to [V

DD

×f

(CLK)

×4] / 256 / (TRACKINH duty cycle). So the peak and valley
counter is incremented or decremented by a count of 4 on every clock cycle when the input signal amplitude
is greater than or less than the peak and valley DAC output voltage.

The decay rate is calculated equal to [V

DD

×f

(CLK)

×8] / 256 / (TRACKINH duty cycle). So the peak and valley
counter is decrement or increment by 8 on every clock cycle when the input signal amplitude is less than or
greater than the peak and valley DAC output voltage.

When the device is in fast track mode, the decay counter is reset to 1.
The attack and decay times for a V

DD

supply variation of 1.8 V to 2.5 V and a fixed clock input of 38.4 kHz are

given in Table 5.

Table 5. Fast Track Mode Attack and Decay Times

DESCRIPTION CONDITIONS MIN MAX UNIT

Attack rate (ATTR) TRACKINH = Low 1620 1980 mV/ms

Decay rate (DECR) TRACKINH = Low 3240 3960 mV/ms

hold mode

In hold mode the peak and valley counters are disabled from counting when either attack or decay enable
signals are present. There is no change to the peak and valley DAC output voltages in this mode.

When the device is in hold mode, the decay counter is reset to 1.

off mode

In off mode, the peak and valley counters are disabled from counting, and the device is set to low-power standby
mode. Both peak and valley voltages float to the V

DD

voltage as the resistor string element within the DAC
structure is isolated from the ground (GND) supply to conserve power. When the of f state is released, the peak
and valley voltages return to the previously set values.

When the device is in off mode, the decay counter is reset to 1.

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The TLV5592 converter is optimized for messaging applications. The TLV5592 optimizes the filtering and
conversion resolution to meet the specific requirements of FLEX messaging devices. The combination of the
TL V5592 converter and TLV559X decoder reduces overall system cost by allowing a low-cost microcontroller
to be used in the messaging system. Figure 5 shows the basic connections between system elements.

SIG

0.1 µF

TLV559X

FLEX

Decoder

2.0 V

Microcontroller

Receiver

AV

DD

DV

DD

EXTS0
EXTS1

TRACKINH

CON2

TLV5592

CON1

BW

CLK

SDI

SDO

SCK

TEST
GND

READY

SCK

MOSI

MISO

RESET

PORT

IRQ

EXTS0
EXTS1

SYMCLK

S5
S6
S4
CLKOUT

S0

0.0018 µF

18 KΩ

DC OFFSET

‡

MID

†

†

The voltage on the MID terminal is nominally AVDD/2.

‡

The voltage applied to the DC OFFSET terminal is equal to the dc offset voltage of the input signal applied to the SIG terminal.

220 nF

SS

SS

Figure 5. TL V5592 Application Schematic

At least one bit of warm-up time in fast track mode followed by five bits of warm-up time in slow track mode is
necessary before valid data can be present. Hold mode is used during a data transfer, and fast track mode is
used for warm-up. Slow track mode is used for tracking during the synchronization portion of the data.

TLV5592

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET

SLAS145A – JUNE1996 – REVISED DECEMBER 1997

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/E 08/96

14 PIN SHOWN

Seating Plane

0,05 MIN

1,20 MAX

1

A

7

14

0,19

4,50
4,30

8

6,20

6,60

0,30

0,75
0,50

0,25

Gage Plane

0,15 NOM

0,65

M

0,10

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

8

4,90

5,10

14

6,60

6,404,90

5,10

16

7,70

20

7,90

24

9,60

9,80

28

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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