Page 1
D
Drive Capability and Output Counts
– 80 mA (Current Sink) x 16 Bits
D
Constant Current Output Range
– 5 to 80 mA (Current Value Setting for All
Output Terminals Using External Resistor
and Internal Brightness Control Register)
D
Constant Current Accuracy
– ±4% (Maximum Error Between Bits)
D
Voltage Applied to Constant Current Output
Terminals
– Minimum 0.4 V (Output Current 5 to
40 mA)
– Minimum 0.7 V (Output Current 40 to
80 mA)
D
1024 Gray Scale Display
– Pulse Width Control 1024 Steps
D
Brightness Adjustment
– All Output Current Adjustment for 64
Steps (Adjustment for Brightness
Deviation Between LED Modules)
– Output Current Adjustment by Output
(OUT0 to OUT15) for 64 Steps
(Adjustment for Brightness Deviation
Between Dots)
– Brightness Control by 16 Steps
Frequency Division Gray Scale Control
Clock (Brightness Adjustment for Panel)
D
Gray Scale Clock Generation
– Gray Scale Control Clock Generation by
Internal PLL or External Input Selectable
D
Clock Invert/Noninvert Selectable
– Clock Invert Selectable to Reduce
Changes in Duty Ratio at Cascade
Operation
†
LED DRIVER
SLLS392 – NOVEMBER 1999
D
Protection
– WDT (Watchdog Timer) Function (Turn
Output Off When Scan Signal Stopped)
– TSD (Thermal Shutdown) Function (Turn
Output Off When Junction Temperature
Exceeds Limit)
D
LOD
– LED Open Detection (Detection for LED
Disconnection)
D
Data Input/Output
– Port A (for Data Display)
– Clock Synchronized 10 Bit Parallel
Input (Schmitt Triggered Input)
– Clock Synchronized 10 Bit Parallel
Output (3-State Output)
– Port B (for Dot Correction Data)
– Clock Synchronized 6 Bit Parallel
Input (Schmitt-Triggered Input)
– Clock Synchronized 6 Bit Parallel
Output
D
Input/Output Signal Level
– CMOS Level
D
Power Supply Voltage
– 4.5 V to 5.5 V (Logic, Analog and
Constant Current)
– 3 V to 5.5 V (Interface)
D
Maximum Output Voltage . . . 15 V (Max)
D
Data Transfer Rate . . . 20 MHz (Max)
D
Gray Scale Clock Frequency
– 16 MHz (Max) Using Internal PLL
– 8 MHz (Max) Using External Clock
D
Operating Free-Air Temperature Range
–20°C to 85°C
D
100-Pin HTQFP Package (PD=4.7 W,
T
= 25°C)
A
‡
TLC5910
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
These functions are adjustable independently.
‡
Allows the writting of all the data at port A by setting the logic to 1.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
Page 2
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
description
The TLC5910 is a constant current driver, incorporating a shift register , data latch, and constant current circuitry
with current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display
using pulse width control. The output current is a maximum of 80 mA with 16 bits, and the current value of
constant current output can be set by one external resistor. The device has two channel I/O ports. The
brightness deviation between LED modules (ICs) can be adjusted by external data input from a display data
port. The brightness control for the panel can be accomplished by the brightness adjustment circuitry.
Independently of these functions, the device incorporates the shift register and data latch to correct the deviation
between LEDs adjusting output current using data from a dot correction data port. Moreover, the device
incorporates watchdog timer (WDT) circuitry , which turns the constant current output off when a scan signal is
stopped at the dynamic scanning operation. It incorporates thermal shutdown (TSD) circuitry, which turns
constant current output off when the junction temperature exceeds the limit. It also incorporates LOD (LED open
detection) circuitry, which creates an error signal output when LED disconnection occurs and test mode
functions detect LED open or short conditions.
PZP PACKAGE
(TOP VIEW)
GNDLED
OUT0
OUT1
GNDLED
OUT2
OUT3
GNDLED
OUT4
OUT5
GNDLED
OUT6
OUT7
GNDLED
OUT8
OUT9
GNDLED
OUT10
OUT11
GNDLED
OUT12
OUT13
GNDLED
OUT14
OUT15
GNDLED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TEST4
TEST3
99
100
27
26
GNDLOG
TEST2
DPOL
96
97
98
30
29
28
DCENA
BCENA
VCCLOG
93
94
95
33
32
31
VCCIF
DCDIN5
91
92
35
34
DCDIN4
DCDIN3
DCDIN2
88
89
90
38
37
36
DCDIN1
DCDIN0
DIN9
85
86
87
41
40
39
DIN8
DIN7
83
84
43
42
DIN6
DIN5
81
82
45
44
DIN4
DIN3
79
80
47
46
DIN2
DIN1
77
78
49
48
DIN0
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VCOIN
RBIAS
MAG0
MAG1
MAG2
PDOUT
GSPOL
GSCLK
BLANK
XENABLE
XOE
DCLK
XLA TCH
DCCLK
XDCLAT
RSEL0
RSEL1
LEDCHK
OPEN
WDTRG
XDOWN1
XDOWN2
BOUT
XGSOUT
XPOUT
IREF
TEST1
TSENA
VCCLED
WDCAP
GNDANA
XDWN2TST
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
XRST
VCCANA
DCDOUT5
DCDOUT4
DCDOUT3
DCDOUT2
DCDOUT1
DOUT9
DOUT8
DOUT7
DCDOUT0
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
Page 3
functional block diagram
XOE
BCENA
DCLK
DPOL
XENABLE
DCLK
Control
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
DOUTt0–9
u
DINt0–9u,
XLATCH
RSELt0–1
DCDINt0–5u,
MAGt0–2u, GSPOL,
BLANK
XRST
WDCAP
WDTRG
LEDCHK
XDOWN2TST
TSENA
IREF
DCENA
u
XDCLAT,
DCCLK
GSCLK, RBIAS,
VCOIN, PDOUT
1 x 10 bit B.C.
Data Shift Register
Data Latch
8
PLL
WDT
TSD
10 bit
Clock Countor
16 x 10 bit
Data Shift Register
..........
16 x 10 bit
Data Latch
..........
16 x 10 bit
Data Comparator
..........
16 bit
LED Driver+LOD
..........
16 bit
Current Controller
..........
16 x 6 bit
D.C. Data Latch
XPOUT
XGSOUT
BOUT
OUT0
· · ·
OUT15
XDOWN1
XDOWN2
..........
16 x 6 bit
D.C. Data Shift Register
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C (Dot Control) : Adjustment for brightness deviation between dots.
NOTE: All the input terminals are with Schmitt-triggered inverters except RBIAS, VCOIN, PDOUT, IREF, and WDCAP.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCDOUTt0–5
u
3
Page 4
TLC5910
CONNECTION
LED DRIVER
SLLS392 – NOVEMBER 1999
functional block diagram for shift register and data latch
XOE
DCLK
DPOL
XENABLE
DCCLK
DIN<0–9>
DCDIN<0–5>
XLATCH
XDCLAT
RSEL<0–1>
DCLK
Controller
10
6
DATA
10
a
A
b
B
c
a
A
b
B
c
a
A
b
B
c
S/R
B.C.
S/R
6
D.C.
S/R
10 16 10 16
†
1
‡
2
6 16
DATA
LATCH
10 10
10 1010
B.C.
LATCH
6
D.C.
LATCH
6 16
a
b
c
HI–Z
DATA
Comparator
A
1
0
0
1
10
Clock Counter
Current Controller
6 16
10
DOUT<0–9>
DCDOUT<0–5>
DATA
Comparator
6 16
BCENA
DCENA
†
1 : Connect to 16th 10 bit bus
‡
2 : Connect to 16th 6 bit bus
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C. (dot control) : Adjustment for brightness deviation between dots.
RSEL
RSEL1 RSEL0
0 0 A – a, B – c
0 1 A – b, B – c
1 0 A – c
1 1 INHIBIT
Default
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
schematic
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Input
DOUT0–9, DCDOUT0–5, XGSOUT, XPOUT, BOUT
XDOWN1, XDOWN2
VCCIF
INPUT
GNDLOG
XDOWN1, XDOWN2
VCCLOG
OUTPUT
GNDLOG
OUTn
GNDLOG
OUTn
GNDLED
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
TLC5910
I/O
DESCRIPTION
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LED DRIVER
SLLS392 – NOVEMBER 1999
TERMINAL
NAME NO.
ÁÁÁÁ
BCENA
ÁÁÁÁ
ÁÁÁÁ
BLANK
ÁÁÁÁ
ÁÁÁÁ
BOUT
DCCLK
ÁÁÁÁ
DCDIN0 –
DCDIN5
DCDOUT0 –
ÁÁÁÁ
DCDOUT5
DCENA
ÁÁÁÁ
DCLK
ÁÁÁÁ
DIN0 – DIN9
ÁÁÁÁ
DOUT0 –
DOUT9
ÁÁÁÁ
DPOL
ÁÁÁÁ
GNDANA
GNDLOG
GNDLED
ÁÁÁÁ
ÁÁÁÁ
GSCLK
ÁÁÁÁ
GSPOL
ÁÁÁÁ
IREF
ÁÁÁÁ
LEDCHK
MAG0 – MAG2
OPEN
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
76,77,78,79,80,
81,82,83,84,85
ÁÁÁÁ
50,49,48,47,46,
45,44,43,42,41
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
94
67
53
62
86,87,88,
89,90,91
40,39,38,
37,36,35
95
64
96
28
98
1,4,7,10,13,
16,19,22,25
68
69
32
58
73,72,71
57
Terminal Functions
Brightness control enable. When BCENA is low, brightness control latch is set to the default
БББББББББББББББББББББ
value. The output current value in this status is 100% of setting the value by an external resistor.
I
The frequency division ratio of GSCLK is 1/1. When BCENA is high, writing to brightness control
БББББББББББББББББББББ
latch is enabled.
Blank(light off). When BLANK is high, all outputs of the constant current driver are turned off.
When GSPOL is high, the output is turned on (LED on), synchronizing to the falling edge of
БББББББББББББББББББББ
GSCLK after the next rising edge of GSCLK, when BLANK goes from high to low. When GSPOL
I
БББББББББББББББББББББ
is low, the output is turned on (LED on), synchronizing to the rising edge of GSCLK after the
next falling edge of GSCLK, when BLANK goes from high to low.
БББББББББББББББББББББ
O
BLANK buffered output
Clock input for data transfer. The input data is from DCDIN (port B) , output data at DCDOUT,
and all data on the shift register for dot correction data, from DCDIN, is shifted by 1 bit
I
БББББББББББББББББББББ
synchronizing to the rising edge of DCCLK.
Input for 6 bit parallel data (port B). These terminals are used as a shift register input for dot
I
correction data.
Output for 6 bit parallel data (port B). These terminals are used as a shift register output for dot
O
БББББББББББББББББББББ
correction data.
Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.
I
At this time, the output current value is 100% of the value set by an external resistor.
Clock input for data transfer. The input data is from DIN (port A) , all data on the shift register
БББББББББББББББББББББ
selected by RSEL, 1 and output data at DOUT is shifted by 1 bit synchronizing to DCLK. Note
I
that synchronizing to either the rising or falling edge of DCLK depends on the value of DPOL.
БББББББББББББББББББББ
Input for 10 bit parallel data (port A). These terminals are inputs to the shift register for gray scale
data, brightness control, and dot correction data. The register selected is determined by RSEL0,
I
БББББББББББББББББББББ
1.
Output for 10 bit parallel data (port A). These terminals are outputs to the shift register for gray
scale data, brightness control, and dot correction data. The register selected is determined by
O
БББББББББББББББББББББ
RSEL0, 1.
Select the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When
I
DPOL is low, the falling edge of DCLK is valid.
БББББББББББББББББББББ
Analog ground (internally connected to GNDLOG and GNDLED)
Logic ground (internally connected to GNDANA and GNDLED)
LED driver ground (internally connected to GNDANA and GNDLED)
БББББББББББББББББББББ
Clock input for gray scale. When MAG0 to MAG2 are all low, GSCLK is used for pulse width
control, and GSCLK is used for PLL timing control when either MAG is not low. The gray scale
БББББББББББББББББББББ
I
display is accomplished by lighting LEDs on until the number of GSCLK or PLL clocks counted
БББББББББББББББББББББ
is equal to data latched.
Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When
I
GSPOL is low, the falling edge of GSCLK is valid.
Constant current value setting. LED current is set to the desired value by connecting an external
БББББББББББББББББББББ
resistor between IREF and GND. The 38 times current compares current across the external
I/O
resistor sink on the output terminal.
БББББББББББББББББББББ
LED disconnection detection enable. When LEDCHK is high, LED disconnection detection is
I
enabled and XDOWN2 is valid. When LEDCHK is low, LED disconnection detection is disabled.
I
PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set.
TEST. Factory test terminal. OPEN should be opened.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
I/O
DESCRIPTION
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ББББББ
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TERMINAL
NAME NO.
ÁÁÁÁ
OUT0–DOUT15
ÁÁÁÁ
PDOUT
RBIAS
ÁÁÁÁ
ÁÁÁÁ
RSEL0
RSEL1
ÁÁÁÁ
ÁÁÁÁ
TEST1–TEST4
THERMAL PAD
TSENA
VCOIN
VCCANA
VCCLOG
VCCIF
VCCLED
WDTRG
ÁÁÁÁ
WDCAP
ÁÁÁÁ
ÁÁÁÁ
XDCLAT
ÁÁÁÁ
XDOWN1
ÁÁÁÁ
XDOWN2
XDWN2TST
ÁÁÁÁ
XENABLE
XGSOUT
ÁÁÁÁ
XLATCH
ÁÁÁÁ
XOE
ÁÁÁÁ
XPOUT
XRST
2,3,5,6,8,9,11,12,
ÁÁÁÁ
14,15,17,18,20,21,
23,24
ÁÁÁÁ
70
74
ÁÁÁÁ
ÁÁÁÁ
60
59
ÁÁÁÁ
ÁÁÁÁ
29,97,99,100
package bottom
31
75
33
93
92
26
56
ÁÁÁÁ
30
ÁÁÁÁ
ÁÁÁÁ
61
ÁÁÁÁ
55
ÁÁÁÁ
54
27
ÁÁÁÁ
66
52
ÁÁÁÁ
63
ÁÁÁÁ
65
ÁÁÁÁ
51
34
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions (Continued)
I/O
I/O
I/O
I/O
Á
O
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I
I
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O
I
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I
O
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I
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O
I
БББББББББББББББББББ
Constant current output
БББББББББББББББББББ
Resistor connection for PLL feedback adjustment
Resistor connection for PLL oscillation frequency setting
Input/output port selection and shift register data latch switching.
БББББББББББББББББББ
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected
to port A and the dot correction register latch is selected to port B.
БББББББББББББББББББ
When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
БББББББББББББББББББ
port A and the dot correction register latch is selected to port B.
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port
БББББББББББББББББББ
A and no register latch is selected to port B.
TEST. Factory test terminal. These terminals should be connected to GND.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is
low, TSD is disabled.
Capacitance connection for PLL feedback adjustment
Analog power supply voltage
Logic power supply voltage
Interface power supply voltage
LED driver power supply voltage
WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan
signal can be monitored by turning the constant current output off and protecting the LED
БББББББББББББББББББ
from damage when the scan signal stopped during the constant period designed.
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
between WDCAP and GND. When WDCAP is directly connected to GND, WDT function
БББББББББББББББББББ
is disabled. In this case, WDTRG should be tied to a high or low level.
Data latch for dot correction. When XDCLAT is high, data on the shift register for dot
БББББББББББББББББББ
correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is
latched. Accordingly , if data on the shift register is changed during XDCLAT high, this new
БББББББББББББББББББ
value is latched (level latch).
Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current
output is shut down by WDT or TSD function.
БББББББББББББББББББ
LED disconnection detection output. XDOWN2 is configured as an open collector.
XDOWN2 goes low when an LED disconnection is detected.
T est for XDOWN2. When XDWN2TST is low, XDOWN2 goes low . (This terminal is internally
БББББББББББББББББББ
pulled up with 50 kΩ)
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.
Clock output for gray scale. When MAG0 to MAG2 are all low, the clock with GSCLK inverted
БББББББББББББББББББ
appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal.
Latch. When XLATCH is high, data on the shift register from DIN (port A) goes through latch.
When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed
БББББББББББББББББББ
during XLATCH high, this new value is latched (level latch).
Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,
DOUT0–9 terminals go to a high
БББББББББББББББББББ
-impedance state.
GSPOL output inverted
Blank (Light off). When XRST is low, all the output of the constant current driver is turned
off. (This terminal is internally pulled up with 50 kΩ)
TLC5910
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
TLC5910
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mA
LED DRIVER
SLLS392 – NOVEMBER 1999
absolute maximum ratings (see Note 1)
†
Logic supply voltage, VCCLOG – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage for interface circuit, VCCIF – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage for constant current circuit, VCCLED – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog supply voltage, VCCANA – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (dc), I
85 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O(LC)
Input voltage range, VI – 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
and V
XGSOUT
Output voltage range, V
O(DOUT)
– 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O(OUT)
Storage temperature range, T
, V
O(DCDOUT)
and V
O(XDOWNn)
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
str
, V
BOUT
, V
XPOUT
– 0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) TA = 25°C 4.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation rating at (or above) T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GNDLOG terminal.
= 25°C 38.2 mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
recommended operating conditions
dc characteristics
PARAMETER
Logic supply voltage, VCCLOG
Supply voltage for interface circuit,
VCCIF
Supply voltage for constant current
БББББББББ
circuit, VCCLED
Analog power supply, VCCANA
Voltage between VCC, V
БББББББББ
Voltage between GND, V
БББББББББ
DIFF1
DIFF2
Voltage applied to constant current
БББББББББ
output, V
High-level input voltage, V
Low-level input voltage, V
High–level output current, I
БББББББББ
БББББББББ
Low–level output current, I
Constant output current, I
OUT
IH
IL
OH
OL
OLC
Operating free-air temperature range,
T
A
PLL capacitance, C
PLL resistor, R
PLL resistor, R
VCO
BIAS
PD
ББББББББББÁÁÁÁ
V
DIFF1
VCCLOG – VCCLED
ББББББББББ
VCCANA – VCCLED
V
DIFF2
GNDLOG – GNDLED
ББББББББББ
GNDANA – GNDLED
OUT0 to OUT15 off
ББББББББББ
VCCLOG = 4.5 V,
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
ББББББББББ
VCCLOG = 4.5V,
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
ББББББББББ
BOUT, XGSOUT, XPOUT
VCCLOG = 4.5 V, XDOWN1, XDOWN2
OUT0 to OUT15
At 16 MHz oscillation
TEST CONDITIONS
= VCCLOG – VCCANA
= GNDLOG – GNDANA
MIN
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
0.8 VCCLOG
GNDLOG
4.5
3.0
4.5
4.5
– 0.3
– 0.3
NOM
Á
Á
Á
5
5
5
ÁÁÁ
5
0
ÁÁÁ
0
ÁÁÁ
0.2 VCCLOG
MAX
5.5
5.5
5.5
5.5
0.3
0.3
15
VCCLOG
– 1.0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
5
– 20
1.0
80
85
1
22
30
UNIT
V
V
V
Á
V
V
Á
V
Á
V
Á
V
V
Á
Á
5
mA
mA
°C
µF
kΩ
kΩ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
DCLK, DCCLK clock frequenc
f
f
MH
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
ac characteristics, VC CLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, T
PARAMETER
y,
DCLK, DCCLK pulse duration (high or low level), twh/t
GSCLK clock frequency, f
GSCLK
GSCLK pulse duration (high or low level), twh/t
WDT clock frequency, f
WDT
WDT pulse duration (high or low level), twh/t
XLATCH, XDCLAT pulse duration (high level), t
Rise / fall time, tr/t
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
Setup time, t
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
Hold time, t
БББББББББББББББ
БББББББББББББББ
БББББББББББББББ
f
su
h
DCLK,
DCCLK
wl
wl
wl
wh
TEST CONDITIONS
At single operation
At cascade operation
DINn – DCLK
БББББББ
DCDINn – DCCLK
BLANK – GSCLK
БББББББ
XENABLE – DCLK
БББББББ
XLATCH – DCLK
XLATCH – GSCLK
БББББББ
XDCLAT – DCCLK
RSEL – DCLK
БББББББ
RSEL – DCCLK
БББББББ
RSEL – XLATCH
RSEL – XDCLAT
БББББББ
DINn – DCLK
DCDINn – DCCLK
БББББББ
XENABLE – DCLK
XLATCH – DCLK
БББББББ
XDCLAT – DCCLK
БББББББ
RSEL – DCLK
RSEL – DCCLK
БББББББ
RSEL – XLATCH
БББББББ
RSEL – XDCLAT
= – 20 to 85°C (unless otherwise noted)
A
MIN
TYP
MAX
UNIT
20
15
20
8
40
8
40
30
100
5
Á
Á
Á
Á
Á
Á
Á
10
15
10
10
10
10
15
30
15
Á
5
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
15
15
Á
Á
Á
Á
Á
20
30
20
20
20
20
10
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
z
ns
MHz
ns
MHz
ns
ns
ns
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
TLC5910
Á
Á
Á
Á
Á
OL
g
Á
Á
Á
Á
Á
Á
Á
Á
I
Á
Supply current (logic)
Á
Á
Á
Á
mA
Á
Á
Á
Á
I
Supply current (analog)
mA
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
I
OLK
Constant out ut leakage current
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
LED DRIVER
SLLS392 – NOVEMBER 1999
electrical characteristics, LEDCHK = L,
MIN/MAX: VCCLOG = VCCANA
= VCCLED = 4.5 V to 5.5 V, T
TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)
= – 20 to 85°C
A
V
OH
ÁÁÁ
PARAMETER
High-level output voltage
БББББББББ
DOUTn, DCOUTn, XGSOUT, XPOUT,
БББББББББ
BOUT IOH = –1 mA
TEST CONDITIONS
DOUTn, DCOUTn, XGSOUT, XPOUT,
V
Low-level output voltage
BOUT IOL = 1 mA
XDOWN1, XDOWN2 IOL = 5 mA
I
I
Input current
VIN = VCCLOG or GNDLOG
Input signal is static,
ÁÁÁÁБББББББББÁБББББББББ
TSENA = H, WDCAP = OPEN,
No PLL is used
Input signal is static,
ÁÁÁÁБББББББББ
LOG
ÁÁÁ
pp
БББББББББ
TSENA = H, WDCAP = OPEN,
БББББББББ
PLL multiple ratio = 1042
Data transfer,
DCLK = 20 MHz, GSCLK = 8 MHz
БББББББББ
No PLL is used
Data transfer,
ÁÁÁÁБББББББББÁБББББББББ
DCLK = 20 MHz, GSCLK = 15 kHz
PLL multiple ratio = 1042
ANA
pp
BLANK = L, R
BLANK = L, R
LED turn off, R
LED turn off, R
V
=1V, R
I
LED
ÁÁÁÁБББББББББÁБББББББББ
I
OLC1
I
ÁÁÁ
OLC2
Supply current (constant current driver)
Constant output current (includes error
between bits)
Constant output current (includes error
БББББББББ
between bits)
OUT
All output bits turn on
V
=1V, R
OUT
All output bits turn on
V
=1V, V
OUT
R
= 1200Ω
IREF
V
= 0.7 V, V
OUT
БББББББББ
R
= 600 Ω
IREF
OUT0 to OUT15 (V
p
XDOWN1,2 (V
= 1200 Ω
IREF
= 600 Ω
IREF
= 1200 Ω
IREF
=600 Ω
IREF
= 1200Ω
IREF
= 600 Ω
IREF
= 1.21 V,
IREF
IREF
OUTn
XDOWNn
= 1.21 V,
= 15 V)
= 15 V)
DOUTn, DCDOUTn
(V
= VCCLOG or GND)
OUTn
VCCLOG=VCCANA=VCCLED= 5 V,
∆I
ÁÁÁ
OLC
I∆
OLC1
ÁÁÁ
I∆
OLC2
T
tsd
T
wdt
V
IREF
V
LEDDET
ÁÁÁ
P
LLJITTER
Constant output current error between bit
БББББББББ
Changes in constant output current
БББББББББ
depend on supply voltage
Changes in constant output current
depend on output voltage
TSD detection temperature
WDT detection temperature
Voltage reference
Voltage applied to LED disconnection
detection
БББББББББ
PLL jitter
V
= 1 V, R
БББББББББ
OUT
All output bits turn on
V
= 1V, R
OUT
БББББББББ
V
= 1.21 V
IREF
V
= 1 V to 3 V, R
OUT
V
= 1.21 V, 1 bit output turn on
IREF
IREF
IREF
= 600 Ω
= 600 Ω,
IREF
= 600 Ω,
Junction temperature
No external capacitor
BCENA = L, R
БББББББББÁÁÁ
R
= 22 kΩ, RPD = 30 kΩ,
BIAS
C
= 0.1 µF
VCO
IREF
= 590 Ω,
MIN
TYP
MAX
VCCLOG
ÁÁ
–0.5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
35
Á
39
Á
6.5
13
12
20
12
ÁÁÁÁ
35
70
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
20
40
80
Á
± 1%
± 1
Á
Á
± 4%
Á
Á
± 1
150
160
5
170
10
1.21
0.2
0.3
Á
Á
0.4%
0.5
0.5
± 1
0.1
45
49
15
20
35
20
35
45
90
0.1
± 4
± 3
15
0.4
2%
UNIT
V
V
µA
mA
Á
1
Á
Á
mA
Á
8
mA
Á
mA
mA
Á
µA
1
µA
1
µA
Á
%/V
Á
%/V
°C
ms
V
V
Á
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 11
tdPropagation delay time
ns
switching characteristics, CL = 15pF,
MIN/MAX: VCCLOG= VCCANA
= VCCLED = 4.5 V to 5.5 V, T
TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)
= – 20 to 85°C,
A
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PARAMETER
t
Rise time
r
t
Fall time
f
p
NOTES: 2. MAG0 to MAG2 are all low level.
3. Until DOUT will be turned on (drive) or turned off (Hi-Z).
TEST CONDITIONS
DOUTn, DCDOUTn
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
DOUTn, DCDOUTn
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
OUTn+1 – OUTn
BLANK↑ – OUT0
BLANK – BOUT
GSCLK – OUT0 (see Note 2)
GSCLK – XGSOUT
DCLK – DOUTn
DCLK – DCDOUTn
DCCLK – DCDOUTn
XOE↓ – DOUTn (see Note 3)
XOE↑ – DOUTn (see Note 3)
RSEL – DOUTn
LEDCHK – XDOWN2
MIN
40
10
10
15
15
15
10
10
10
TYP
110
130
12
12
10
10
30
50
20
20
30
30
30
20
15
20
MAX
7
1000
30
30
30
30
45
105
40
40
45
45
45
35
25
40
UNIT
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
Page 12
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
90%
10%
100%
50%
0%
V
CC
IREF OUTn
600 Ω
GND
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
V
IH
V
t
r
t
wh
t
f
t
wl
IL
100%
50%
0%
V
IH
V
IL
100%
50%
0%
51 Ω
15pF
VIH or V
VIL or V
t
d
OH
OL
VIH or V
VIL or V
OH
OL
Figure 2. Timing Requirements
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 13
RSEL1
RSEL0
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
external resistor, R
using the following equation:
R
(Ω) ≅ 38 × 1.21 (V)/I
IREF
Note that more current flows if IREF is connected to GND directly.
constant output current operation
If GSPOL is high, the constant current output turns on the sink constant current if all the gray scale data in the
gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale
clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10 bit gray
scale counter. Then, the output counted corresponding to the gray scale data is turned of f (stop to sink constant
current). The gray scale clock can be selected from GSCLK or that generated by internal PLL circuitry. If the
shift register for gray scale is updated during XLA TCH high, data on the gray scale data latch is also updated
affecting the constant current output number of the gray scale. Accordingly , during the on-state of the constant
current output, keep the XLATCH to a low level and hold the gray scale data latch.
(connected between IREF and GND), can flow. The external resistor value is calculated
IREF
(A) where both BCENA and DCENA are low.
O(LC)
TLC5910
input/output port and shift register selection
The TLC5910 supplies two parallel input ports such as DIN (10 bits) and DCDIN (6 bits). The DIN and DCDIN
ports also supply DCLK and DCCLK for shift clock, XLA TCH and XDCLAT for latch, and DOUT and DCDOUT
for output, respectively . The device has three types of shift register latches, gray scale data, brightness control,
and dot correction. The port and shift register can be selected by RSEL0 and RSEL1. Table 1 shows the
selection using RESL0 and RSEL1. Note that the RSELn setting should be done at DCLK low, (when DPOL
is high, and at DCLK high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and
XDCLAT should be connected to GND.
Table 1. Shift Register Latch Selection
SELECTED SHIFT REGISTER LATCH
PORT A
DIN, DCLK, XLATCH, DOUT
L
L
H
H
NOTE: Zero is output to DOUT6 to DOUT9.
L
H
L
H
Gray scale data displayed
Brightness control
Dot correction (see Note)
N/A (inhibit)
DCDIN, DCCLK, XDCLATCH
Dot correction
Dot correction
Not connected
N/A (inhibit)
shift register latch for gray scale data
The shift register latch for gray scale data is configured with 16 x 10 bits. The gray scale data, configured with
10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). When
the gray scale data is 1023, the time is longest, and it turns on during time of 1023 clocks from the gray scale
clock. The configuration of the shift register and latch for gray scale data is shown in Figure 3.
PORT B
DCDOUT
Dot correction
Dot correction
Dot correction
N/A (inhibit)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
Page 14
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Latch for Gray Scale Data
PRINCIPLES OF OPERATION
XLATCH
DOUT0 to 9
OUT15
Data
(10 bits)
Shift Register for Gray Scale Data
16th byte
DIN9 MSB
DIN0 LSB
OUT14
Data
(10 bits)
15th byte
DIN9 MSB
DIN0 LSB
OUT1
Data
(10 bits)
2nd byte
DIN9 MSB
DIN0 LSB
OUT0
Data
(10 bits)
1st byte
DIN9 MSB
DIN0 LSB
Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data
shift register latch for brightness control
The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for
brightness control, the division ratio of the gray scale clock can be set and the output current value on constant
current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not
initialized. Data should be written to the shift register latch prior to lighting-on (BLANK=L) when these functions
are used. Also, the latch value for brightness control cannot be rewritten when the constant current output is
turned on. When these functions are not used, the latch value can be set to the default value setting BCENA
to low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain
the compatibility with TLC5901/02/03 family . The configuration of the shift register and the latch for brightness
control is shown below.
Latch for Brightness Control
DCLK
DIN0 to 9
Gray Scale Clock Division Ratio Data Set
XLATCH
DOUT0 to 9
Note A: Indicates default value at BCENA low.
00 1111
MSB LSB MSB LSB
Shift Register for Brightness Control
DIN8
DATA
DIN7
DATA
DIN6
DATA
00
DIN5
DATA
Current Data Adjusted On Constant Current Output
11
DIN4
DATA
DIN3
DATA
DIN2
DATA
DIN1
DATA
DIN0
DATA
DIN9
DATA
Figure 4. Relationship Between Shift Register and Latch for Brightness Control
shift register latch for dot correction
The shift register latch for dot correction is configured with 16 × 6 bits. Using the shift register latch for dot
correction, the current value on the constant current output can be set individually . When powered up, the latch
data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior
to lighting-on (BLANK=L) when these functions are used. Also, the latch value for dot correction cannot be
rewritten when the constant current output is turned on. When these functions are not used, the latch value can
be set to the default value setting of DCENA to low level (connect to GND). The configuration of the shift register
and the latch for dot correction is shown in Figure 5.
(Note A)
DCLK
DIN0 to 9
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 15
5
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
Latch for Dot Correction
XLATCH
DCDOUT0 to 5
XLATCH
DOUT0 to 5
OUT15
Data
(6 bits)
Shift Register for Dot Correction
16th byte
DCDIN5 MSB
DCDIN0 LSB
Using Port B (RSEL0=L or H, RSEL1=L)
Latch for Dot Correction
OUT15
Data
(6 bits)
Shift Register for Dot Correction
16th byte
DCDIN5 MSB
DCDIN0 LSB
OUT14
Data
(6 bits)
15th byte
DCDIN5 MSB
DCDIN0 LSB
OUT14
Data
(6 bits)
15th byte
DCDIN5 MSB
DCDIN0 LSB
OUT1
Data
(6 bits)
2nd byte
DCDIN5 MSB
DCDIN0 LSB
OUT1
Data
(6 bits)
2nd byte
DCDIN5 MSB
DCDIN0 LSB
OUT0
Data
(6 bits)
1st byte
DCDIN5 MSB
DCDIN0 LSB
OUT0
Data
(6 bits)
1st byte
DCDIN5 MSB
DCDIN0 LSB
DCCLK
DCDIN0 to
DCLK
DIN0 to 5
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between Shift Register and Latch for Dot Correction
write data to shift register latch
The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. At port A, the data is applied
to the DIN data input terminal and clocked into the shift register synchronizing to the rising edge of DCLK after
XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal and clocked into the
shift register synchronizing to the rising edge of DCCLK. The shift register for the gray scale data is configured
with 16 × 10 bits and the shift register for dot correction is configured with 16 x 6 bits resulting in sixteen times
DCLK, and the shift register for brightness control is configured with 1 x 10 bits resulting in one times DCLK.
At number of DCLK input for each case, data can be written into the shift register. In this condition, when
XLA TCH at port A or XDCLAT at port B is pulled high, data in the shift register is clocked into latch (data through),
and when XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
Page 16
TLC5910
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
brightness control function
By writting data into the brightness control latch, the current on all constant current outputs can be adjusted to
control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control
the variation of brigtness for the total panel system. Furthermore, by writing data into the dot correction latch,
the current on each constant current output can be adjusted.
output current adjustment on all constant current outputs – brightness adjustment between ICs
By using the lower 6 bits of the brightness control latch, the output current can be adjusted to 64 steps. 1 step
of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an external resistor (note
that the current value is lower if the constant current output is corrected using the dot correction function). By
using this function, the brightness control between modules (ICs) can be adjusted sending the desired data
externally even if the ICs are mounted on a print-circuit board. When BCENA is pulled low, output current is set
to 100%.
Table 2. Relative Current Ratio For Total Constant Current Output
CODE
MSB 000000 LSB
.
БББББ
БББББ
.
.
.
111110
†
111111
†
BCENA is low.
CURRENT RATIO
(%)
50.8
.
ÁÁÁÁ
ÁÁÁÁ
.
.
.
99.2
100
20
(mA)80(mA)
10.2
.
.
ÁÁ
.
ÁÁ
.
19.8
20.0
40.6
.
.
Á
.
Á
.
79.7
80.0
V
IREF
(TYP)
0.61
.
.
ÁÁ
.
ÁÁ
.
1.20
1.21
frequency division ratio setting for gray scale clock – panel brightness adjustment
By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16.
If the gray scale clock is set to 16 times the speed (1024×16=16384) of frequency during horizontal scanning
time, the brightness can be adjusted to 16 steps selecting the frequency division ratio. By using this function,
the total panel brightness can be adjusted at once, and it applies to the brightness of day or night circumstances.
When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can
be adjusted (see Table 3).
Table 3. Relative Brightness Ratio For Total Constant Current Output
CODE
ÁÁÁÁ
MSB 0000 LSB
ÁÁÁÁ
1110
1111
†
BCENA is low.
FREQUENCY
DIVISION RATIO
БББББ
†
.
.
.
БББББ
.
1/1
.
.
.
.
1/15
1/16
RELATIVE BRIGHTNESS RATIO
ББББББББ
(%)
6.3
.
.
ББББББББ
.
.
93.8
100
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 17
Á
Á
Á
Á
Á
Á
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
output current adjustment on each constant current output – LED brightness adjustment
By using the 6 bits of the dot correction latch, the output current on each constant current output can be adjusted
to 64 steps. 1 step of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an
external resistor at 1 11111h of the latched value and the lower 6 bits of the brightness control register . By using
this function, the brightness deviation due to LED brightness variation can be minimized. When DCENA is pulled
low, the output current is set to 100% without dot correction.
Table 4. Relative Current Ratio By Constant Current Output
TLC5910
CODE
MSB 000000 LSB
.
ÁÁÁÁ
ÁÁÁÁ
.
.
.
111110
111111
†
DCENA is low.
†
CURRENT RATIO (%)
50.8
.
ББББББ
ББББББ
.
.
.
99.2
100
I
=40 (mA)
OLC
20.3
.
ÁÁÁ
.
.
ÁÁÁ
.
39.7
40
clock edge selection
The high speed clock signal is delayed due to the duty ratio change through multiple stages of an IC or through
the module stages shown in Figure 6.
A’IN A OUT IN A OUT OUT’
IN
A
OUT
IN’
A’
OUT
a) Propagate through multiple stages buffer
b) Insert inverter between buffers
with slow falling edge
Figure 6. Clock Edge Selection
As shown in Figure 6 a), if the falling at the internal buffer is behind the rising, the clock will disappear as multiple
cascade connections are made. To resolve this problem, the duty ratio can be held unchanged using the
connection as shown in Figure 6 b) if the valid clock edge can be selected (arrow in Figure 6). Note that the clock
delay is not avoided even in this case.
The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,
the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL.
Thus the degradation for the duty ratio can be reduced. The relation between each signals is shown in
Table 5.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
Page 18
TLC5910
(Gray scale clock internally generated)
LED DRIVER
SLLS392 – NOVEMBER 1999
clock edge selection (continued)
Table 5. Valid Edge For DCLK and GSCLK
PRINCIPLES OF OPERATION
DPOL
H
L
GSPOL
H
L
DCLK valid edge
DCLK↑
DCLK↓
GSCLK valid edge
GSCLK↑
GSCLK↓
Operation at XENABLE = H
Pull DCLK to low level
Pull DCLK to high level
PLL operation
Synchronize to the high level of DCLK
Synchronize to the low level of DCLK
The device supplies XPOUT and XGSOUT output terminals for the cascade operation which invert GSPOL and
GSCLK respectively . It also supplies the BOUT output terminal as a buffered BLANK to make easy timing with
GSCLK and XGSOUT.
gray scale clock generation
When MAG<0:2> are all low, the clock input from GSCLK terminal is used as the gray scale clock with no
change, and except for this case internal PLL generates the clock for the gray scale control clock. When using
the PLL, the gray scale clock is generated by adjusting the clock having the same number of pulses as the
multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are keeping the same level). Note that
the reference period is required above 40% of the GSCLK period. The ratio in this case is determined depending
on MAG 0 to MAG 2 as shown in Table 6.
When using PLL, internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, this clock can be utilized
for other devices on the same print-circuit board. Note that the number of ICs connected is limited depending
on the frequency.
Table 6. PLL Multiple Ratio
MAG2
L
L
L
L
H
H
H
H
MAG1
L
L
H
H
L
L
H
H
MAG0
L
H
L
H
L
H
L
H
MULTIPLE RATIO
1 (Signal to control GSCLK by GSPOL)
28+6(=262)
29+10(=522)
210+18(=1042)
211+34(=2082)
212+66(=4162)
213+130(=8322)
214+258(=16642)
XGSOUT
Inverted GSCLK
PLLCLK
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 19
PRINCIPLES OF OPERATION
gray scale clock generation (continued)
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
MAG<0–2>
GSPOL
GSCLK
XGSOUT
PLLCLK
Except all low level
Same number of pulse as ratio
a) GSPOL is high
Same number of pulse as ratio
Except all low level
a) GSPOL is low
Figure 7. Gray Scale Clock Generation
The oscillation frequency bandwidth as referenced for PLL can be set by an external resistor connected
between RBIAS and GND. The relation between the external resistor and oscillation frequency is shown in
Table 7.
Table 7. PLL Oscillation Frequency
RBIAS
FREQUENCY
22 kΩ
13 to 20 MHz
30 kΩ
8 to 14 MHz
62 kΩ
4 to 9 MHz
120 kΩ
3 to 5 MHz
T o make PLL stabilization, a resistor and acapacitor connection is required between VCOIN, PDOUT , and GND.
The recommended value is shown in the following table in Figure 8.
PDOUT
R
pd
VCOIN
C
VCO
Recommeded Value
C
VCO
0.1 to 1 µF
R
pd
22 to 62 kΩ
Figure 8. Resistor and Capacitor Connection
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
protection
This device incorporates WDT and TSD functions. If WDT or TSD functions, the constant current output is
stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be
detected immediately . Since the XDOWN1 output is configured as an open collector, outputs of multiple ICs are
brought together.
WDT (watchdog timer)
The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapses after the
signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (signal to control line
displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned
off. This prevents the LED from burning and damage caused by continuous LED turnon at the dynamic scanning
operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately
10 ms without a capacitor, 160 ms with a 1000 pF capacitor , and 1500 ms with a0.01 µF capacitor . During static
operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to
WDTRG). Note that normal operations will resume changing the WDTRG level when WDT functions.
WDT operational time: T (ms) ≅ 10 + 0.15 × Cext (pF)
TLC5910
t – Time – ms
1500
160
10
0 0.001 0.01
Cext – External Capacitor – µF
Scan Signal
Cext
WDTRG
WDCAP
Figure 9. WDT Operational Time and Usage Example
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD starts to function and turns constant current output off,
and XDOWN1 goes low. When TSD is used, TSENA should be pulled high. When TSD is not used, TSENA
should be pulled low. To recover from constant current output off-state to normal operation, the power supply
should be turned off or TSENA should be pulled low once.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 21
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
LOD function (LED open detection)
When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a
high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and
XDOWN2 goes low if any LED is disconnected monitoring OUTn terminals to be turned on. This function is
operational for sixteen OUTn terminals individually . T o know which constant current output is disconnected, the
level of XDOWN2 is repeatedly checked 16 times from OUT0 to OUT15 turning one constant current output on.
The power supply voltage should be set so the constant current output is applied to above 0.4 V when the LED
is lighting normally . Also, since the time of approximately 1000 ns is required from turning the constant current
output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied.
Table 8 is an example for XDOWN2 output status using four LEDs .
Table 8. XDOWN2 Output Example
TLC5910
LED NUMBER
LED STATUS
OUTn
XDOWN2
LED NUMBER
LED STATUS
OUTn
DETECTION RESULT
XDOWN2
LED NUMBER
LED STATUS
OUTn
DETECTION RESULT
XDOWN2
1
GOOD
ON
1
GOOD
ON
GOOD
1
GOOD
OFF
GOOD
2
NG
ON
LOW (by case 2, 4)
2
NG
ON
NG
LOW (by case 2)
2
NG
OFF
GOOD
HIGH–IMPEDANCE
GOOD
GOOD
GOOD
GOOD
GOOD
3
ON
3
OFF
3
OFF
4
NG
ON
4
NG
OFF
GOOD
4
NG
OFF
GOOD
noise reduction
concurrent switching noise reduction
Concurrent switching noise has the potential to occur when multiple outputs turn on or off at the same time. To
prevent this noise, the device has a delay output terminal such as XGSOUT and BOUT for GSCLK (gray scale
clock) and BLANK (blanking signal) respectively . Connecting these outputs to the GSCLK and BLANK terminals
of next stage IC allows differences of the switching time between ICs. When GSCLK is output to GSOUT through
the device, duty will be changed between input and output. The number of stages to be connected will be limited
depending on frequency.
delay between constant current output
The constant current output has a delay time of approximately 20 ns between outputs. This means
approximately 300 ns delay time exists between OUT0 and OUT15. This time differences by delay reduces the
concurrent switching noise.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
power supply
The followings should be taken into consideration:
D
VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage
differences between these terminals.
D
The bypass capacitor should be located between the power supply and GND to eliminate the variation of
power supply voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
thermal pad
The thermal pad should be connected to GND to eliminate the noise influence when it is connected to the bottom
side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with
better thermal conductivity.
power rating – free-air temperature
4.7
2.4
– Total Power Dissipation – W
D
P
0
0 25 85–20
†
VCCLOG=VCCANA=VCCLED=5.0V, I
NOTES: A. IC is mounted on PCB.
PCB size: 102 × 76 x 1.6 [mm3], four layers with the internal two layer being plane. The thermal pad is soldered to the PCB pattern
of 10 × 10 [mm2]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
B. The thermal impedance will be varied depending on mounting conditions. Since the PZP package established low thermal
impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance.
C. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.
= 80mA, ICC is typical value.
OLC
†
3.2
1.48
Output Voltage (Constant Current) – V
0
TA – Free–Air Temperature – °C
22
Figure 10. Power Rating
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 23
constant output current
90
80
70
60
50
– mA
OLC
40
I
30
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
20
10
0
0.1
R
– kΩ
IREF
Conditions: V
NOTE: The brightness control and dot corrected value are 100%. The resistor, R
to avoid the noise influence.
I
R
OLC
OUT
(mA)
IREF
= 1.0V, V
≅
≅
(kW)
V
R
I
IREF
IREF
IREF
47
OLC
= 1.21V
(V)
(kW)
(mA)
38
Figure 11. Current on Constant Current Output vs External Resistor
10.01.0
, should be located as close to the IREF terminal as possible
IREF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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DPOL
XOE
XENABLE
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
emp
ate
e
ease
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
DCLK
DIN0
DIN9
XLATCH
DOUT0
DOUT9
DPOL
Hi-Z
Hi-Z
tsu (XENABLE–DCLK)
tsu (DIN–DCLK)
D00_A D01_A D02_A D0F_A D00_B D0D_B D0E_B D0F_B D00_C D01_CD0E_A
D90_A D91_A D92_A D9F_A D90_B D9D_B D9E_B D9F_B D90_C D91_CD9E_A
th (DIN–DCLK)
td (XOE↓–DOUT)
twl (DCLK) twh (DCLK)
th (XLATCH–DCLK)
1/f
DCLK
tsu (XLATCH–DCLK)
twh (XLATCH)
D00_A D01_A D0E_A D0F_A D00_B
D90_A D91_A D9E_A D9F_A D90_B
td (DCLK–DOUT)
th (XENABLE–DCLK)
td (XOE↑–DOUT)
ate:
–
–
DCLK
DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted with each other).
Figure 12. Timing Diagram (Shift Register for Gray Scale Data)
Page 25
BCENA
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 25
RSEL0
RSEL1
XOE
DPOL
XENABLE
DCLK
DIN0
DIN9
XLATCH
td (XOE↓–DOUT)
tsu (RSEL–XLATCH) th (RSEL–XLATCH)
tsu (RSEL–DCLK)
D0_A D0_C D0_J D0_K D0_L D0_M D0_N D0_OD0_B
D9_A
D9_C D9_J D9_K D9_L D9_M D9_N D9_OD9_B
th (XLATCH–DCLK)
tsu (RSEL–DCLK)
BCL_0–5
BCL_6–9
DOUT0
DOUT9
Default Value “1”
(Brightness Control Latch: Internal Signal)
Default Value “0”
tsu (RSEL–DOUT)
Hi-Z
Hi-Z
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
twh (XLATCH)
D<5:0>_A
D<9:6>_A
td (DCLK–DOUT)
D0_E D0_G D0_H D0_I
D0_FD0_A D0_C
D9_FD9_A D9_C D9_E D9_G D9_H D9_I
Figure 13. Timing Diagram (Shift Register for Brightness Control)
Default Value “1”
Default Value “0”
td (XOE↑–DOUT)
SLLS392 – NOVEMBER 1999
LED DRIVER
TLC5910
Page 26
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DCENA
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
emp
ate
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
RSEL0
RSEL1
tsu (RSEL–DCCLK)
DCCLK
DCDIN0
DCDIN5
XDCLAT
DCL_0–15 Default Value “1”
tsu (RSEL–XDCLAT)
D0_A
D5_A
(Note)
tsu(XENABLE–DCLK)
D0_C D0_J D0_K D0_L D0_M D0_N D0_OD0_B
D5_C D5_J D5_K D5_L D5_M D5_N D5_OD5_B
th (XDCLAT–DCCLK)
twh (XDCLAT)
Dx<15:0>_A
th (RSEL–XDCLAT)
tsu(RSEL–DCCLK)
Default Value “1”
e
ease
ate:
–
–
(Dot Correction Latch: Internal Signal: 6 bit x 16)
DCDOUT0
DCDOUT5
NOTE: Register value is immediately before DCLAT↓.
Figure 14. Timing Diagram (Shift Register for Dot Correction : Using Port B)
td (DCCLK–DCDOUT)
D0_FD0_A D0_C D0_E D0_G D0_H D0_I
D5_FD5_A D5_C D5_E D5_G D5_H D5_I
Page 27
RSEL0
RSEL1
XOE
DPOL
XENABLE
td (XOE↓–DOUT)
tsu (RSEL–XLATCH)
th (RSEL–XLATCH)
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 27
DCLK
DIN0
DIN9
XLATCH
DOUT0
DOUT5
DOUT
<9:6>
DCDOUT0
DCDOUT5
tsu (RSEL–DCLK)
D0_A D0_C D0_J D0_K D0_L D0_M D0_N D0_O
td (DCLK–DOUT)
tsu (RSEL–DOUT)
Hi-Z
Hi-Z
Hi-Z
..
.
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
D0_B
D9_B
td (DCLK–DCDOUT)
D9_C D9_J D9_K D9_L D9_M D9_N D9_OD9_A
th (XLATCH–DCLK)
twh (XLATCH)
D0_FD0_A D0_C D0_E D0_G D0_H D0_I
D5_FD5_A D5_C D5_E D5_G D5_H D5_I
D0_FD0_A D0_C D0_E D0_G D0_H D0_I
D5_FD5_A D5_C D5_E D5_G D5_H D5_I
tsu (RSEL–DCLK)
td (XOE↑–DOUT)
td (XOE↓–DOUT)
..
.
SLLS392 – NOVEMBER 1999
LED DRIVER
TLC5910
Figure 15. Timing Diagram (Shift Register for Dot Correction : Using Port A)
Page 28
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XLATCH
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
emp
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
BLANK
GSPOL
GSCLK
1/f
WDTRG
twl (WDTRG)
OUT0
OUT1
OUT15
WDT
twh (WDTRG)
td (BLANK–OUT0)
td (OUTn+1–OUTn)
tsu (XLATCH–GSCLK)
1/f
tsu (BLANK–GSCLK)
td (GSCLK–OUT0)
OFF OFF
OFF OFF
OFF OFF OFF
ON(Note A)
ON(Note A)
ON(Note A)
NOTE A: ON or OFF , or ON time is varied depend on the gray scale data and BLANK.
td (GSCLK–OUT0)
td (BLANK–OUT0)
OFF
td (OUTn+1–OUTn)
OFF
(Note A) (Note A)
GSCLK
twl (GSCLK)
twh (GSCLK)
(Note A)
(Note A) (Note A)
t
wdt
(Note A)
ate
e
ease
ate:
–
–
XDOWN1
XDOWN2
td (GSCLK–XDOWN2)
BOUT
XGSOUT
LEDCHK
GSPOL, GSCLK and XGSOUT can be replaced with signals inverted with each other.
td (BLANK–BOUT)
td (GSCLK–XGSOUT)
td (LEDCHK–XDOWN2)
HI–Z
Figure 16. Timing Diagram (Constant Current Output) – MAG0 to MAG2 are all zero
(Note B) (Note B)
NOTE B: When LED is disconnected.
td (LEDCHK–XDOWN2)
(Note B)
Page 29
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK
76
100
1,05
0,95
75
1
0,50
12,00 TYP
14,20
SQ
13,80
16,20
SQ
15,80
0,27
0,17
25
51
0,08
M
50
26
Thermal Pad
(see Note D)
0,15
0,05
0,13 NOM
Gage Plane
0,25
0°–7°
0,75
0,45
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.. The demensions of the
thermal pad are 2 mm x 2 mm. The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Seating Plane
0,08
4146929/A 04/99
29
Page 30
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1999, Texas Instruments Incorporated
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